One of the most potential energy sources in this current world is the energy of wind. It has seve... more One of the most potential energy sources in this current world is the energy of wind. It has several advantages like its renewability, cost effectiveness and sustainability make it a great source of energy. But, to predict the power generation from wind is complex process. In this paper, the effectiveness of four machine learning algorithms: random forest regressor, decision tree regressor, gradient boosting regressor, voting regressors have been used for predicting wind speed, which has direct co-relation with power production. For measuring the accuracy of these models three standard criteria namely mean square error, root mean square error and R squared have been used. In this paper, the performance and accuracy of those algorithms have been analyzed for the purpose of predicting wind speed which is one of the most important factors for wind power utilization.
Being one of the fastest-growing economies in the world, Bangladesh needs to upgrade its electric... more Being one of the fastest-growing economies in the world, Bangladesh needs to upgrade its electrical network and aim to reduce dependency on fossil fuel-based energy. For the aging and ever-expanding power network, it is necessary to have a smart substation in order to provide reliable, affordable, and sustainable electrical power. As Bangladesh is looking to integrate Distributed Generation (DG) in the power system, it is high time to think about integrating a smart distribution substation into its power network. In this paper, an investigation of the current power generation structure of Bangladesh was conducted and is described. The major focus was given to the upgradation of the existing substation and distribution setup of Bangladesh by providing suitable architectures, technologies, and communication protocols. Detailed studies of Bangladesh's prospects to incorporate the new technology and renewable energy into its power network are discussed. ETAP was used to simulate the prospective system to show the feasibility of the prospective smart distribution substation in Bangladesh's power network.
This article is an open access article distributed under the terms and conditions of the Creative... more This article is an open access article distributed under the terms and conditions of the Creative Commons Attribution (CC BY
This study proposes an 18-transistor full adder (FA) cell based on the full swing hybrid logic st... more This study proposes an 18-transistor full adder (FA) cell based on the full swing hybrid logic style. It has a first stage comprising the XOR-XNOR module followed by pass transistors and inverters to generate the sum and carry outputs. The performance evaluation of the proposed FA cell has been carried out using an HSPICE simulator at the 16 nm process node by comparing it with eight existing FAs over the supply voltage ranging from 0.4 to 1.0 V. The proposed adder achieved 34.77% improvement in propagation delay, 48.8% improvement in average power and 66.58% improvement in Power Delay Product compared to the conventional CMOS Mirror adder while operating at 0.8 V. Moreover, its performance metrics are also better than those of other latest existing adder cells. Hence, the proposed FA is suitable for modern high performance digital processors.
Engineering Science and Technology, An International Journal, 2020
A full-swing high-speed hybrid Full Adder (FA) cell based on Gate Diffusion Input (GDI) technique... more A full-swing high-speed hybrid Full Adder (FA) cell based on Gate Diffusion Input (GDI) technique and Conventional Complementary Metal-Oxide Semiconductor (CCMOS) logic has been proposed in this work. The design has been verified and compared with ten existing state-of-the-art FAs to validate its performance. Simulations were conducted using Cadence Computer Aided Design (CAD) tool in 45 nm CMOS process. The proposed design shows significant performance improvement in terms of speed and Power Delay Product (PDP). To evaluate performance parameters in large structures, the FAs have been cascaded and extended up to 32 bits. The proposed design, along with five out of ten existing designs worked flawlessly when extended to 32 bits. However, the proposed design achieved the best performance parameters in large cascaded circuits.
Indonesian Journal of Electrical Engineering and Informatics, 2020
Design of a 4-bit Carry Look-Ahead (CLA) process in static CMOS logic has been presented. CLA arc... more Design of a 4-bit Carry Look-Ahead (CLA) process in static CMOS logic has been presented. CLA architecture proposed in this work computes carry-out terms without using carry-propagate and carry-generate signals which are used in conventional static CMOS (C-CMOS) 4-bit CLA adder. Performance parameters of the proposed 4-bit CLA architecture have been simulated and validated by comparing with the conventional design using Cadence design toolset in 45 nm technology. The designs were compared in terms of average power consumption, propagation delay and power delay product (PDP). The proposed 4-bit CLA topology obtained 34.53 % improvement in speed, 4.84 % improvement in power consumption and 37.696 % improvement in PDP while the source voltage was 1.0 V. Hence, as per acquired simulation results, the proposed 4-bit CLA structure is proven to be an excellent alternative to the conventional design for data-path design in modern high-performance processors.
Full Adder (FA) circuits are integral components in the design of Arithmetic Logic Units (ALUs) o... more Full Adder (FA) circuits are integral components in the design of Arithmetic Logic Units (ALUs) of modern computing systems. Recently, there have been massive research interests in this area due to the growing need for low-power and high-performance computing systems. Researchers have proposed a variety of FA cells with diverse design techniques, each having its pros and cons. As a result, a systematic method for performance comparison of FA cells using a common simulation platform has become necessary. In this work, we present an extensive study of FA cells. We have compared the performance of thirty-three (33) existing 1-bit FA cells. The drive powers of these FA cells have been compared by applying a variety of load conditions. In addition, the 1-bit FA cells have been extended to 32-bit structures to test their scalability and to investigate their performance in wide-word structures. We have determined that twenty-one (21) of the thirty-three (33) FA cells cannot operate in a 32-bit structure, even though some of them exhibit excellent performance as a 1-bit cell. The main finding of this research is that the single-bit performance parameters of FA cells should not be considered as the main basis for performance comparison. Any FA cell should be analyzed in a multi-bit structure to determine its practical effectiveness. Article Highlights • Hybrid full adders offer better performance than single logic full adders • Many existing full adder cells are not scalable • Conventional Mirror CMOS full adder offers better performance than many recent full adders in wide adder structure
Parking allocation has become a major problem in modern cities for which numerous smart parking s... more Parking allocation has become a major problem in modern cities for which numerous smart parking systems (SPS) have been developed. This paper aims to provide comprehensive study, comparison and extensive analysis of SPSs in terms of technological approach, sensors utilized, networking technologies, user interface, computational approaches, and service provided. Moreover, the paper fills up the research gap by providing a clear insight into the suitability of SPSs in various environmental conditions and highlights their advantages/disadvantages. The extensive comparison among multiple aspects of SPSs would enable researchers, designers, and policymakers to identify the best suited SPS and understand the current trends in this sector.
Journal of Computer Science and Technology Studies, Aug 25, 2020
This paper proposes a low-cost automated traffic detection system based on image processing. Dhak... more This paper proposes a low-cost automated traffic detection system based on image processing. Dhaka is one of the crowded cities in the world with highly challenging traffic system. There is substantial lack of awareness among the drivers of transport system. As a result, citizens do not follow the rules and regulation while driving in Dhaka city. The tendency of violating the traffic regulation is noticeable throughout the country. As a result, the whole traffic system collapses very often and sometimes it ends-up with severe accidents. In recent days, the government has taken different initiatives including enlargement of pedestrian walkways, building new flyovers and foot-over bridges, expansion of existing roads. But, violation still the outcome of all these initiatives could not improve the situation significantly. The proposed system will automatically detect the traffic through live streaming video so that the detected images can be used to detect traffic violation. Later on, the law enforcement agency will be able to take necessary legal steps based on the stored information on the database.
IEEE 2019 10th International Conference on Computing, Communication and Networking Technologies (ICCCNT), 2019
This research proposes a hybrid Full Adder (FA) cell using a combination of Gate Diffusion Input ... more This research proposes a hybrid Full Adder (FA) cell using a combination of Gate Diffusion Input (GDI) technique, Transmission Gate (TG) and conventional Static CMOS (C-CMOS) logic. To test performance parameters, simulation has been conducted using Cadence Virtuoso in 65 nm technology. Moreover, a comparative analysis of the proposed design with 13 existing state of art FAs has been presented in this research to observe the performance improvements obtained by the proposed FA. In addition, the proposed and existing FAs have been cascaded to implement 4-bit, 8-bit, 16-bit and 32-bit adder to test their performance and feasibility in large structures. The proposed design exhibited remarkable performance both as single cell and cascaded mode. Besides, the proposed technique for FA design removes the defect of voltage degradation in GDI technique and low drivability of TG based design by utilizing C-CMOS logic in the output terminals.
IEEE 2019 10th International Conference on Computing, Communication and Networking Technologies (ICCCNT), 2019
A new carry generation scheme for carry out bit of a 4-bit carry look-ahead (CLA) adder is presen... more A new carry generation scheme for carry out bit of a 4-bit carry look-ahead (CLA) adder is presented. To analyze performance, proposed design for carry-out bit was implemented and verified in Cadence Virtuoso environment in 90nm technology. Performance parameters were compared with the conventional design of carry-out bit of 4-bit CLA adder. The proposed design achieved 19.69% improvement in propagation delay over the conventional CLA design. Due to low transistor count and low dynamic power dissipation, an improvement of 75.973 % was achieved in average power consumption over the conventional carry-out bit of CLA design. As a result, the obtained improvement in PDP was 79.003 %. Due to enhancements in performance parameters and reduced transistor count, the proposed CLA carry-out bit is expected to have extensive impact on overall adder performance.
Science Journal of Circuits, Systems and Signal Processing, 2019
Carry Look-Ahead Adder (CLA) is considered as one of the most widely used adder topologies which ... more Carry Look-Ahead Adder (CLA) is considered as one of the most widely used adder topologies which are used in high performance computing systems. In this research, an improved version of 4-bit CLA adder has been proposed. Performance improvement of 4-bit CLA adder has been made by using hybrid AND and XOR gates in the input side for generating carry propagate and carry generate terms. The CLA circuits are kept exactly the same as the conventional one. Performance of the proposed modified 4-bit CLA adder has been evaluated and compared with the conventional design using Cadence tools in 90 nm technology node. Performance has been evaluated and compared in terms of average power, propagation delay and power delay product. The proposed modified design exhibited significant improvement in performance while compared with the conventional one. Enhancement done by the proposed 4-bit CLA adder design in average power, propagation delay and PDP were 14.96%, 11.76% and 25.32% respectively. In addition to performance enhancement, transistor count require for the proposed design is quite less compared to the conventional design which result in less surface area on chip. Moreover, less transistor count accounts for less power dissipation. Hence, utilizing the proposed design in modern high-performance computing systems would bring about high-performance improvements.
IEEE 2018 4th International Conference on Computing Communication and Automation (ICCCA), 2018
Full Adders considered as the major component in Arithmetic Logic Unit of digital signal processi... more Full Adders considered as the major component in Arithmetic Logic Unit of digital signal processing chips and microprocessors gained much interest among researchers over the years. As a result, various adder cells have been developed by employing various logic styles. Therefore, it is necessary to have a complete overview of the various sorts of full adders to figure out their performance level. This paper presents an overview and comparative analysis of different sorts of full adder cells. Analysis and simulation on Complementary Pass Logic, Complementary CMOS, Transmission Gate, Transmission Function, 24 Transistor, 14 Transistor, 10 Transistor, Swing Restored Complementary Pass Logic, Hybrid Pass Static CMOS, Double Pass Transistor and some Hybrid full adder cells have been conducted using Cadence Virtuoso Tools in 90nm technology. It was observed that Complementary Pass Logic adder cell had the least delay and 14-Transistor adder cell displayed the worst delay. Hybrid Pass Static CMOS full adder had the least power consumption whereas 24 Transistor full adder consumed highest power. Highest power-delay product was displayed by Double Pass Transistor Logic adder cell.
IEEE 2018 Fourth International Conference on Research in Computational Intelligence and Communication Networks (ICRCICN), 2018
Smart Home Systems have achieved great interest in the recent years to make people's life easier ... more Smart Home Systems have achieved great interest in the recent years to make people's life easier and more comfortable. Smart home system offers people to control home environment in efficient and comfortable manner. Technological advancement in recent years resulted in producing a large number of smart and sophisticated systems which promoted smart living technology. This paper presents complete analysis of various smart and intelligent home automation systems. Comparative analysis of existing smart home system has been made which provides a clear idea of the pros and cons of the existing systems. Working principle of different types of smart home systems such as Dual Tone Multi Frequency based, Global System for Mobile based, voice recognition based, Zigbee based, Bluetooth based, Internet and Wi-fi based, and Gesture based smart home systems has been studied. Comments according to different aspects and features have been made for the studied smart home systems which enable users to select suitable technology according to budget and needs.
IEEE 2018 Fifth HCT Information Technology Trends (ITT), 2018
This paper introduces a low-cost android application (app) controlled smart home system that can ... more This paper introduces a low-cost android application (app) controlled smart home system that can remotely switch on/off as many as 208 appliances using only 4 digital pins of an ATmega328 microcontroller based Arduino UNO board. The appliance switching system requires approximately 70% less wiring cost for real life installation in home compared to the similar conventional systems. Moreover, the smart home system includes: (1) automatic night light that only lights up at night if it detects any human in the close proximity; (2) 'Outside Mode' that turns off every single appliance connected to the system with a touch from android app when user leaves the home; (3) a smart security system that sounds an alarm, sends message and makes call to the user using GSM module if it detects any intrusion in the house. The android application provides a user-friendly Graphical User Interface (GUI) to send command to the microcontroller via Bluetooth. Compared to the products available in market, cost of the proposed system is cheaper to a great extent.
Unauthorized entry in restricted areas represents an obvious security issue. Therefore, strict mo... more Unauthorized entry in restricted areas represents an obvious security issue. Therefore, strict monitoring is highly required in order to ensure security. This research presents a smart surveillance bot for highly restricted areas with (1) automatic surveillance of an area specified by the user and obstacle detection and avoidance using Ultrasonic Sensor (2) human detection using Infrared (IR) thermal camera and identification of friend or foe (IFF) using RFID tags (3) live video surveillance using camera and manual remote control mode. The bot has the ability to detect human presence in an area using thermal image processing. If the bot detects and human presence while operating in surveillance mode, it confirms whether the person is a friend or foe by reading RFID. If the bot identifies the person as foe, it automatically sends the user a notification of intrusion and turns on live video streaming. The user would be able to take total control of the bot remotely in order to verify and judge on the situation using live video streaming. It also exhibits warning message in its display and points a toy gun at the intruder. In real life cases, the toy gun can be replaced with actual ones. The user bears the authority to decide whether to shoot or not. Due to having tank rover chassis, the robot has the ability to maneuver in rough terrains which enhances its versatility and usability.
International Journal of Sensors and Sensor Networks, 2019
As technological advancement in recent years is bringing ease to our everyday life, smart home sy... more As technological advancement in recent years is bringing ease to our everyday life, smart home systems based on wireless networks and sensors are rapidly gaining importance. Research on microcontroller controller smart home systems has become popular due to its low cost and reliability. However, appliance switching capacity of microcontroller is quite low which limits the widespread use of such sort of systems. This paper introduces an external appliance switching circuit for microcontroller controller automated home which has the ability to control 208 appliances. This large appliance switching capability has been obtained by demultiplexing digital signals obtained from microcontroller board using a complex array of 4 to 16 line decoders. The proposed appliance switching circuit can be implemented with 60-70% less wiring cost in real time compared to the typical wiring technique in microcontroller controlled smart homes. Also, hardware implementation expenditure in this research has been reduced significantly compared to the existing designs. Moreover, the issue associated with existing microcontroller appliance switching scheme in case of incorporating manual switch has been solved. The proposed circuit is incorporated with a smart phone application by which the user sends commands to the microcontroller board using Bluetooth as the medium of wireless transfer. The proposed microcontroller controlled smart home system with external appliance switching circuit is quite cheaper than the existing systems which allows consumers to afford smart living with limited budget. Due to reduction of implementation cost and solution of major technical design issues incorporated with the existing microcontroller-based system been solved in this research work, microcontroller based smart home systems is expected to become a potential product in the market in near future.
One of the most potential energy sources in this current world is the energy of wind. It has seve... more One of the most potential energy sources in this current world is the energy of wind. It has several advantages like its renewability, cost effectiveness and sustainability make it a great source of energy. But, to predict the power generation from wind is complex process. In this paper, the effectiveness of four machine learning algorithms: random forest regressor, decision tree regressor, gradient boosting regressor, voting regressors have been used for predicting wind speed, which has direct co-relation with power production. For measuring the accuracy of these models three standard criteria namely mean square error, root mean square error and R squared have been used. In this paper, the performance and accuracy of those algorithms have been analyzed for the purpose of predicting wind speed which is one of the most important factors for wind power utilization.
Being one of the fastest-growing economies in the world, Bangladesh needs to upgrade its electric... more Being one of the fastest-growing economies in the world, Bangladesh needs to upgrade its electrical network and aim to reduce dependency on fossil fuel-based energy. For the aging and ever-expanding power network, it is necessary to have a smart substation in order to provide reliable, affordable, and sustainable electrical power. As Bangladesh is looking to integrate Distributed Generation (DG) in the power system, it is high time to think about integrating a smart distribution substation into its power network. In this paper, an investigation of the current power generation structure of Bangladesh was conducted and is described. The major focus was given to the upgradation of the existing substation and distribution setup of Bangladesh by providing suitable architectures, technologies, and communication protocols. Detailed studies of Bangladesh's prospects to incorporate the new technology and renewable energy into its power network are discussed. ETAP was used to simulate the prospective system to show the feasibility of the prospective smart distribution substation in Bangladesh's power network.
This article is an open access article distributed under the terms and conditions of the Creative... more This article is an open access article distributed under the terms and conditions of the Creative Commons Attribution (CC BY
This study proposes an 18-transistor full adder (FA) cell based on the full swing hybrid logic st... more This study proposes an 18-transistor full adder (FA) cell based on the full swing hybrid logic style. It has a first stage comprising the XOR-XNOR module followed by pass transistors and inverters to generate the sum and carry outputs. The performance evaluation of the proposed FA cell has been carried out using an HSPICE simulator at the 16 nm process node by comparing it with eight existing FAs over the supply voltage ranging from 0.4 to 1.0 V. The proposed adder achieved 34.77% improvement in propagation delay, 48.8% improvement in average power and 66.58% improvement in Power Delay Product compared to the conventional CMOS Mirror adder while operating at 0.8 V. Moreover, its performance metrics are also better than those of other latest existing adder cells. Hence, the proposed FA is suitable for modern high performance digital processors.
Engineering Science and Technology, An International Journal, 2020
A full-swing high-speed hybrid Full Adder (FA) cell based on Gate Diffusion Input (GDI) technique... more A full-swing high-speed hybrid Full Adder (FA) cell based on Gate Diffusion Input (GDI) technique and Conventional Complementary Metal-Oxide Semiconductor (CCMOS) logic has been proposed in this work. The design has been verified and compared with ten existing state-of-the-art FAs to validate its performance. Simulations were conducted using Cadence Computer Aided Design (CAD) tool in 45 nm CMOS process. The proposed design shows significant performance improvement in terms of speed and Power Delay Product (PDP). To evaluate performance parameters in large structures, the FAs have been cascaded and extended up to 32 bits. The proposed design, along with five out of ten existing designs worked flawlessly when extended to 32 bits. However, the proposed design achieved the best performance parameters in large cascaded circuits.
Indonesian Journal of Electrical Engineering and Informatics, 2020
Design of a 4-bit Carry Look-Ahead (CLA) process in static CMOS logic has been presented. CLA arc... more Design of a 4-bit Carry Look-Ahead (CLA) process in static CMOS logic has been presented. CLA architecture proposed in this work computes carry-out terms without using carry-propagate and carry-generate signals which are used in conventional static CMOS (C-CMOS) 4-bit CLA adder. Performance parameters of the proposed 4-bit CLA architecture have been simulated and validated by comparing with the conventional design using Cadence design toolset in 45 nm technology. The designs were compared in terms of average power consumption, propagation delay and power delay product (PDP). The proposed 4-bit CLA topology obtained 34.53 % improvement in speed, 4.84 % improvement in power consumption and 37.696 % improvement in PDP while the source voltage was 1.0 V. Hence, as per acquired simulation results, the proposed 4-bit CLA structure is proven to be an excellent alternative to the conventional design for data-path design in modern high-performance processors.
Full Adder (FA) circuits are integral components in the design of Arithmetic Logic Units (ALUs) o... more Full Adder (FA) circuits are integral components in the design of Arithmetic Logic Units (ALUs) of modern computing systems. Recently, there have been massive research interests in this area due to the growing need for low-power and high-performance computing systems. Researchers have proposed a variety of FA cells with diverse design techniques, each having its pros and cons. As a result, a systematic method for performance comparison of FA cells using a common simulation platform has become necessary. In this work, we present an extensive study of FA cells. We have compared the performance of thirty-three (33) existing 1-bit FA cells. The drive powers of these FA cells have been compared by applying a variety of load conditions. In addition, the 1-bit FA cells have been extended to 32-bit structures to test their scalability and to investigate their performance in wide-word structures. We have determined that twenty-one (21) of the thirty-three (33) FA cells cannot operate in a 32-bit structure, even though some of them exhibit excellent performance as a 1-bit cell. The main finding of this research is that the single-bit performance parameters of FA cells should not be considered as the main basis for performance comparison. Any FA cell should be analyzed in a multi-bit structure to determine its practical effectiveness. Article Highlights • Hybrid full adders offer better performance than single logic full adders • Many existing full adder cells are not scalable • Conventional Mirror CMOS full adder offers better performance than many recent full adders in wide adder structure
Parking allocation has become a major problem in modern cities for which numerous smart parking s... more Parking allocation has become a major problem in modern cities for which numerous smart parking systems (SPS) have been developed. This paper aims to provide comprehensive study, comparison and extensive analysis of SPSs in terms of technological approach, sensors utilized, networking technologies, user interface, computational approaches, and service provided. Moreover, the paper fills up the research gap by providing a clear insight into the suitability of SPSs in various environmental conditions and highlights their advantages/disadvantages. The extensive comparison among multiple aspects of SPSs would enable researchers, designers, and policymakers to identify the best suited SPS and understand the current trends in this sector.
Journal of Computer Science and Technology Studies, Aug 25, 2020
This paper proposes a low-cost automated traffic detection system based on image processing. Dhak... more This paper proposes a low-cost automated traffic detection system based on image processing. Dhaka is one of the crowded cities in the world with highly challenging traffic system. There is substantial lack of awareness among the drivers of transport system. As a result, citizens do not follow the rules and regulation while driving in Dhaka city. The tendency of violating the traffic regulation is noticeable throughout the country. As a result, the whole traffic system collapses very often and sometimes it ends-up with severe accidents. In recent days, the government has taken different initiatives including enlargement of pedestrian walkways, building new flyovers and foot-over bridges, expansion of existing roads. But, violation still the outcome of all these initiatives could not improve the situation significantly. The proposed system will automatically detect the traffic through live streaming video so that the detected images can be used to detect traffic violation. Later on, the law enforcement agency will be able to take necessary legal steps based on the stored information on the database.
IEEE 2019 10th International Conference on Computing, Communication and Networking Technologies (ICCCNT), 2019
This research proposes a hybrid Full Adder (FA) cell using a combination of Gate Diffusion Input ... more This research proposes a hybrid Full Adder (FA) cell using a combination of Gate Diffusion Input (GDI) technique, Transmission Gate (TG) and conventional Static CMOS (C-CMOS) logic. To test performance parameters, simulation has been conducted using Cadence Virtuoso in 65 nm technology. Moreover, a comparative analysis of the proposed design with 13 existing state of art FAs has been presented in this research to observe the performance improvements obtained by the proposed FA. In addition, the proposed and existing FAs have been cascaded to implement 4-bit, 8-bit, 16-bit and 32-bit adder to test their performance and feasibility in large structures. The proposed design exhibited remarkable performance both as single cell and cascaded mode. Besides, the proposed technique for FA design removes the defect of voltage degradation in GDI technique and low drivability of TG based design by utilizing C-CMOS logic in the output terminals.
IEEE 2019 10th International Conference on Computing, Communication and Networking Technologies (ICCCNT), 2019
A new carry generation scheme for carry out bit of a 4-bit carry look-ahead (CLA) adder is presen... more A new carry generation scheme for carry out bit of a 4-bit carry look-ahead (CLA) adder is presented. To analyze performance, proposed design for carry-out bit was implemented and verified in Cadence Virtuoso environment in 90nm technology. Performance parameters were compared with the conventional design of carry-out bit of 4-bit CLA adder. The proposed design achieved 19.69% improvement in propagation delay over the conventional CLA design. Due to low transistor count and low dynamic power dissipation, an improvement of 75.973 % was achieved in average power consumption over the conventional carry-out bit of CLA design. As a result, the obtained improvement in PDP was 79.003 %. Due to enhancements in performance parameters and reduced transistor count, the proposed CLA carry-out bit is expected to have extensive impact on overall adder performance.
Science Journal of Circuits, Systems and Signal Processing, 2019
Carry Look-Ahead Adder (CLA) is considered as one of the most widely used adder topologies which ... more Carry Look-Ahead Adder (CLA) is considered as one of the most widely used adder topologies which are used in high performance computing systems. In this research, an improved version of 4-bit CLA adder has been proposed. Performance improvement of 4-bit CLA adder has been made by using hybrid AND and XOR gates in the input side for generating carry propagate and carry generate terms. The CLA circuits are kept exactly the same as the conventional one. Performance of the proposed modified 4-bit CLA adder has been evaluated and compared with the conventional design using Cadence tools in 90 nm technology node. Performance has been evaluated and compared in terms of average power, propagation delay and power delay product. The proposed modified design exhibited significant improvement in performance while compared with the conventional one. Enhancement done by the proposed 4-bit CLA adder design in average power, propagation delay and PDP were 14.96%, 11.76% and 25.32% respectively. In addition to performance enhancement, transistor count require for the proposed design is quite less compared to the conventional design which result in less surface area on chip. Moreover, less transistor count accounts for less power dissipation. Hence, utilizing the proposed design in modern high-performance computing systems would bring about high-performance improvements.
IEEE 2018 4th International Conference on Computing Communication and Automation (ICCCA), 2018
Full Adders considered as the major component in Arithmetic Logic Unit of digital signal processi... more Full Adders considered as the major component in Arithmetic Logic Unit of digital signal processing chips and microprocessors gained much interest among researchers over the years. As a result, various adder cells have been developed by employing various logic styles. Therefore, it is necessary to have a complete overview of the various sorts of full adders to figure out their performance level. This paper presents an overview and comparative analysis of different sorts of full adder cells. Analysis and simulation on Complementary Pass Logic, Complementary CMOS, Transmission Gate, Transmission Function, 24 Transistor, 14 Transistor, 10 Transistor, Swing Restored Complementary Pass Logic, Hybrid Pass Static CMOS, Double Pass Transistor and some Hybrid full adder cells have been conducted using Cadence Virtuoso Tools in 90nm technology. It was observed that Complementary Pass Logic adder cell had the least delay and 14-Transistor adder cell displayed the worst delay. Hybrid Pass Static CMOS full adder had the least power consumption whereas 24 Transistor full adder consumed highest power. Highest power-delay product was displayed by Double Pass Transistor Logic adder cell.
IEEE 2018 Fourth International Conference on Research in Computational Intelligence and Communication Networks (ICRCICN), 2018
Smart Home Systems have achieved great interest in the recent years to make people's life easier ... more Smart Home Systems have achieved great interest in the recent years to make people's life easier and more comfortable. Smart home system offers people to control home environment in efficient and comfortable manner. Technological advancement in recent years resulted in producing a large number of smart and sophisticated systems which promoted smart living technology. This paper presents complete analysis of various smart and intelligent home automation systems. Comparative analysis of existing smart home system has been made which provides a clear idea of the pros and cons of the existing systems. Working principle of different types of smart home systems such as Dual Tone Multi Frequency based, Global System for Mobile based, voice recognition based, Zigbee based, Bluetooth based, Internet and Wi-fi based, and Gesture based smart home systems has been studied. Comments according to different aspects and features have been made for the studied smart home systems which enable users to select suitable technology according to budget and needs.
IEEE 2018 Fifth HCT Information Technology Trends (ITT), 2018
This paper introduces a low-cost android application (app) controlled smart home system that can ... more This paper introduces a low-cost android application (app) controlled smart home system that can remotely switch on/off as many as 208 appliances using only 4 digital pins of an ATmega328 microcontroller based Arduino UNO board. The appliance switching system requires approximately 70% less wiring cost for real life installation in home compared to the similar conventional systems. Moreover, the smart home system includes: (1) automatic night light that only lights up at night if it detects any human in the close proximity; (2) 'Outside Mode' that turns off every single appliance connected to the system with a touch from android app when user leaves the home; (3) a smart security system that sounds an alarm, sends message and makes call to the user using GSM module if it detects any intrusion in the house. The android application provides a user-friendly Graphical User Interface (GUI) to send command to the microcontroller via Bluetooth. Compared to the products available in market, cost of the proposed system is cheaper to a great extent.
Unauthorized entry in restricted areas represents an obvious security issue. Therefore, strict mo... more Unauthorized entry in restricted areas represents an obvious security issue. Therefore, strict monitoring is highly required in order to ensure security. This research presents a smart surveillance bot for highly restricted areas with (1) automatic surveillance of an area specified by the user and obstacle detection and avoidance using Ultrasonic Sensor (2) human detection using Infrared (IR) thermal camera and identification of friend or foe (IFF) using RFID tags (3) live video surveillance using camera and manual remote control mode. The bot has the ability to detect human presence in an area using thermal image processing. If the bot detects and human presence while operating in surveillance mode, it confirms whether the person is a friend or foe by reading RFID. If the bot identifies the person as foe, it automatically sends the user a notification of intrusion and turns on live video streaming. The user would be able to take total control of the bot remotely in order to verify and judge on the situation using live video streaming. It also exhibits warning message in its display and points a toy gun at the intruder. In real life cases, the toy gun can be replaced with actual ones. The user bears the authority to decide whether to shoot or not. Due to having tank rover chassis, the robot has the ability to maneuver in rough terrains which enhances its versatility and usability.
International Journal of Sensors and Sensor Networks, 2019
As technological advancement in recent years is bringing ease to our everyday life, smart home sy... more As technological advancement in recent years is bringing ease to our everyday life, smart home systems based on wireless networks and sensors are rapidly gaining importance. Research on microcontroller controller smart home systems has become popular due to its low cost and reliability. However, appliance switching capacity of microcontroller is quite low which limits the widespread use of such sort of systems. This paper introduces an external appliance switching circuit for microcontroller controller automated home which has the ability to control 208 appliances. This large appliance switching capability has been obtained by demultiplexing digital signals obtained from microcontroller board using a complex array of 4 to 16 line decoders. The proposed appliance switching circuit can be implemented with 60-70% less wiring cost in real time compared to the typical wiring technique in microcontroller controlled smart homes. Also, hardware implementation expenditure in this research has been reduced significantly compared to the existing designs. Moreover, the issue associated with existing microcontroller appliance switching scheme in case of incorporating manual switch has been solved. The proposed circuit is incorporated with a smart phone application by which the user sends commands to the microcontroller board using Bluetooth as the medium of wireless transfer. The proposed microcontroller controlled smart home system with external appliance switching circuit is quite cheaper than the existing systems which allows consumers to afford smart living with limited budget. Due to reduction of implementation cost and solution of major technical design issues incorporated with the existing microcontroller-based system been solved in this research work, microcontroller based smart home systems is expected to become a potential product in the market in near future.
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