The authors deal with the design and performance analysis of two real-time speech coder algorithm... more The authors deal with the design and performance analysis of two real-time speech coder algorithms implemented on an array processor, i.e., a linear predictive coder (LPC) operating at 2.4 kb/s, and a baseband residual coder (BBC) operating at 7.2/9.6 kb/s. The effects of channel impairments typical of mobile satellite systems, such as multipath fading and shadowing, on the subjective quality
Proceedings. Electrotechnical Conference Integrating Research, Industry and Education in Energy and Communication Engineering', 1989
The architecture and the design of an interface for a 260 Mb/s CSMA-CD (carrier sense multiple ac... more The architecture and the design of an interface for a 260 Mb/s CSMA-CD (carrier sense multiple access with collision detection) multichannel local area network (M-LAN) are presented. The interface prototype is described, showing the feasibility of M-LANs at reasonable costs. It is shown that such an interface can be implemented using available and inexpensive technologies. Particular attention was paid to flexibility, as the interface prototype should allow the experimental testing of a wide class of protocols under different conditions
ABSTRACT The performance of combined coding and modulation schemes in channels with intersymbol i... more ABSTRACT The performance of combined coding and modulation schemes in channels with intersymbol interference and nonlinearities is studied using an analytical approach. The class of possible receivers is presented, and a generalization of the minimum Euclidean distance used for the asymptotic analysis of the performance of combined coding and modulation schemes on AWGN channels is introduced. Numerical results are presented for coded 16-PSK modulation.
IEEE TENCON'90: 1990 IEEE Region 10 Conference on Computer and Communication Systems. Conference Proceedings, 1990
A high speed packet switch based on VLSI chips and optical components is presented. The chips, lo... more A high speed packet switch based on VLSI chips and optical components is presented. The chips, located at the inputs of the switch, implement the routing algorithm, store the incoming packets, and control the access to the optical interconnection network, which connects inputs and outputs. The simulation showed that up to two packets at a time must be transmitted on the optical interconnection network from any input to achieve optimal performance. The impact of this result on the chip complexity and on the transmission scheme used in the optical part is discussed, and a possible solution is outlined
[1991] Proceedings, Advanced Computer Technology, Reliable Systems and Applications, 1991
The performance of deflection networks (extension of Manhattan Street network) under bursty traff... more The performance of deflection networks (extension of Manhattan Street network) under bursty traffic has been analyzed assuming the use of a preference routing algorithm. The throughput performance under these conditions has proven to be almost independent from the burstiness of the traffic. Packets of a single burst are often received in the wrong alignment. Analyses simulating the generation of bursts
ABSTRACT The design of a deflection network node is presented. Users can access the network via a... more ABSTRACT The design of a deflection network node is presented. Users can access the network via a bidirectional parallel port or through an interface to a local area network. The characteristics of the devices implementing the different functions and their interconnection are taken into consideration. One of the most critical steps is the design of a dedicated VLSI chip performing the switching function; this aspect is also outlined
IEEE INFCOM '91. The conference on Computer Communications. Tenth Annual Joint Comference of the IEEE Computer and Communications Societies Proceedings, 1991
ABSTRACT The architecture of a high speed packet switch for an ATM system is presented. The switc... more ABSTRACT The architecture of a high speed packet switch for an ATM system is presented. The switch is based on input electronic modules, where the incoming packets are processed and buffered, and on an optical interconnection network, connecting the inputs to the outputs. During each slot each output can receive a single packet, and each input can transmit up to L packets. A reservation mechanism avoids collisions on the optical network, implementing a series of distributed queues. The switch performance was studied by simulation. The effect of the input switching capacity L on the performance is discussed
Proceedings ISCC 2002 Seventh International Symposium on Computers and Communications, 2002
ABSTRACT The simulation of complex telecommunication systems, such as satellite-based networks, i... more ABSTRACT The simulation of complex telecommunication systems, such as satellite-based networks, is seldom sufficient to understand fully their real behavior and to evaluate the quality of service (QoS) perceived by their users. The mean opinion score (MOS) method, widely used to evaluate the perceived QoS, requires the use of a working system, and this is usually not the case for satellites, when studying new protocols and/or new system architectures. A simulator able to replicate in real time the behavior of the system under examination would be very useful: we call it an emulator. This paper describes an emulator for IP data traffic on a single beam GEO satellite, with TDM/TDMA radio links and on-board circuit switch. The emulator has been implemented in the CNIT Radio Communication Laboratory at Politecnico di Torino.
[1991 Proceedings] Tenth Annual International Phoenix Conference on Computers and Communications, 1991
ABSTRACT The architecture of an electro-optical packet switch is outlined. Electronic circuits ar... more ABSTRACT The architecture of an electro-optical packet switch is outlined. Electronic circuits are used for buffering and control at the switch inputs. The switch outputs do not require logic circuits or buffers, but are simple regenerative repeaters. An optical interconnection network links inputs and outputs. A novel feature of the proposed architecture is the capability to transmit from each input unit up to two packets simultaneously. This proves the reliability of the equipment. Its simulation, when loaded with homogeneous traffic, showed that when input modules are allowed to transmit up to two packets at a time the performance approaches the optimum value. The implementation of the switch with today's technology is briefly discussed
SBT/IEEE International Symposium on Telecommunications, 1990
A packet switch based on electrooptical technologies is presented. It is composed of N VLSI chips... more A packet switch based on electrooptical technologies is presented. It is composed of N VLSI chips which interface the input and output links with the internal optical interconnection network. Its simulation, when loaded with homogeneous input and output traffic, showed that two packets at a time must be first extracted from each input buffer and then transmitted on the optical interconnection network to achieve an almost optimal performance. This significantly affects both the architecture of the VLSI chips and the optical transmission scheme
International Zurich Seminar on Digital Communications, Electronic Circuits and Systems for Communications., 1990
ABSTRACT The performance of a network based on an optical star is discussed. Destination nodes ar... more ABSTRACT The performance of a network based on an optical star is discussed. Destination nodes are addressed by directly sending the information on the channel reserved to that node. Simulation of the network shows that the throughput-delay characteristic is dramatically affected by the output capabilities of the network nodes, i.e., by the number of packets they can simultaneously send. In particular, nodes able to transmit two packets at the same time represent a good tradeoff between cost and performance. Wavelength division multiplexing and code division multiplexing techniques can be combined to implement the network. This, in turn, requires new integrated components for a single-chip implementation of transmitters and receivers
[Conference Record] SUPERCOMM/ICC '92 Discovering a New World of Communications, 1992
ABSTRACT The first implementation of a laboratory prototype of a deflection network, named D-Net,... more ABSTRACT The first implementation of a laboratory prototype of a deflection network, named D-Net, is discussed. The performance of some network topologies suited for deflection networks is summarized. The architecture of the network nodes is reviewed. In particular, the microcontroller and the other commercially available devices constituting the node are described, and the structure of a custom chip implementing the switching fabric is outlined. A possible application of the network is explained
8th European Conference on Electrotechnics, Conference Proceedings on Area Communication, 1988
ABSTRACT The problem of the integration of data and voice on the same LAN (local area network) is... more ABSTRACT The problem of the integration of data and voice on the same LAN (local area network) is investigated. Some advanced telephone services that can be implemented on LANs are presented. In particular, conference service here named multiple internal call, is investigated. Other services, such as the call queue or the bypass, which can be considered as typical services of the office of the near future, are described
The authors deal with the design and performance analysis of two real-time speech coder algorithm... more The authors deal with the design and performance analysis of two real-time speech coder algorithms implemented on an array processor, i.e., a linear predictive coder (LPC) operating at 2.4 kb/s, and a baseband residual coder (BBC) operating at 7.2/9.6 kb/s. The effects of channel impairments typical of mobile satellite systems, such as multipath fading and shadowing, on the subjective quality
Proceedings. Electrotechnical Conference Integrating Research, Industry and Education in Energy and Communication Engineering', 1989
The architecture and the design of an interface for a 260 Mb/s CSMA-CD (carrier sense multiple ac... more The architecture and the design of an interface for a 260 Mb/s CSMA-CD (carrier sense multiple access with collision detection) multichannel local area network (M-LAN) are presented. The interface prototype is described, showing the feasibility of M-LANs at reasonable costs. It is shown that such an interface can be implemented using available and inexpensive technologies. Particular attention was paid to flexibility, as the interface prototype should allow the experimental testing of a wide class of protocols under different conditions
ABSTRACT The performance of combined coding and modulation schemes in channels with intersymbol i... more ABSTRACT The performance of combined coding and modulation schemes in channels with intersymbol interference and nonlinearities is studied using an analytical approach. The class of possible receivers is presented, and a generalization of the minimum Euclidean distance used for the asymptotic analysis of the performance of combined coding and modulation schemes on AWGN channels is introduced. Numerical results are presented for coded 16-PSK modulation.
IEEE TENCON'90: 1990 IEEE Region 10 Conference on Computer and Communication Systems. Conference Proceedings, 1990
A high speed packet switch based on VLSI chips and optical components is presented. The chips, lo... more A high speed packet switch based on VLSI chips and optical components is presented. The chips, located at the inputs of the switch, implement the routing algorithm, store the incoming packets, and control the access to the optical interconnection network, which connects inputs and outputs. The simulation showed that up to two packets at a time must be transmitted on the optical interconnection network from any input to achieve optimal performance. The impact of this result on the chip complexity and on the transmission scheme used in the optical part is discussed, and a possible solution is outlined
[1991] Proceedings, Advanced Computer Technology, Reliable Systems and Applications, 1991
The performance of deflection networks (extension of Manhattan Street network) under bursty traff... more The performance of deflection networks (extension of Manhattan Street network) under bursty traffic has been analyzed assuming the use of a preference routing algorithm. The throughput performance under these conditions has proven to be almost independent from the burstiness of the traffic. Packets of a single burst are often received in the wrong alignment. Analyses simulating the generation of bursts
ABSTRACT The design of a deflection network node is presented. Users can access the network via a... more ABSTRACT The design of a deflection network node is presented. Users can access the network via a bidirectional parallel port or through an interface to a local area network. The characteristics of the devices implementing the different functions and their interconnection are taken into consideration. One of the most critical steps is the design of a dedicated VLSI chip performing the switching function; this aspect is also outlined
IEEE INFCOM '91. The conference on Computer Communications. Tenth Annual Joint Comference of the IEEE Computer and Communications Societies Proceedings, 1991
ABSTRACT The architecture of a high speed packet switch for an ATM system is presented. The switc... more ABSTRACT The architecture of a high speed packet switch for an ATM system is presented. The switch is based on input electronic modules, where the incoming packets are processed and buffered, and on an optical interconnection network, connecting the inputs to the outputs. During each slot each output can receive a single packet, and each input can transmit up to L packets. A reservation mechanism avoids collisions on the optical network, implementing a series of distributed queues. The switch performance was studied by simulation. The effect of the input switching capacity L on the performance is discussed
Proceedings ISCC 2002 Seventh International Symposium on Computers and Communications, 2002
ABSTRACT The simulation of complex telecommunication systems, such as satellite-based networks, i... more ABSTRACT The simulation of complex telecommunication systems, such as satellite-based networks, is seldom sufficient to understand fully their real behavior and to evaluate the quality of service (QoS) perceived by their users. The mean opinion score (MOS) method, widely used to evaluate the perceived QoS, requires the use of a working system, and this is usually not the case for satellites, when studying new protocols and/or new system architectures. A simulator able to replicate in real time the behavior of the system under examination would be very useful: we call it an emulator. This paper describes an emulator for IP data traffic on a single beam GEO satellite, with TDM/TDMA radio links and on-board circuit switch. The emulator has been implemented in the CNIT Radio Communication Laboratory at Politecnico di Torino.
[1991 Proceedings] Tenth Annual International Phoenix Conference on Computers and Communications, 1991
ABSTRACT The architecture of an electro-optical packet switch is outlined. Electronic circuits ar... more ABSTRACT The architecture of an electro-optical packet switch is outlined. Electronic circuits are used for buffering and control at the switch inputs. The switch outputs do not require logic circuits or buffers, but are simple regenerative repeaters. An optical interconnection network links inputs and outputs. A novel feature of the proposed architecture is the capability to transmit from each input unit up to two packets simultaneously. This proves the reliability of the equipment. Its simulation, when loaded with homogeneous traffic, showed that when input modules are allowed to transmit up to two packets at a time the performance approaches the optimum value. The implementation of the switch with today's technology is briefly discussed
SBT/IEEE International Symposium on Telecommunications, 1990
A packet switch based on electrooptical technologies is presented. It is composed of N VLSI chips... more A packet switch based on electrooptical technologies is presented. It is composed of N VLSI chips which interface the input and output links with the internal optical interconnection network. Its simulation, when loaded with homogeneous input and output traffic, showed that two packets at a time must be first extracted from each input buffer and then transmitted on the optical interconnection network to achieve an almost optimal performance. This significantly affects both the architecture of the VLSI chips and the optical transmission scheme
International Zurich Seminar on Digital Communications, Electronic Circuits and Systems for Communications., 1990
ABSTRACT The performance of a network based on an optical star is discussed. Destination nodes ar... more ABSTRACT The performance of a network based on an optical star is discussed. Destination nodes are addressed by directly sending the information on the channel reserved to that node. Simulation of the network shows that the throughput-delay characteristic is dramatically affected by the output capabilities of the network nodes, i.e., by the number of packets they can simultaneously send. In particular, nodes able to transmit two packets at the same time represent a good tradeoff between cost and performance. Wavelength division multiplexing and code division multiplexing techniques can be combined to implement the network. This, in turn, requires new integrated components for a single-chip implementation of transmitters and receivers
[Conference Record] SUPERCOMM/ICC '92 Discovering a New World of Communications, 1992
ABSTRACT The first implementation of a laboratory prototype of a deflection network, named D-Net,... more ABSTRACT The first implementation of a laboratory prototype of a deflection network, named D-Net, is discussed. The performance of some network topologies suited for deflection networks is summarized. The architecture of the network nodes is reviewed. In particular, the microcontroller and the other commercially available devices constituting the node are described, and the structure of a custom chip implementing the switching fabric is outlined. A possible application of the network is explained
8th European Conference on Electrotechnics, Conference Proceedings on Area Communication, 1988
ABSTRACT The problem of the integration of data and voice on the same LAN (local area network) is... more ABSTRACT The problem of the integration of data and voice on the same LAN (local area network) is investigated. Some advanced telephone services that can be implemented on LANs are presented. In particular, conference service here named multiple internal call, is investigated. Other services, such as the call queue or the bypass, which can be considered as typical services of the office of the near future, are described
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Papers by G. Albertengo