Due to continuous advances in technology scaling, modern integrated circuits consist of billions ... more Due to continuous advances in technology scaling, modern integrated circuits consist of billions of transistors. Interconnects between the gates in these transistors were
considered as ideal conductors that propagated signals
instantaneously. While device sizes were shrinking with each
technology generation, multilevel metal structures rose higher
and higher above the surface of the silicon and soon began to
dominate the landscape of the integrated circuit. In the sub
100nm scaling regime, interconnect behavior limits the
performance and correctness of VLSI systems. The wiring in
today’s integrated circuits forms a complex geometry that
introduces capacitive, resistive, and inductive parasitics. They
can cause an increase in propagation delay, impact on energy
dissipation and the power distribution and introduce extra noise sources, which affects the reliability of the circuit. As the device size scales down the impact of interconnect in the VLSI circuits became even more significant. The performance of copper interconnects tend to get reduced in the sub 100nm range and hence we need to examine for other interconnect via options. Single Wall Carbon Nanotubes exhibit better performance in sub 100nm processing technology due to their very large current carrying capacity and large electron mean free paths. Initially we have analyzed the performances of a copper based CMOS inverter for 32nm technology node. SPICE simulations were carried out to validate the results and the results show improved performance of CNT interconnects in terms of power and delay time in comparison to traditional copper based interconnects. This work suggests using Single Wall Carbon Nanotubes (SWCNT) as interconnects for global interconnects in VLSI design as they consume less energy and gives more throughput and bandwidth when compared with traditional Copper wires.
Due to continuous advances in technology scaling, modern integrated circuits consist of billions ... more Due to continuous advances in technology scaling, modern integrated circuits consist of billions of transistors. Interconnects between the gates in these transistors were
considered as ideal conductors that propagated signals
instantaneously. While device sizes were shrinking with each
technology generation, multilevel metal structures rose higher
and higher above the surface of the silicon and soon began to
dominate the landscape of the integrated circuit. In the sub
100nm scaling regime, interconnect behavior limits the
performance and correctness of VLSI systems. The wiring in
today’s integrated circuits forms a complex geometry that
introduces capacitive, resistive, and inductive parasitics. They
can cause an increase in propagation delay, impact on energy
dissipation and the power distribution and introduce extra noise sources, which affects the reliability of the circuit. As the device size scales down the impact of interconnect in the VLSI circuits became even more significant. The performance of copper interconnects tend to get reduced in the sub 100nm range and hence we need to examine for other interconnect via options. Single Wall Carbon Nanotubes exhibit better performance in sub 100nm processing technology due to their very large current carrying capacity and large electron mean free paths. Initially we have analyzed the performances of a copper based CMOS inverter for 32nm technology node. SPICE simulations were carried out to validate the results and the results show improved performance of CNT interconnects in terms of power and delay time in comparison to traditional copper based interconnects. This work suggests using Single Wall Carbon Nanotubes (SWCNT) as interconnects for global interconnects in VLSI design as they consume less energy and gives more throughput and bandwidth when compared with traditional Copper wires.
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IJEMS VOL.2 ISSUE 5 by Gaurav Soni
considered as ideal conductors that propagated signals
instantaneously. While device sizes were shrinking with each
technology generation, multilevel metal structures rose higher
and higher above the surface of the silicon and soon began to
dominate the landscape of the integrated circuit. In the sub
100nm scaling regime, interconnect behavior limits the
performance and correctness of VLSI systems. The wiring in
today’s integrated circuits forms a complex geometry that
introduces capacitive, resistive, and inductive parasitics. They
can cause an increase in propagation delay, impact on energy
dissipation and the power distribution and introduce extra noise sources, which affects the reliability of the circuit. As the device size scales down the impact of interconnect in the VLSI circuits became even more significant. The performance of copper interconnects tend to get reduced in the sub 100nm range and hence we need to examine for other interconnect via options. Single Wall Carbon Nanotubes exhibit better performance in sub 100nm processing technology due to their very large current carrying capacity and large electron mean free paths. Initially we have analyzed the performances of a copper based CMOS inverter for 32nm technology node. SPICE simulations were carried out to validate the results and the results show improved performance of CNT interconnects in terms of power and delay time in comparison to traditional copper based interconnects. This work suggests using Single Wall Carbon Nanotubes (SWCNT) as interconnects for global interconnects in VLSI design as they consume less energy and gives more throughput and bandwidth when compared with traditional Copper wires.
Papers by Gaurav Soni
considered as ideal conductors that propagated signals
instantaneously. While device sizes were shrinking with each
technology generation, multilevel metal structures rose higher
and higher above the surface of the silicon and soon began to
dominate the landscape of the integrated circuit. In the sub
100nm scaling regime, interconnect behavior limits the
performance and correctness of VLSI systems. The wiring in
today’s integrated circuits forms a complex geometry that
introduces capacitive, resistive, and inductive parasitics. They
can cause an increase in propagation delay, impact on energy
dissipation and the power distribution and introduce extra noise sources, which affects the reliability of the circuit. As the device size scales down the impact of interconnect in the VLSI circuits became even more significant. The performance of copper interconnects tend to get reduced in the sub 100nm range and hence we need to examine for other interconnect via options. Single Wall Carbon Nanotubes exhibit better performance in sub 100nm processing technology due to their very large current carrying capacity and large electron mean free paths. Initially we have analyzed the performances of a copper based CMOS inverter for 32nm technology node. SPICE simulations were carried out to validate the results and the results show improved performance of CNT interconnects in terms of power and delay time in comparison to traditional copper based interconnects. This work suggests using Single Wall Carbon Nanotubes (SWCNT) as interconnects for global interconnects in VLSI design as they consume less energy and gives more throughput and bandwidth when compared with traditional Copper wires.