Proceedings 6th IEEE International On-Line Testing Workshop (Cat. No.PR00646), 2000
We present hereafter a new approach to estimate the reliability of complex circuits used in harmf... more We present hereafter a new approach to estimate the reliability of complex circuits used in harmful environments like radiation. This goal can be attained in an early stage of the design process. Usually, this step is performed in laboratory, by means of radiation facilities ...
This paper proposes a flexible and reusable BIST controller for the test of logic IP cores. Such ... more This paper proposes a flexible and reusable BIST controller for the test of logic IP cores. Such a controller, called ProBIST, provides test programmability and flexibility for the BIST architecture, making it easier the reuse of the IP core and the test structure. The ProBIST processor can be programmed according to the core user's requirements. In this way, the proposed BIST architecture can be created by the core vendor according to the core's implementation details, offering to the core user an additional degree of flexibility, i.e. the choice of an efficient BIST solution. The integration of the ProBIST controller into a P1500 wrapper, also presented in this paper, provides a standard test interface between the BISTed core and the final system. The proposed strategy is discussed considering area and performance experimental data.
Network-on-Chip has recently emerged ,as an ,alternative communication ,architecture for complex ... more Network-on-Chip has recently emerged ,as an ,alternative communication ,architecture for complex ,system chip and different aspects regarding ,NoC design have been studied in the literature. However, the test of the NoC itself for manufacturing,faults has been marginally tackled. This paper proposes a scalable ,test strategy for the routers in a NoC, based on partial scan and on an IEEE
2013 International Symposium on Rapid System Prototyping (RSP), 2013
ABSTRACT Advances in design integration have enabled the integration of large Multiprocessor Syst... more ABSTRACT Advances in design integration have enabled the integration of large Multiprocessor Systems-on-Chip (MPSoC). Such systems are prone to the execution of complex applications if high degree of parallelism is employed on the communication infrastructure. Network-on-Chip (NoC) has emerged as a new communication paradigm for large MPSoCs with advantages such as the increase of reliability on components interactions. However, device's integration may convey few shortcomings during MPSoC manufacturing and operation, for instance, the vulnerability to faults. This paper describes Phoenix, which is a direct mesh NoC with fault detection scheme. The proposed architecture explores a fault-tolerant mechanism, which is implemented in a distributed manner as a fault monitor on processors and routers. Results demonstrate that Phoenix can be scalable in view of the stabilization time regarding to faults incidence, allowing MPSoC operation even with the occurrence of a large number of faults.
Reliability, Availability and Serviceability of Networks-on-Chip, 2011
In this chapter we cover the first proposed test approaches that reuse the NoC as Test Access Mec... more In this chapter we cover the first proposed test approaches that reuse the NoC as Test Access Mechanism (TAM) in a core-based system. First, the basic reuse strategy is presented, including the very few modifications implemented in the network interface, and ...
2013 IEEE Computer Society Annual Symposium on VLSI (ISVLSI), 2013
ABSTRACT Mechanisms for fault-tolerance in MPSoCs are mandatory to cope with faults during fabric... more ABSTRACT Mechanisms for fault-tolerance in MPSoCs are mandatory to cope with faults during fabrication or product lifetime. For instance, permanent faults on the interconnect network can stall or crash applications even though the network has alternative fault-free paths to a given destination. This PhD work presents a fault-tolerant communication protocol that takes advantage of the NoC routing method to provide alternative paths between any source-target pair of processors. At the application layer, the method is seen as a typical MPI-like message passing protocol. At the lower layers, the method consists of a software kernel layer that monitors the regularity of message exchanges between pairs of tasks. If a message is not delivered in a certain time, the software fires the path finding mechanism, which guarantees complete network reachability. The proposed approach determines new paths quickly, and the costs of extra silicon area and memory usage are small.
Design, Automation & Test in Europe Conference & Exhibition (DATE), 2013, 2013
ABSTRACT Routing algorithms for NoCs were extensively studied in the last 12 years, and proposals... more ABSTRACT Routing algorithms for NoCs were extensively studied in the last 12 years, and proposals for algorithms targeting some cost function, as latency reduction or congestion avoidance, abound in the literature. Fault-tolerant routing algorithms were also proposed, being the table-based approach the most adopted method. Considering SoCs with hundred of cores in a near future, features as scalability, reachability, and fault assumptions should be considered in the fault-tolerant routing methods. However, the current proposals some have some limitations: (1) increasing cost related to the NoC size, compromising scalability; (2) some healthy routers may not be reached even if there is a source-target path; (3) some algorithms restricts the number of faults and their location to operate correctly. The present work presents a method, inspired in VLSI routing algorithms, to search the path between source-target pairs where the network topology is abstracted. Results present the routing path for different topologies (mesh, torus, Spidergon and Hierarchical-Spidergon) in the presence of faulty routers. The silicon area overhead and total execution time of the path computation is small, demonstrating that the proposed method may be adopted in NoC designs.
2013 IEEE Computer Society Annual Symposium on VLSI (ISVLSI), 2013
ABSTRACT Conventional approaches using the Network-on-Chip (NoC) as Test Access Mechanism (TAM), ... more ABSTRACT Conventional approaches using the Network-on-Chip (NoC) as Test Access Mechanism (TAM), called NoC TAM, model the test sources/sinks and the routing algorithm as constraints to the test scheduling, reducing its efficiency. This paper is based on a new NoC TAM model where these constraints do not exist, potentially resulting in shorter tests. The contribution of this paper is to present the part of the test flow which determines the optimal number and location of the test sources and sinks in a NoC TAM without constraining the test scheduler. Searching the minimal number of sources/sinks can minimize the silicon area overhead since each NoC source/sink requires about 4300 gates for a NoC channel with 32-bit width.
An extended fault model and novel strategy to tackle interconnect faults in network-on-chips are ... more An extended fault model and novel strategy to tackle interconnect faults in network-on-chips are proposed. Short faults between distinct channels are considered in a cost-effective test sequence for mesh NoC topologies based on XY routing.
Proceedings 6th IEEE International On-Line Testing Workshop (Cat. No.PR00646), 2000
We present hereafter a new approach to estimate the reliability of complex circuits used in harmf... more We present hereafter a new approach to estimate the reliability of complex circuits used in harmful environments like radiation. This goal can be attained in an early stage of the design process. Usually, this step is performed in laboratory, by means of radiation facilities ...
This paper proposes a flexible and reusable BIST controller for the test of logic IP cores. Such ... more This paper proposes a flexible and reusable BIST controller for the test of logic IP cores. Such a controller, called ProBIST, provides test programmability and flexibility for the BIST architecture, making it easier the reuse of the IP core and the test structure. The ProBIST processor can be programmed according to the core user's requirements. In this way, the proposed BIST architecture can be created by the core vendor according to the core's implementation details, offering to the core user an additional degree of flexibility, i.e. the choice of an efficient BIST solution. The integration of the ProBIST controller into a P1500 wrapper, also presented in this paper, provides a standard test interface between the BISTed core and the final system. The proposed strategy is discussed considering area and performance experimental data.
Network-on-Chip has recently emerged ,as an ,alternative communication ,architecture for complex ... more Network-on-Chip has recently emerged ,as an ,alternative communication ,architecture for complex ,system chip and different aspects regarding ,NoC design have been studied in the literature. However, the test of the NoC itself for manufacturing,faults has been marginally tackled. This paper proposes a scalable ,test strategy for the routers in a NoC, based on partial scan and on an IEEE
2013 International Symposium on Rapid System Prototyping (RSP), 2013
ABSTRACT Advances in design integration have enabled the integration of large Multiprocessor Syst... more ABSTRACT Advances in design integration have enabled the integration of large Multiprocessor Systems-on-Chip (MPSoC). Such systems are prone to the execution of complex applications if high degree of parallelism is employed on the communication infrastructure. Network-on-Chip (NoC) has emerged as a new communication paradigm for large MPSoCs with advantages such as the increase of reliability on components interactions. However, device's integration may convey few shortcomings during MPSoC manufacturing and operation, for instance, the vulnerability to faults. This paper describes Phoenix, which is a direct mesh NoC with fault detection scheme. The proposed architecture explores a fault-tolerant mechanism, which is implemented in a distributed manner as a fault monitor on processors and routers. Results demonstrate that Phoenix can be scalable in view of the stabilization time regarding to faults incidence, allowing MPSoC operation even with the occurrence of a large number of faults.
Reliability, Availability and Serviceability of Networks-on-Chip, 2011
In this chapter we cover the first proposed test approaches that reuse the NoC as Test Access Mec... more In this chapter we cover the first proposed test approaches that reuse the NoC as Test Access Mechanism (TAM) in a core-based system. First, the basic reuse strategy is presented, including the very few modifications implemented in the network interface, and ...
2013 IEEE Computer Society Annual Symposium on VLSI (ISVLSI), 2013
ABSTRACT Mechanisms for fault-tolerance in MPSoCs are mandatory to cope with faults during fabric... more ABSTRACT Mechanisms for fault-tolerance in MPSoCs are mandatory to cope with faults during fabrication or product lifetime. For instance, permanent faults on the interconnect network can stall or crash applications even though the network has alternative fault-free paths to a given destination. This PhD work presents a fault-tolerant communication protocol that takes advantage of the NoC routing method to provide alternative paths between any source-target pair of processors. At the application layer, the method is seen as a typical MPI-like message passing protocol. At the lower layers, the method consists of a software kernel layer that monitors the regularity of message exchanges between pairs of tasks. If a message is not delivered in a certain time, the software fires the path finding mechanism, which guarantees complete network reachability. The proposed approach determines new paths quickly, and the costs of extra silicon area and memory usage are small.
Design, Automation & Test in Europe Conference & Exhibition (DATE), 2013, 2013
ABSTRACT Routing algorithms for NoCs were extensively studied in the last 12 years, and proposals... more ABSTRACT Routing algorithms for NoCs were extensively studied in the last 12 years, and proposals for algorithms targeting some cost function, as latency reduction or congestion avoidance, abound in the literature. Fault-tolerant routing algorithms were also proposed, being the table-based approach the most adopted method. Considering SoCs with hundred of cores in a near future, features as scalability, reachability, and fault assumptions should be considered in the fault-tolerant routing methods. However, the current proposals some have some limitations: (1) increasing cost related to the NoC size, compromising scalability; (2) some healthy routers may not be reached even if there is a source-target path; (3) some algorithms restricts the number of faults and their location to operate correctly. The present work presents a method, inspired in VLSI routing algorithms, to search the path between source-target pairs where the network topology is abstracted. Results present the routing path for different topologies (mesh, torus, Spidergon and Hierarchical-Spidergon) in the presence of faulty routers. The silicon area overhead and total execution time of the path computation is small, demonstrating that the proposed method may be adopted in NoC designs.
2013 IEEE Computer Society Annual Symposium on VLSI (ISVLSI), 2013
ABSTRACT Conventional approaches using the Network-on-Chip (NoC) as Test Access Mechanism (TAM), ... more ABSTRACT Conventional approaches using the Network-on-Chip (NoC) as Test Access Mechanism (TAM), called NoC TAM, model the test sources/sinks and the routing algorithm as constraints to the test scheduling, reducing its efficiency. This paper is based on a new NoC TAM model where these constraints do not exist, potentially resulting in shorter tests. The contribution of this paper is to present the part of the test flow which determines the optimal number and location of the test sources and sinks in a NoC TAM without constraining the test scheduler. Searching the minimal number of sources/sinks can minimize the silicon area overhead since each NoC source/sink requires about 4300 gates for a NoC channel with 32-bit width.
An extended fault model and novel strategy to tackle interconnect faults in network-on-chips are ... more An extended fault model and novel strategy to tackle interconnect faults in network-on-chips are proposed. Short faults between distinct channels are considered in a cost-effective test sequence for mesh NoC topologies based on XY routing.
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Papers by Alexandre M Amory