A 15mW 3.6 GS/s CT-δσ ADC with 36MHz bandwidth and 83dB DR in 90nm CMOS
P Shettigar, S Pavan - 2012 IEEE International Solid-State …, 2012 - ieeexplore.ieee.org
2012 IEEE International Solid-State Circuits Conference, 2012•ieeexplore.ieee.org
We propose design techniques that enable the realization of power-efficient single-bit CT-ΔΣ
ADCs at multi-Gb/s speeds. An FIR DAC [1] is used to reduce sensitivity to clock jitter and
relax loop filter linearity. A mostly analog path compensates the modulator for the delay
introduced by the FIR DAC. The CTDSM samples at 3.6 GS/S, has 83dB DR in 36MHz BW,
and occupies 0.12 mm2 in 90nm CMOS. Dissipating 15mW from a 1.2 V supply, it thereby
achieves an FoM SNDR of 72.8 fJ/level, which is an improvement over the state of the art for …
ADCs at multi-Gb/s speeds. An FIR DAC [1] is used to reduce sensitivity to clock jitter and
relax loop filter linearity. A mostly analog path compensates the modulator for the delay
introduced by the FIR DAC. The CTDSM samples at 3.6 GS/S, has 83dB DR in 36MHz BW,
and occupies 0.12 mm2 in 90nm CMOS. Dissipating 15mW from a 1.2 V supply, it thereby
achieves an FoM SNDR of 72.8 fJ/level, which is an improvement over the state of the art for …
We propose design techniques that enable the realization of power-efficient single-bit CT-ΔΣ ADCs at multi-Gb/s speeds. An FIR DAC [1 ] is used to reduce sensitivity to clock jitter and relax loop filter linearity. A mostly analog path compensates the modulator for the delay introduced by the FIR DAC. The CTDSM samples at 3.6GS/S, has 83dB DR in 36MHz BW, and occupies 0.12mm2 in 90nm CMOS. Dissipating 15mW from a 1.2V supply, it thereby achieves an FoM SNDR of 72.8fJ/level, which is an improvement over the state of the art for converters with bandwidths greater than 20MHz.
ieeexplore.ieee.org