In this paper, we propose a novel standard-cell-based OTA architecture based on an improved versi... more In this paper, we propose a novel standard-cell-based OTA architecture based on an improved version of the differential to single-ended converter, previously proposed by the authors, on a novel standard-cell-based basic voltage amplifier block. Due to a replica-bias approach, the basic voltage amplifier exhibits a well-defined output static voltage to allow easy cascadability. Another feature of the basic voltage amplifier is to provide a low output impedance to allow dominant pole compensation at the output of the cascade of several stages. An ultra-low voltage (ULV) standard-cell-based OTA based on the proposed architecture and building blocks has been designed referring to the standard-cell library of a 130-nm CMOS process with a supply voltage of 0.3 V. The layout of the OTA has been implemented by following an automatic layout flow within a commercial tool for the place-and-route of digital circuits. Simulation results have shown a differential gain of 50 dB with a gain–bandwid...
2019 26th IEEE International Conference on Electronics, Circuits and Systems (ICECS), 2019
A low-power class-AB Gm-C biquad stage has been designed using a voltage buffer based on error am... more A low-power class-AB Gm-C biquad stage has been designed using a voltage buffer based on error amplifiers and a push-pull current mirror. The class-AB architecture allows good power efficiency by lowering the required bias current. The biquad stage consumes $250\boldsymbol{\mu} \mathbf{A}$ from a 1.2V supply, and achieves a resonance frequency of 2.2MHz with a Q of 2. The SFDR (spurious-free dynamic range) with a two-tone test is 48dB and the SNR (signal-to-noise ratio) is 44.4dB, with a 400mVpp differential input signal. A pseudo-differential architecture allows large bandwidth and lower power consumption in the transconductance stages. The stage can be used to synthetize lowpass and bandpass filters composed of low-Q stages.
2017 European Conference on Circuit Theory and Design (ECCTD), 2017
The Voltage Conveyor (VCII) is the dual of the second generation Current Conveyor (CCII), and has... more The Voltage Conveyor (VCII) is the dual of the second generation Current Conveyor (CCII), and has received only a cursory attention in the literature, probably for lack of interesting applications. The VCII has a current buffer between Y and X terminals, and a voltage buffer between X and Z terminals. In this way, it makes it easier to sum (current) signals at the Y node, whereas CCIIs make it easier to sum (current) signals at the X node. Exploiting this difference between the two dual circuits, a very simple N-port synthesizer can be obtained using only N VCIIs. A mixed-signal Y-matrix synthesizer using VCIIs is also proposed, which is the dual of a similar one using CCIIs, and can also be used as an N-port analyzer, with an advantage with respect to the CCII-based version related to the possibility of sensing low-impedance (voltage) inputs. An inductor emulator and a lowpass / bandpass biquad filter are also simulated, showing the versatility of the VCII.
IEEE Transactions on Circuits and Systems I: Regular Papers, 2022
High-speed digitizers operating at sampling rates higher than 10GS/s require low-pass anti-aliasi... more High-speed digitizers operating at sampling rates higher than 10GS/s require low-pass anti-aliasing filters in the multi-GHz range. Asynchronous Time-Interleaved (ATI) digitizers also need low-pass filters before digitization, and additional requirements on their design are set by this specific application. In integrated solutions, inductor-less filters are important for minimizing the chip area footprint. In this paper, we present the design of a 6th-order inductor-less 10GHz low-pass filter implemented in the STMicroelectronics SiGe BiCMOS55 process. It can be used as anti-aliasing filter for conventional 30GS/s digitizers or at the output of a 40GS/s ATI digitizer. We exploit positive feedback to synthesize the active inductor based on a stacked topology, minimizing the number of current branches, and thus power consumption. Analysis and design guidelines for the biquad are presented. The filter exhibits a bandwidth of 10GHz with a power consumption of 43mW, a THD of −45dB and an SNR of 43dB with an input amplitude of 710mV peak-to-peak differential. Extensive corner and Monte Carlo post-layout simulations have been carried out to highlight the robustness of the circuit to PVT and mismatch variations. Experimental results have confirmed very good agreement between measured and simulated performance, validating the proposed design flow.
AEU - International Journal of Electronics and Communications, 2021
Abstract The switched-resistor (S-R) approach is becoming more and more popular among integrated ... more Abstract The switched-resistor (S-R) approach is becoming more and more popular among integrated circuits designers because it allows the implementation of very high equivalent resistances in CMOS circuits. When using this technique, the value of a reference poly resistor is multiplied by a factor dependent on the duty cycle of the clock signal. To achieve resistance multiplication factors higher than 100, the value of the duty cycle has to be reduced below 0.01, but in this case the effects of parasitic components are not negligible anymore and the value of the equivalent resistance tends to saturate at a maximum value. In this paper, we present a distributed switched-resistor approach that aims to strongly mitigate the effect of parasitic capacitances on the value of the equivalent resistance even when exploiting very small values for the duty cycle, thus allowing resistance multiplication factors up to a few thousands. As a validation of this approach, we consider the implementation of a high Q biquad filter for neural recording applications and compare the conventional S-R technique against the proposed distributed S-R approach in terms of the maximum achievable Q factor.
2020 AEIT International Annual Conference (AEIT), 2020
CMOS technology has been extensively used for the realization of image sensors at Terahertz frequ... more CMOS technology has been extensively used for the realization of image sensors at Terahertz frequencies. The explanation of its strong efficiency was usually given invoking a mechanism described by the plasma wave detection theory. This model predicts that, when a high frequency potential is applied between gate and source electrodes of a MOSFET, oscillations of the 2D electron gas, located in the inversion layer, converts THz radiation into a DC voltage. Recently, we developed a new model of the self-mixing rectification process occurring in the depleted portion of a semiconductors crossed by a radiofrequency electric field. We studied both the new double barrier structure and the extensively used depleted region in MOS. In this paper, on the light of these new results, we review the theory of the THz detection in a MOS-FET structure. For a comparison with the former approach, we notice that the volume of interaction between free carriers and the RF electric field considered in thi...
2017 European Conference on Circuit Theory and Design (ECCTD), 2017
We propose a novel class-AB second-generation Current Conveyor (CCII) based on the class-AB Flipp... more We propose a novel class-AB second-generation Current Conveyor (CCII) based on the class-AB Flipped Voltage Follower (FVF) topology, and compare it with a class-A CCII based on the conventional FVF. The AB-FVF is capable of driving larger capacitive loads, showing faster settling. Furthermore, it can drive the Z output with currents larger than the biasing ones, improving power efficiency. A modification of a previously published FVF is also introduced to improve the compensation of the frequency response.
IEEE Transactions on Circuits and Systems II: Express Briefs, 2021
The implementation of backhauling links poses several challenges to the designers which are reque... more The implementation of backhauling links poses several challenges to the designers which are requested to limit the hardware costs in the framework of complex millimeter wave radio systems. This work presents a monolithically integrated E-band I/Q receiver covering the whole bandwidth from 71 to 86 GHz. The chip was implemented in a 55 nm SiGe BiCMOS technology which allows reaching a high level of integration. The receiver is based on a Low Noise Amplifier (LNA) stage and a Variable-Gain Amplifier (VGA) which provide a −11 dBm IP1dB. A double balanced mixer provides I/Q baseband outputs through a reduced-size differential phase shifter which allows to contain the chip size to 1.8 mm2.
International Journal of Circuit Theory and Applications, 2020
A 4th‐order Butterworth class‐AB current‐mode low‐pass filter is proposed, based on second‐genera... more A 4th‐order Butterworth class‐AB current‐mode low‐pass filter is proposed, based on second‐generation Current Conveyors (CCII). Class‐AB operation allows high‐power efficiency and driving large loads with small quiescent currents. The CCII topology uses the class‐AB output buffer with error amplifiers: this topology is known to be sensitive to mismatch errors, which cause offsets in the error amplifiers, affecting the biasing current of the stage. This problem is solved via a control loop, which compensates the effect of mismatches. The technique is shown to be effective in Monte Carlo simulations with process variations and mismatches. Simulations have been carried out in 40 nm CMOS technology. The proposed filter achieves good power efficiency, thanks to the class‐AB architecture, and good dynamic range, thanks to the closed‐loop output buffer. A cut‐off frequency of 6 MHz, with 184 μW of total quiescent power consumption, is achieved, with a THD of ‐55 dB and a SNR of 49 dB.
In this paper, a novel dynamic body-driven ultra-low voltage (ULV) comparator is presented. The p... more In this paper, a novel dynamic body-driven ultra-low voltage (ULV) comparator is presented. The proposed topology takes advantage of the back-gate configuration by driving the input transistors’ gates with a clocked positive feedback loop made of two AND gates. This allows for the removal of the clocked tail generator, which decreases the number of stacked transistors and improves performance at low VDD. Furthermore, the clocked feedback loop causes the comparator to behave as a full CMOS latch during the regeneration phase, which means no static power consumption occurs after the outputs have settled. Thanks to body driving, the proposed comparator also achieves rail-to-rail input common mode range (ICMR), which is a critical feature for circuits that operate at low and ultra-low voltage headrooms. The comparator was designed and optimized in a 130-nm technology from STMicroelectronics at VDD=0.3 V and is able to operate at up to 2 MHz with an input differential voltage of 1 mV. Th...
The use of capacitive sensors has advantages in different industrial applications due to their lo... more The use of capacitive sensors has advantages in different industrial applications due to their low cost and low-temperature dependence. In this sense, the current-mode approach by means of second-generation current conveyors (CCIIs) allows for improvements in key features, such as sensitivity and resolution. In this paper, a novel architecture of CCII for differential capacitive sensor interfaces is presented. The proposed topology shows a closed-loop configuration for both the voltage and the current buffer, thus leading to better interface impedances at terminals X and Z. Moreover, a low power consumption of 600 µW was obtained due to class-AB biasing of both buffers, and the inherent drawbacks in terms of linearity under the mismatch of class-AB buffering are overcome by its closed-loop configuration. The advantages of the novel architecture are demonstrated by circuit analysis and simulations; in particular, very good robustness under process, supply voltage and temperature vari...
Journal of Low Power Electronics and Applications, 2022
In this paper, we introduce a novel tree-based architecture which allows the implementation of Ul... more In this paper, we introduce a novel tree-based architecture which allows the implementation of Ultra-Low-Voltage (ULV) amplifiers. The architecture exploits a body-driven input stage to guarantee a rail-to-rail input common mode range and body-diode loading to avoid Miller compensation, thanks to the absence of high-impedance internal nodes. The tree-based structure improves the CMRR of the proposed amplifier with respect to the conventional OTA architectures and allows achievement of a reasonable CMRR even at supply voltages as low as 0.3 V and without tail current generators which cannot be used in ULV circuits. The bias currents and the static output voltages of all the stages implementing the architecture are accurately set through the gate terminals of biasing transistors in order to guarantee good robustness against PVT variations. The proposed architecture and the implementing stages are investigated from an analytical point of view and design equations for the main performan...
In this paper, we propose a novel standard-cell-based OTA architecture based on an improved versi... more In this paper, we propose a novel standard-cell-based OTA architecture based on an improved version of the differential to single-ended converter, previously proposed by the authors, on a novel standard-cell-based basic voltage amplifier block. Due to a replica-bias approach, the basic voltage amplifier exhibits a well-defined output static voltage to allow easy cascadability. Another feature of the basic voltage amplifier is to provide a low output impedance to allow dominant pole compensation at the output of the cascade of several stages. An ultra-low voltage (ULV) standard-cell-based OTA based on the proposed architecture and building blocks has been designed referring to the standard-cell library of a 130-nm CMOS process with a supply voltage of 0.3 V. The layout of the OTA has been implemented by following an automatic layout flow within a commercial tool for the place-and-route of digital circuits. Simulation results have shown a differential gain of 50 dB with a gain–bandwid...
2019 26th IEEE International Conference on Electronics, Circuits and Systems (ICECS), 2019
A low-power class-AB Gm-C biquad stage has been designed using a voltage buffer based on error am... more A low-power class-AB Gm-C biquad stage has been designed using a voltage buffer based on error amplifiers and a push-pull current mirror. The class-AB architecture allows good power efficiency by lowering the required bias current. The biquad stage consumes $250\boldsymbol{\mu} \mathbf{A}$ from a 1.2V supply, and achieves a resonance frequency of 2.2MHz with a Q of 2. The SFDR (spurious-free dynamic range) with a two-tone test is 48dB and the SNR (signal-to-noise ratio) is 44.4dB, with a 400mVpp differential input signal. A pseudo-differential architecture allows large bandwidth and lower power consumption in the transconductance stages. The stage can be used to synthetize lowpass and bandpass filters composed of low-Q stages.
2017 European Conference on Circuit Theory and Design (ECCTD), 2017
The Voltage Conveyor (VCII) is the dual of the second generation Current Conveyor (CCII), and has... more The Voltage Conveyor (VCII) is the dual of the second generation Current Conveyor (CCII), and has received only a cursory attention in the literature, probably for lack of interesting applications. The VCII has a current buffer between Y and X terminals, and a voltage buffer between X and Z terminals. In this way, it makes it easier to sum (current) signals at the Y node, whereas CCIIs make it easier to sum (current) signals at the X node. Exploiting this difference between the two dual circuits, a very simple N-port synthesizer can be obtained using only N VCIIs. A mixed-signal Y-matrix synthesizer using VCIIs is also proposed, which is the dual of a similar one using CCIIs, and can also be used as an N-port analyzer, with an advantage with respect to the CCII-based version related to the possibility of sensing low-impedance (voltage) inputs. An inductor emulator and a lowpass / bandpass biquad filter are also simulated, showing the versatility of the VCII.
IEEE Transactions on Circuits and Systems I: Regular Papers, 2022
High-speed digitizers operating at sampling rates higher than 10GS/s require low-pass anti-aliasi... more High-speed digitizers operating at sampling rates higher than 10GS/s require low-pass anti-aliasing filters in the multi-GHz range. Asynchronous Time-Interleaved (ATI) digitizers also need low-pass filters before digitization, and additional requirements on their design are set by this specific application. In integrated solutions, inductor-less filters are important for minimizing the chip area footprint. In this paper, we present the design of a 6th-order inductor-less 10GHz low-pass filter implemented in the STMicroelectronics SiGe BiCMOS55 process. It can be used as anti-aliasing filter for conventional 30GS/s digitizers or at the output of a 40GS/s ATI digitizer. We exploit positive feedback to synthesize the active inductor based on a stacked topology, minimizing the number of current branches, and thus power consumption. Analysis and design guidelines for the biquad are presented. The filter exhibits a bandwidth of 10GHz with a power consumption of 43mW, a THD of −45dB and an SNR of 43dB with an input amplitude of 710mV peak-to-peak differential. Extensive corner and Monte Carlo post-layout simulations have been carried out to highlight the robustness of the circuit to PVT and mismatch variations. Experimental results have confirmed very good agreement between measured and simulated performance, validating the proposed design flow.
AEU - International Journal of Electronics and Communications, 2021
Abstract The switched-resistor (S-R) approach is becoming more and more popular among integrated ... more Abstract The switched-resistor (S-R) approach is becoming more and more popular among integrated circuits designers because it allows the implementation of very high equivalent resistances in CMOS circuits. When using this technique, the value of a reference poly resistor is multiplied by a factor dependent on the duty cycle of the clock signal. To achieve resistance multiplication factors higher than 100, the value of the duty cycle has to be reduced below 0.01, but in this case the effects of parasitic components are not negligible anymore and the value of the equivalent resistance tends to saturate at a maximum value. In this paper, we present a distributed switched-resistor approach that aims to strongly mitigate the effect of parasitic capacitances on the value of the equivalent resistance even when exploiting very small values for the duty cycle, thus allowing resistance multiplication factors up to a few thousands. As a validation of this approach, we consider the implementation of a high Q biquad filter for neural recording applications and compare the conventional S-R technique against the proposed distributed S-R approach in terms of the maximum achievable Q factor.
2020 AEIT International Annual Conference (AEIT), 2020
CMOS technology has been extensively used for the realization of image sensors at Terahertz frequ... more CMOS technology has been extensively used for the realization of image sensors at Terahertz frequencies. The explanation of its strong efficiency was usually given invoking a mechanism described by the plasma wave detection theory. This model predicts that, when a high frequency potential is applied between gate and source electrodes of a MOSFET, oscillations of the 2D electron gas, located in the inversion layer, converts THz radiation into a DC voltage. Recently, we developed a new model of the self-mixing rectification process occurring in the depleted portion of a semiconductors crossed by a radiofrequency electric field. We studied both the new double barrier structure and the extensively used depleted region in MOS. In this paper, on the light of these new results, we review the theory of the THz detection in a MOS-FET structure. For a comparison with the former approach, we notice that the volume of interaction between free carriers and the RF electric field considered in thi...
2017 European Conference on Circuit Theory and Design (ECCTD), 2017
We propose a novel class-AB second-generation Current Conveyor (CCII) based on the class-AB Flipp... more We propose a novel class-AB second-generation Current Conveyor (CCII) based on the class-AB Flipped Voltage Follower (FVF) topology, and compare it with a class-A CCII based on the conventional FVF. The AB-FVF is capable of driving larger capacitive loads, showing faster settling. Furthermore, it can drive the Z output with currents larger than the biasing ones, improving power efficiency. A modification of a previously published FVF is also introduced to improve the compensation of the frequency response.
IEEE Transactions on Circuits and Systems II: Express Briefs, 2021
The implementation of backhauling links poses several challenges to the designers which are reque... more The implementation of backhauling links poses several challenges to the designers which are requested to limit the hardware costs in the framework of complex millimeter wave radio systems. This work presents a monolithically integrated E-band I/Q receiver covering the whole bandwidth from 71 to 86 GHz. The chip was implemented in a 55 nm SiGe BiCMOS technology which allows reaching a high level of integration. The receiver is based on a Low Noise Amplifier (LNA) stage and a Variable-Gain Amplifier (VGA) which provide a −11 dBm IP1dB. A double balanced mixer provides I/Q baseband outputs through a reduced-size differential phase shifter which allows to contain the chip size to 1.8 mm2.
International Journal of Circuit Theory and Applications, 2020
A 4th‐order Butterworth class‐AB current‐mode low‐pass filter is proposed, based on second‐genera... more A 4th‐order Butterworth class‐AB current‐mode low‐pass filter is proposed, based on second‐generation Current Conveyors (CCII). Class‐AB operation allows high‐power efficiency and driving large loads with small quiescent currents. The CCII topology uses the class‐AB output buffer with error amplifiers: this topology is known to be sensitive to mismatch errors, which cause offsets in the error amplifiers, affecting the biasing current of the stage. This problem is solved via a control loop, which compensates the effect of mismatches. The technique is shown to be effective in Monte Carlo simulations with process variations and mismatches. Simulations have been carried out in 40 nm CMOS technology. The proposed filter achieves good power efficiency, thanks to the class‐AB architecture, and good dynamic range, thanks to the closed‐loop output buffer. A cut‐off frequency of 6 MHz, with 184 μW of total quiescent power consumption, is achieved, with a THD of ‐55 dB and a SNR of 49 dB.
In this paper, a novel dynamic body-driven ultra-low voltage (ULV) comparator is presented. The p... more In this paper, a novel dynamic body-driven ultra-low voltage (ULV) comparator is presented. The proposed topology takes advantage of the back-gate configuration by driving the input transistors’ gates with a clocked positive feedback loop made of two AND gates. This allows for the removal of the clocked tail generator, which decreases the number of stacked transistors and improves performance at low VDD. Furthermore, the clocked feedback loop causes the comparator to behave as a full CMOS latch during the regeneration phase, which means no static power consumption occurs after the outputs have settled. Thanks to body driving, the proposed comparator also achieves rail-to-rail input common mode range (ICMR), which is a critical feature for circuits that operate at low and ultra-low voltage headrooms. The comparator was designed and optimized in a 130-nm technology from STMicroelectronics at VDD=0.3 V and is able to operate at up to 2 MHz with an input differential voltage of 1 mV. Th...
The use of capacitive sensors has advantages in different industrial applications due to their lo... more The use of capacitive sensors has advantages in different industrial applications due to their low cost and low-temperature dependence. In this sense, the current-mode approach by means of second-generation current conveyors (CCIIs) allows for improvements in key features, such as sensitivity and resolution. In this paper, a novel architecture of CCII for differential capacitive sensor interfaces is presented. The proposed topology shows a closed-loop configuration for both the voltage and the current buffer, thus leading to better interface impedances at terminals X and Z. Moreover, a low power consumption of 600 µW was obtained due to class-AB biasing of both buffers, and the inherent drawbacks in terms of linearity under the mismatch of class-AB buffering are overcome by its closed-loop configuration. The advantages of the novel architecture are demonstrated by circuit analysis and simulations; in particular, very good robustness under process, supply voltage and temperature vari...
Journal of Low Power Electronics and Applications, 2022
In this paper, we introduce a novel tree-based architecture which allows the implementation of Ul... more In this paper, we introduce a novel tree-based architecture which allows the implementation of Ultra-Low-Voltage (ULV) amplifiers. The architecture exploits a body-driven input stage to guarantee a rail-to-rail input common mode range and body-diode loading to avoid Miller compensation, thanks to the absence of high-impedance internal nodes. The tree-based structure improves the CMRR of the proposed amplifier with respect to the conventional OTA architectures and allows achievement of a reasonable CMRR even at supply voltages as low as 0.3 V and without tail current generators which cannot be used in ULV circuits. The bias currents and the static output voltages of all the stages implementing the architecture are accurately set through the gate terminals of biasing transistors in order to guarantee good robustness against PVT variations. The proposed architecture and the implementing stages are investigated from an analytical point of view and design equations for the main performan...
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Papers by Francesco Centurelli