research-article

Energy reduction for STT-RAM using early write termination

Authors:

Youtao ZhangAuthors Info & Claims

ICCAD '09: Proceedings of the 2009 International Conference on Computer-Aided Design

Pages 264 - 268

https://doi.org/10.1145/1687399.1687448

Published: 02 November 2009 Publication History

Abstract

The emerging Spin Torque Transfer memory (STT-RAM) is a promising candidate for future on-chip caches due to STT-RAM's high density, low leakage, long endurance and high access speed. However, one of the major challenges of STT-RAM is its high write current, which is disadvantageous when used as an on-chip cache since the dynamic power generated is too high.

In this paper, we propose Early Write Termination (EWT), a novel technique to significantly reduce write energy with no performance penalty. EWT can be implemented with low complexity and low energy overhead. Our evaluation shows that up to 80% of write energy reduction can be achieved through EWT, resulting 33% less total energy consumption, and 34% reduction in ED². These results indicate that EWT is an effective and practical scheme to improve the energy efficiency of a STT-RAM cache.

References

[1]

Y. Chen, X. Wang, H. Li, H. Liu, D. V. Dimitrov, "Design Margin Exploration of Spin-Torque Transfer RAM (SPRAM)," International Symposium on Quality Electronic Design, pp. 684--690, 2008.

Digital Library

[2]

X. Dong, X. Wu, G. Sun, Y. Xie, H. Li, Y. Chen, "Circuit and Microarchitecture Evaluation of 3D Stacking Magnetic RAM (MRAM) as a Universal Memory Replacement," Design Automation Conference, pp. 554--559, 2008.

Digital Library

[3]

M. Hosomi et.al. "A Novel Nonvolatile Memory with Spin Torque Transfer Magnetization Switching: Spin-RAM" IEEE International Electron Devices Meeting, pp. 459--462, 2005.

[4]

D. H. Kang, et al., "Two-bit Cell Operation in Diode-Switch Phase Change Memory Cells with 90nm Technology," IEEE Symposium on VLSI Technology Digest of Technical Papers, pp. 98--99, 2008.

[5]

T. Kawahara et.al. "2 Mb SPRAM (SPin-Transfer Torque RAM) with Bit-by-Bit Bi-Directional Current Write and Parallelizing-Direction Current Read," IEEE Journal of Solid-State Circuits, Vol. 43, No. 1, pp. 109--120, Jan. 2008.

[6]

S. Lai, T. Lowrey, "OUM - A 180nm Nonvolatile Memory Cell Element Technology for Standalone and Embedded Applications," International Electron Devices Meeting, pp. 36.5.1--36.5.4, 2001.

[7]

B. C. Lee, E. Ipek, D. Burger "Architecting Phase Change Memory as a Scalable DRAM Alternative," to appear, International Symposium on Computer Architecture, 2009.

Digital Library

[8]

K. M. Lepak and M. H. Lipasti, "On the Value Locality of Store Instructions," International Symposium on Computer Architecture, pp. 182--191, 2000.

Digital Library

[9]

K. M. Lepak and M. H. Lipasti, "Silent Stores for Free," International Symposium on Microarchitecture, pp. 22--31, 2000.

Digital Library

[10]

J. Li, C. Augustine, S. Salahuddin, K. Roy, "Modeling of Failure Probability and Statistical Design of Spin-Torque Transfer Magnetic Random Access Memory (STTMRAM) Array for Yield Enhancement," Design Automation Conference, pp. 278--283, 2008.

Digital Library

[11]

P. S. Magnusson, et al., "Simics: A full system simulation platform," Computer, 35(2):50--58, 2002.

Digital Library

[12]

M. Hosomi, et al. "A Novel Nonvolatile Memory With Spin Torque Transfer Magnetization Switching: Spin-RAM," International Electron Devices Meeting, pp. 459--462, 2005.

[13]

J. P. Singh, W. Weber, A. Gupta. "SPLASH: Stanford Parallel Applications for Shared-Memory". In Computer Architecture News, vol. 20, no. 1, pp 5--44.

Digital Library

[14]

G. Sun, X. Dong, Y. Xie, J. Li, Y. Chen, "A Novel Architecture of the 3D Stacked MRAM L2 Cache for CMPs," The 15th International Symposium on High-Performance Computer Architecture, pp. 239--249, 2009.

[15]

F. Tabrizi, "The Future of Scalable STT-RAM as a Universal Embedded Memory," Embedded.com, February 2007.

[16]

S. Thoziyoor, N. Muralimanohar, J. H. Ahn, N. P. Jouppi, "CACTI 5.1", http://www.hpl.hp.com/techreports/2008/HPL-2008-20.html, 2008.

[17]

Y. Xie, G. H. Loh, B. Black, K. Bernstein, "Design space exploration for 3D architectures," ACM Journal on Emerging Technologies in Computing Systems (JETC), pp. 65--103, 2006.

Digital Library

[18]

F. Yeung, et al., "De ₂ Sb ₂ Te ₅ Confined Structures and Integration of 64Mb Phase-Change Random Access Memory," Japanese Journal of Applied Physics, pp. 2691--2695, 2005.

[19]

"The International Technology Roadmap for Semiconductors, Process Integration, Device and Structures," http://www.itrs.net/links/2007itrs/2007_chapters/2007_PIDS.pdf 2007.

[20]

P. Zhou, B. Zhao, J. Yang, Y. Zhang, "A Durable and Energy Efficient Main Memory Using Phase Change Memory Technology," The 36^th International Symposium on Computer Architecture, To Appear, 2009.

Digital Library

[21]

J. G. Zhu, "Magnetoresistive Random AccessMemory: The Path to Competitiveness and Scalability," Proceedings of the IEEE, pp. 1786--1798, 2008.

[22]

J. M. Rabaey, A. Chandrakasan, B. Nikolic, "Digital Integrated Circuits: A Design Perspective 2nd Edition," Prentice-Hall Electronics And VLSI Series, page 680--681, 2003.

Digital Library

[23]

K. Miura, et al., "A novel SPRAM (SPin-transfer torque RAM) with a synthetic ferrimagnetic free layer for higher immunity to read disturbance and reducing write-current dispersion," Symposium on VLSI Technology Digest of Technical Papers, pp. 234--235, 2007.

[24]

J. Hayakawa, et al., "Current-Induced Magnetization Switching in MgO Barrier Magnetic Tunnel Junctions With CoFeB-Based Synthetic Ferrimagnetic Free Layers," IEEE Transactions on Magnetics, Vol. 44, No. 7, pp. 1962--1967, 2008.

[25]

M. Durlam, et al., "A 1-Mbit MRAM Based on 1T1MTJ Bit Cell Integrated With Copper Interconnects," IEEE Journal of Solid-State Circuits, Vol. 38, No. 5, pp. 769--773, 2003.

[26]

C. L. Su, et al., "Write Disturbance Modeling and Testing for MRAM," IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Vol. 16, No. 3, pp. 277--288, 2008.

Digital Library

[27]

D. Gogl, et al., "A 16-Mb MRAM Featuring Bootstrapped Write Drivers," IEEE Journal of Solid-State Circuits, Vol. 40, No. 4, pp. 902--908, 2005.

Cited By

ASANO KNATSUI MHANYU T(2024)Error-Tolerance-Aware Write-Energy Reduction of MTJ-Based Quantized Neural Network HardwareIEICE Transactions on Information and Systems10.1587/transinf.2023LOP0007E107.D:8(958-965)Online publication date: 1-Aug-2024
https://doi.org/10.1587/transinf.2023LOP0007
Kumari SYadav R(2024)Survey On the Sensing Techniques Used for Spin Transfer Torque MRAMJournal of The Institution of Engineers (India): Series B10.1007/s40031-024-01111-1105:5(1469-1496)Online publication date: 18-Jul-2024
https://doi.org/10.1007/s40031-024-01111-1
Rajpoot JVerma S(2023)Area-Efficient Auto-Write-Terminate Circuit for NV Latch and Logic-In-Memory ApplicationsIEEE Transactions on Circuits and Systems II: Express Briefs10.1109/TCSII.2023.324298970:7(2630-2634)Online publication date: Jul-2023
https://doi.org/10.1109/TCSII.2023.3242989
Show More Cited By

Index Terms

Energy reduction for STT-RAM using early write termination
1. Applied computing
  1. Arts and humanities
    1. Architecture (buildings)
      1. Computer-aided design
  2. Physical sciences and engineering
    1. Engineering
      1. Computer-aided design
2. Hardware
  1. Integrated circuits
    1. Semiconductor memory

Recommendations

STT-RAM Energy Reduction Using Self-Referenced Differential Write Termination Technique

Spin-transfer torque random access memory (STT-RAM) has emerged as an attractive candidate for future nonvolatile memories. It advantages the benefits of current state-of-the-art memories including high-speed read operation (of static RAM), high density ...
Low-energy volatile STT-RAM cache design using cache-coherence-enabled adaptive refresh

Spin-Torque Transfer RAM (STT-RAM) is a promising candidate for SRAM replacement because of its excellent features, such as fast read access, high density, low leakage power, and CMOS technology compatibility. However, wide adoption of STT-RAM as cache ...
Endurance enhancement of write-optimized STT-RAM caches
MEMSYS '19: Proceedings of the International Symposium on Memory Systems

Low density and high leakage power of SRAM are the major setbacks for its scalability. Non-volatile memory (NVM) like spin-transfer torque random access memory (STT-RAM) is a suitable replacement for SRAM at the last level cache (LLC). NVM offers high ...

Comments

Information & Contributors

Information

Published In

cover image ACM Conferences

ICCAD '09: Proceedings of the 2009 International Conference on Computer-Aided Design

November 2009

803 pages

ISBN:9781605588001

DOI:10.1145/1687399

General Chair:
Jaijeet Roychowdhury
Univ. of California, Berkeley, Berkeley, California

Copyright © 2009 ACM.

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

Sponsors

SIGDA: ACM Special Interest Group on Design Automation
IEEE CAS
IEEE Council on Electronic Design Automation (CEDA)

Publisher

Association for Computing Machinery

New York, NY, United States

Publication History

Published: 02 November 2009

Permissions

Request permissions for this article.

Request Permissions

Check for updates

Qualifiers

Research-article

Funding Sources

Conference

ICCAD '09

Sponsor:

SIGDA

ICCAD '09: The International Conference on Computer-Aided Design

November 2 - 5, 2009

California, San Jose

Acceptance Rates

Overall Acceptance Rate 457 of 1,762 submissions, 26%

Contributors

Other Metrics

View Article Metrics

Bibliometrics & Citations

Bibliometrics

Article Metrics

284
Total Citations
View Citations
719
Total Downloads

Downloads (Last 12 months)51
Downloads (Last 6 weeks)9

Reflects downloads up to 23 Dec 2024

Other Metrics

View Author Metrics

Citations

Cited By

ASANO KNATSUI MHANYU T(2024)Error-Tolerance-Aware Write-Energy Reduction of MTJ-Based Quantized Neural Network HardwareIEICE Transactions on Information and Systems10.1587/transinf.2023LOP0007E107.D:8(958-965)Online publication date: 1-Aug-2024
https://doi.org/10.1587/transinf.2023LOP0007
Kumari SYadav R(2024)Survey On the Sensing Techniques Used for Spin Transfer Torque MRAMJournal of The Institution of Engineers (India): Series B10.1007/s40031-024-01111-1105:5(1469-1496)Online publication date: 18-Jul-2024
https://doi.org/10.1007/s40031-024-01111-1
Rajpoot JVerma S(2023)Area-Efficient Auto-Write-Terminate Circuit for NV Latch and Logic-In-Memory ApplicationsIEEE Transactions on Circuits and Systems II: Express Briefs10.1109/TCSII.2023.324298970:7(2630-2634)Online publication date: Jul-2023
https://doi.org/10.1109/TCSII.2023.3242989
Rajpoot JGupta MVerma S(2023)Enhancing the Reliability of Hybrid MTJ/CMOS Circuits with Auto Write Termination2023 IEEE International Symposium on the Physical and Failure Analysis of Integrated Circuits (IPFA)10.1109/IPFA58228.2023.10249113(1-6)Online publication date: 24-Jul-2023
https://doi.org/10.1109/IPFA58228.2023.10249113
Zhang GJiang Y(2023)Novel multi-bit parallel pipeline-circuit design for STT-MRAMAIP Advances10.1063/9.000057613:2(025010)Online publication date: 1-Feb-2023
https://doi.org/10.1063/9.0000576
Jeong JZeng JJung CWeissman JChandra AGavrilovska ATiwari D(2022)CapriProceedings of the 31st International Symposium on High-Performance Parallel and Distributed Computing10.1145/3502181.3531474(71-83)Online publication date: 27-Jun-2022
https://dl.acm.org/doi/10.1145/3502181.3531474
Asifuzzaman KVerdejo RRadojković P(2022)Performance and Power Estimation of STT-MRAM Main Memory with Reliable System-level SimulationACM Transactions on Embedded Computing Systems10.1145/347683821:1(1-25)Online publication date: 14-Jan-2022
https://dl.acm.org/doi/10.1145/3476838
Zhang GJiang Y(2022)Fast Writing Strategy of STT-MRAM With Pipeline ArchitectureIEEE Transactions on Magnetics10.1109/TMAG.2021.313660458:8(1-5)Online publication date: Aug-2022
https://doi.org/10.1109/TMAG.2021.3136604
Singh RVerma SMittal S(2022)FinFET Fin-Trimming During Replacement Metal Gate for an Asymmetric Device Toward STT MRAM Performance EnhancementIEEE Transactions on Electron Devices10.1109/TED.2022.321720669:12(6699-6704)Online publication date: Dec-2022
https://doi.org/10.1109/TED.2022.3217206
Kim YJeon YChoi HGuyot CCassuto Y(2022)Optimizing Write Fidelity of MRAMs by Alternating Water-Filling AlgorithmIEEE Transactions on Communications10.1109/TCOMM.2022.319086870:9(5825-5836)Online publication date: Sep-2022
https://doi.org/10.1109/TCOMM.2022.3190868
Show More Cited By

View Options

Login options

Check if you have access through your login credentials or your institution to get full access on this article.

Full Access

Get this Publication

View options

PDF

View or Download as a PDF file.

eReader

View online with eReader.

Media

Figures

Other

Tables

View Table of Contents