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Parallelization of the channel width search for FPGA routing

Published: 19 December 2011 Publication History
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    References

    [1]
    J. Luu, I. Kuon, P. Jamieson, T. Campbell, A. Ye, W. Mark, Fang and J. Rose, "VPR 5.0: FPGA cad and architecture exploration tools with single-driver routing, heterogeneity and process scaling," Proc. ACM/SIGDA Int'l Symp. on Field-programmable Gate Arrays, 2009.
    [2]
    P. Baneriee, Parallel Algorithms for VLSI Computer-aided Design, Prentice Hall Int'l Editions, New Jersey, 1994.
    [3]
    P. Chan and M. Schlag, "New parallelization and convergence results for NC: A negotiation-based FPGA router," Proc. ACM/SIGDA 8th Int'l Symp. on Field-programmable Gate Arrays, 2000.
    [4]
    H. Sawada, M. Kuga, M. Amagasaki, M. Iida and T. Sueyoshi, "Parappelization of the channel width search for FPGA routing," Proc. Second Int'l Workshop on Highly-Efficient Accelerators and Reconfiguarable Technologies (HEART2011), pp. 111-116, June 2011.
    [5]
    S. Yang, "Logic synthesis and optimization benchmarks user guide version 3.0," Tech. Report, Microelectronics Center of North Carolina (MCNC), 1991.

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        cover image ACM SIGARCH Computer Architecture News
        ACM SIGARCH Computer Architecture News  Volume 39, Issue 4
        September 2011
        116 pages
        ISSN:0163-5964
        DOI:10.1145/2082156
        Issue’s Table of Contents

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        Association for Computing Machinery

        New York, NY, United States

        Publication History

        Published: 19 December 2011
        Published in SIGARCH Volume 39, Issue 4

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