research-article

Synthesizable Standard Cell FPGA Fabrics Targetable by the Verilog-to-Routing CAD Flow

Authors:

Jason H. AndersonAuthors Info & Claims

ACM Transactions on Reconfigurable Technology and Systems (TRETS), Volume 10, Issue 2

Article No.: 11, Pages 1 - 23

https://doi.org/10.1145/3024063

Published: 06 April 2017 Publication History

Abstract

In this article, we consider implementing field-programmable gate arrays (FPGAs) using a standard cell design methodology and present a framework for the automated generation of synthesizable FPGA fabrics. The open-source Verilog-to-Routing (VTR) FPGA architecture evaluation framework [Rose et al. 2012] is extended to generate synthesizable Verilog for its in-memory FPGA architectural device model. The Verilog can subsequently be synthesized into standard cells, placed and routed using an ASIC design flow. A second extension to VTR generates a configuration bitstream for the FPGA, where the bitstream configures the FPGA to realize a user-provided placed and routed design. The proposed framework and methodology makes possible the silicon implementation of a wide range of VTR-modeled FPGA fabrics. In an experimental study, area and timing-optimized FPGA implementations in 65nm TSMC standard cells are compared to a 65nm Altera commercial FPGA. In addition, we consider augmenting the generic standard-cell library from TSMC with a manually designed and laid-out FPGA-specific cell. We demonstrate the utility of the custom cell in reducing the area of the synthesized FPGA fabric.

References

[1]

Victor Aken’Ova. 2005. Bridging the Gap Between Soft and Hard eFPGA Design. Master’s Thesis. University of British Columbia.

[2]

Victor Aken’Ova, Guy Lemieux, and Resve Saleh. 2005. An improved “soft” eFPGA design and implementation strategy. In Proceedings of the 2005 IEEE CICC Conference (CICC’05). 179--182.

[3]

Victor Aken’Ova and Resve Saleh. 2006. A “soft++” eFPGA physical design approach with case studies in 180nm and 90nm. In Proceedings of the 2006 ISVLSI Conference (ISVLSI’06). IEEE, Los Alamitos, CA.

[4]

Altera. 2015. Stratix III ALM Logic Structure’s 8-Input Fracturable LUT. Technical Report. Altera Corporation. https://www.altera.com/products/fpga/features/st3-logic-structure.html.

[5]

Vaughn Betz, Jonathan Rose, and Alexander Marquardt. 1999. Architecture and CAD for Deep-Submicron FPGAs. Kluwer.

[6]

Vaughn Betz and Jonathan Rose. 1997. VPR: A new packing, placement and routing tool for FPGA research. In Proceedings of the 1997 FPL Conference (FPL’97). 213--222.

[7]

S. D. Brown, R. J. Francis, J. Rose, and Z. G. Vranesic. 2012. Field-Programmable Gate Arrays. Springer International Series in Engineering and Computer Science, Vol. 180. Springer Science 8 Business Media.

[8]

S. Chaudhuri, J.-L. Danger, and S. Guilley. 2007. Efficient modeling and floorplanning of embedded-FPGA fabric. In Proceedings of the 2007 FPL Conference (FPL’07). IEEE, Los Alamitos, CA, 665--669.

[9]

S. Chaudhuri, S. Guilley, F. Flament, P. Hoogvorst, and J.-L. Danger. 2008. An 8x8 run-time reconfigurable FPGA embedded in a SoC. In Proceedings of the 2008 DAC Conference (DAC’08). 120--125.

Digital Library

[10]

Charles Chiasson and Vaughn Betz. 2013. Should FPGAs abandon the pass-gate? In Proceedings of the 2013 FPL Conference (FPL’13). IEEE, Los Alamitos, CA, 1--8.

[11]

W. Deng, D. Yang, T. Ueno, T. Siriburanon, S. Kondo, K. Okada, and A. Matsuzawa. 2015. A fully synthesizable all-digital PLL with interpolative phase coupled oscillator, current-output DAC, and fine-resolution digital varactor using gated edge injection technique. IEEE Journal of Solid-State Circuits 50, 1, 68--80.

[12]

C. Ebeling, D. Cronquist, and P. Franklin. 1996. RaPiD reconfigurable pipelined datapath. In Field-Programmable Logic Smart Applications, New Paradigms and Compilers. Lecture Notes in Computer Science, Vol. 1142. Springer, 126--135.

[13]

E. Fluhr, J. Friedrich, D. M. Dreps, and M. M. Ziegler. 2014. POWER8: A 12-core server-class processor in 22nm SOI with 7.6tb/s off-chip bandwidth. In Proceedings of the 2014 ISSCC Conference (ISSCC’14). IEEE, Los Alamitos, CA, 96--97.

[14]

N. Kafafi, K. Bozman, and S. J. E. Wilton. 2003. architectures and algorithms for synthesizable embedded programmable logic cores. In Proceedings of the 2003 FPGA Conference (FPGA’03). ACM, New York, NY, 3--11.

Digital Library

[15]

Jin Hee Kim and Jason H Anderson. 2015. Synthesizable FPGA fabrics targetable by the Verilog-to-Routing (VTR) CAD flow. In Proceedings of the 2015 FPL Conference (FPL’15). IEEE, Los Alamitos, CA, 1--8.

[16]

Ian Kuon, Aaron Egier, and Jonathan Rose. 2005. Design, layout and verification of an FPGA using automated tools. In Proceedings of the 2005 FPGA Conference (FPGA’05). ACM, New York, NY, 215--226.

Digital Library

[17]

Ian Kuon and Jonathan Rose. 2007. Measuring the gap between FPGAs and ASICs. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 26, 2, 203--215.

Digital Library

[18]

Hao Jun Liu. 2014. Archipelago—An Open Source FPGA with Toolflow Support. Master’s Thesis. University of California at Berkeley.

[19]

J. Luu. 2014. Architecture-Aware Packing and CAD Infrastructure for Field-Programmable Gate Arrays. Ph.D. Dissertation. University of Toronto.

[20]

K. E. Murray, S. Whitty, S. Liu, J. Luu, and V. Betz. 2013. Titan: Enabling large and complex benchmarks in academic CAD. In Proceedings of the 2013 FPL Conference (FPL’13). IEEE, Los Alamitos, CA.

[21]

S. Phillips and S. Hauck. 2002. Automatic layout of domain-specific reconfigurable subsystems for system-on-a-chip. In Proceedings of the 2002 FPGA Conference (FPGA’02). ACM, Los Alamitos, CA, 165--173.

Digital Library

[22]

J. Rose, J. Luu, C. W. Yu, O. Densmore, J. Goeders, A. Somerville, K. B. Kent, P. Jamieson, and J. Anderson. 2012. The VTR project: Architecture and CAD for FPGAs from Verilog to Routing. In Proceedings of the 2012 FPGA Conference (FPGA’12). ACM, New York, NY, 77--86.

Digital Library

[23]

S. Wilton, C. H. Ho, B. Quinton, P. H. W. Leong, and W. Luk. 2007. A synthesizable datapath-oriented embedded FPGA fabric. In Proceedings of the 2007 FPGA Conference (FPGA’07). ACM, New York, NY, 33--41.

Digital Library

[24]

H. Wong, V. Betz, and J. Rose. 2011. Comparing FPGA vs. custom CMOS and the impact on processor microarchitecture. In Proceedings of the 2011 FPGA Conference (FPGA’11). ACM, New York, NY, 5--14.

Digital Library

[25]

S. Yang. 1991. Logic Synthesis and Optimization Benchmarks User Guide Version 3.0. Microelectronics Center of North Carolina.

[26]

Grace Zgheib, Manana Lortkipanidze, Muhsen Owaida, David Novo, and Paolo Ienne. 2016. FPRESSO: Enabling express transistor-level exploration of FPGA architectures. In Proceedings of the 2016 FPGA Conference (FPGA’16).

Digital Library

Cited By

Biscontini APopovici ETemko A(2024)Machine Learning for FPGA Electronic Design AutomationIEEE Access10.1109/ACCESS.2024.351134512(182640-182662)Online publication date: 2024
https://doi.org/10.1109/ACCESS.2024.3511345
Gore GTang XGaillardon P(2023)A Scalable and Area-Efficient Configuration Circuitry for Semi-Custom FPGA DesignIEEE Transactions on Very Large Scale Integration (VLSI) Systems10.1109/TVLSI.2023.327044831:8(1128-1139)Online publication date: 1-Aug-2023
https://dl.acm.org/doi/10.1109/TVLSI.2023.3270448
Chung KDao NYu JKoch DAdler MIenne P(2022)How to Shrink My FPGAs — Optimizing Tile Interfaces and the Configuration Logic in FABulous FPGA FabricsProceedings of the 2022 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays10.1145/3490422.3502371(13-23)Online publication date: 13-Feb-2022
https://dl.acm.org/doi/10.1145/3490422.3502371
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Index Terms

Synthesizable Standard Cell FPGA Fabrics Targetable by the Verilog-to-Routing CAD Flow
1. Computer systems organization
  1. Architectures
    1. Other architectures
      1. Reconfigurable computing
2. Hardware
  1. Electronic design automation
    1. Hardware description languages and compilation

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Published In

cover image ACM Transactions on Reconfigurable Technology and Systems

ACM Transactions on Reconfigurable Technology and Systems Volume 10, Issue 2

Special Section on Field Programmable Logic and Applications 2015 and Regular Papers

June 2017

133 pages

ISSN:1936-7406

EISSN:1936-7414

DOI:10.1145/3068424

Editor:
Steve Wilton
Department of Electrical and Computer Engineering / University of British Columbia / Kaiser 4112, 5500-2332 Main Mall / Vancouver, BC V6T 1Z4 Canada /

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Copyright © 2017 ACM.

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Association for Computing Machinery

New York, NY, United States

Publication History

Published: 06 April 2017

Accepted: 01 November 2016

Revised: 01 October 2016

Received: 01 April 2016

Published in TRETS Volume 10, Issue 2

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Cited By

Biscontini APopovici ETemko A(2024)Machine Learning for FPGA Electronic Design AutomationIEEE Access10.1109/ACCESS.2024.351134512(182640-182662)Online publication date: 2024
https://doi.org/10.1109/ACCESS.2024.3511345
Gore GTang XGaillardon P(2023)A Scalable and Area-Efficient Configuration Circuitry for Semi-Custom FPGA DesignIEEE Transactions on Very Large Scale Integration (VLSI) Systems10.1109/TVLSI.2023.327044831:8(1128-1139)Online publication date: 1-Aug-2023
https://dl.acm.org/doi/10.1109/TVLSI.2023.3270448
Chung KDao NYu JKoch DAdler MIenne P(2022)How to Shrink My FPGAs — Optimizing Tile Interfaces and the Configuration Logic in FABulous FPGA FabricsProceedings of the 2022 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays10.1145/3490422.3502371(13-23)Online publication date: 13-Feb-2022
https://dl.acm.org/doi/10.1145/3490422.3502371
Qiu YCao YDai YYin WWang L(2022)TRAM: An Open-Source Template-based Reconfigurable Architecture Modeling Framework2022 32nd International Conference on Field-Programmable Logic and Applications (FPL)10.1109/FPL57034.2022.00021(61-69)Online publication date: Aug-2022
https://doi.org/10.1109/FPL57034.2022.00021
SUZUKI DHANYU T(2021)Nonvolatile Field-Programmable Gate Array Using a Standard-Cell-Based Design FlowIEICE Transactions on Information and Systems10.1587/transinf.2020LOP0010E104.D:8(1111-1120)Online publication date: 1-Aug-2021
https://doi.org/10.1587/transinf.2020LOP0010
Nakazato YAmagasaki MZhao QIida MKuga M(2021)Automation of Domain-specific FPGA-IP Generation and TestProceedings of the 11th International Symposium on Highly Efficient Accelerators and Reconfigurable Technologies10.1145/3468044.3468048(1-6)Online publication date: 21-Jun-2021
https://dl.acm.org/doi/10.1145/3468044.3468048
Gore GTang XGaillardon PLienig JBehjat LYang S(2021)A Scalable and Robust Hierarchical Floorplanning to Enable 24-hour Prototyping for 100k-LUT FPGAsProceedings of the 2021 International Symposium on Physical Design10.1145/3439706.3447047(135-142)Online publication date: 22-Mar-2021
https://dl.acm.org/doi/10.1145/3439706.3447047
Bao BAnderson J(2021)Dynamic Power Analysis of Standard-Cell FPGA Fabrics2021 IEEE 34th International System-on-Chip Conference (SOCC)10.1109/SOCC52499.2021.9739496(182-187)Online publication date: 14-Sep-2021
https://doi.org/10.1109/SOCC52499.2021.9739496
Razzaq AYe A(2021)Static power model for CMOS and FPGA circuitsIET Computers & Digital Techniques10.1049/cdt2.1202115:4(263-278)Online publication date: 23-Mar-2021
https://doi.org/10.1049/cdt2.12021
Razzaq ASani SYe A(2021)Designing efficient FPGA tiles for power-constrained ultra-low-power applicationsIntegration10.1016/j.vlsi.2021.02.00478(124-134)Online publication date: May-2021
https://doi.org/10.1016/j.vlsi.2021.02.004
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