Article

Automatic layout of domain-specific reconfigurable subsystems for system-on-a-chip

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Shawn Phillips,

Scott HauckAuthors Info & Claims

FPGA '02: Proceedings of the 2002 ACM/SIGDA tenth international symposium on Field-programmable gate arrays

Pages 165 - 173

https://doi.org/10.1145/503048.503073

Published: 24 February 2002 Publication History

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Abstract

When designing SOCs, a unique opportunity exists to generate custom FPGA architectures that are specific to the application domain in which the device will be used. The inclusion of such a device will provide an efficient compromise between the flexibility of software and the performance of hardware, while at the same time allowing for post-fabrication modification of circuits. To automate the layout of reconfigurable subsystems for system-on -a-chip we present template reduction, standard cell, and circuit generator methods. We explore the standard cell method, as well as the creation of FPGA-specific standard cells. Compared to full custom circuits, we achieve designs that are 46% smaller and 36% faster when the application domain is well known in advance. In cases where no reduction from the full functionality is possible, the standard cell approach is 42% larger and 64% slower than full-custom circuits. Standard cells can thus provide competitive implementations, with significantly greater opportunity for adaptation to new domains.

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Cited By

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Grady BAnderson J(2018)Synthesizable Heterogeneous FPGA Fabrics2018 International Conference on Field-Programmable Technology (FPT)10.1109/FPT.2018.00040(222-229)Online publication date: Dec-2018
https://doi.org/10.1109/FPT.2018.00040
Kim JAnderson J(2017)Synthesizable Standard Cell FPGA Fabrics Targetable by the Verilog-to-Routing CAD FlowACM Transactions on Reconfigurable Technology and Systems10.1145/302406310:2(1-23)Online publication date: 6-Apr-2017
https://dl.acm.org/doi/10.1145/3024063
Jin Hee Kim Anderson J(2015)Synthesizable FPGA fabrics targetable by the Verilog-to-Routing (VTR) CAD flow2015 25th International Conference on Field Programmable Logic and Applications (FPL)10.1109/FPL.2015.7293955(1-8)Online publication date: Sep-2015
https://doi.org/10.1109/FPL.2015.7293955
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Automatic layout of domain-specific reconfigurable subsystems for system-on-a-chip
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Published In

FPGA '02: Proceedings of the 2002 ACM/SIGDA tenth international symposium on Field-programmable gate arrays

February 2002

257 pages

ISBN:1581134525

DOI:10.1145/503048

General Chair:
Martine Schlag,
Program Chair:
Steve Trimberger

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

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Association for Computing Machinery

New York, NY, United States

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Published: 24 February 2002

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FPGA02: ACM/SIGDA International Symposium on Field Programmable Gate Arrays

February 24 - 26, 2002

California, Monterey, USA

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Overall Acceptance Rate 125 of 627 submissions, 20%

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Grady BAnderson J(2018)Synthesizable Heterogeneous FPGA Fabrics2018 International Conference on Field-Programmable Technology (FPT)10.1109/FPT.2018.00040(222-229)Online publication date: Dec-2018
https://doi.org/10.1109/FPT.2018.00040
Kim JAnderson J(2017)Synthesizable Standard Cell FPGA Fabrics Targetable by the Verilog-to-Routing CAD FlowACM Transactions on Reconfigurable Technology and Systems10.1145/302406310:2(1-23)Online publication date: 6-Apr-2017
https://dl.acm.org/doi/10.1145/3024063
Jin Hee Kim Anderson J(2015)Synthesizable FPGA fabrics targetable by the Verilog-to-Routing (VTR) CAD flow2015 25th International Conference on Field Programmable Logic and Applications (FPL)10.1109/FPL.2015.7293955(1-8)Online publication date: Sep-2015
https://doi.org/10.1109/FPL.2015.7293955
Chen XZhu JWawrzynek JCompton K(2011)Regular fabric for regular FPGA (abstract only)Proceedings of the 19th ACM/SIGDA international symposium on Field programmable gate arrays10.1145/1950413.1950484(284-284)Online publication date: 27-Feb-2011
https://dl.acm.org/doi/10.1145/1950413.1950484
Chaofan Yu Lingli Wang Xuegong Zhou (2011)Automatic layout generator for embedded FPGA cores2011 9th IEEE International Conference on ASIC10.1109/ASICON.2011.6157202(385-388)Online publication date: Oct-2011
https://doi.org/10.1109/ASICON.2011.6157202
Quinton BWilton S(2009)Programmable logic core enhancements for high-speed on-chip interfacesIEEE Transactions on Very Large Scale Integration (VLSI) Systems10.1109/TVLSI.2008.200142717:9(1334-1339)Online publication date: 1-Sep-2009
https://dl.acm.org/doi/10.1109/TVLSI.2008.2001427
Compton KHauck S(2008)Automatic design of reconfigurable domain-specific flexible coresIEEE Transactions on Very Large Scale Integration (VLSI) Systems10.1109/TVLSI.2007.91543916:5(493-503)Online publication date: 1-May-2008
https://dl.acm.org/doi/10.1109/TVLSI.2007.915439
Parvez HMrabet HMehrez H(2008)Generic techniques and CAD tools for automated generation of FPGA layout2008 Ph.D. Research in Microelectronics and Electronics10.1109/RME.2008.4595745(141-144)Online publication date: Jun-2008
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Mrabet HHusain Parvez Marrakchi ZMehrez HAndre Tissot (2008)Automatic layout generator of domain specific FPGA2008 International Conference on Microelectronics10.1109/ICM.2008.5393493(183-186)Online publication date: Dec-2008
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Chaudhuri SDanger JGuilley S(2007)Efficient Modeling and Floorplanning of Embedded-FPGA Fabric2007 International Conference on Field Programmable Logic and Applications10.1109/FPL.2007.4380741(665-669)Online publication date: Aug-2007
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