research-article

Platform 2012, a many-core computing accelerator for embedded SoCs: performance evaluation of visual analytics applications

Authors:

Diego Melpignano,

Thierry Lepley,

Germain Haugou,

Fabien Clermidy,

Denis DutoitAuthors Info & Claims

DAC '12: Proceedings of the 49th Annual Design Automation Conference

Pages 1137 - 1142

https://doi.org/10.1145/2228360.2228568

Published: 03 June 2012 Publication History

Abstract

P2012 is an area- and power-efficient many-core computing accelerator based on multiple globally asynchronous, locally synchronous processor clusters. Each cluster features up to 16 processors with independent instruction streams sharing a multi-banked one-cycle access L1 data memory, a multi-channel DMA engine and specialized hardware for synchronization and aggressive power management. P2012 is 3D stacking ready and can be customized to achieve extreme area and energy efficiency by adding domain-specific HW IPs to the cluster. The first P2012 SoC prototype in 28nm CMOS will sample in Q3, featuring four 16-processor clusters, a 1MB L2 memory and delivering 80GOPS (with 32 bit single precision floating point support) in 18mm² with 2W power consumption (worst-case). P2012 can run standard OpenCL™ and proprietary Native Programming Model SW components to achieve the highest level of control on application-to-resource mapping. A dedicated version of the OpenCV vision library is provided in the P2012 SW Development Kit to enable visual analytics acceleration. This paper will discuss preliminary performance measurements of common feature extraction and tracking algorithms, parallelized on P2012, versus sequential execution on ARM CPUs.

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Cited By

Hu NWang CZhou X(2022)FLIA: Architecture of Collaborated Mobile GPU and FPGA Heterogeneous ComputingElectronics10.3390/electronics1122375611:22(3756)Online publication date: 16-Nov-2022
https://doi.org/10.3390/electronics11223756
Oh HKim JHwang GLee S(2021)The Design of a 2D Graphics Accelerator for Embedded SystemsElectronics10.3390/electronics1004046910:4(469)Online publication date: 15-Feb-2021
https://doi.org/10.3390/electronics10040469
Penna PSouto JUller JCastro MFreitas HMéhaut J(2021)Inter-kernel communication facility of a distributed operating system for NoC-based lightweight manycoresJournal of Parallel and Distributed Computing10.1016/j.jpdc.2021.04.002154(1-15)Online publication date: Aug-2021
https://doi.org/10.1016/j.jpdc.2021.04.002
Show More Cited By

Index Terms

Platform 2012, a many-core computing accelerator for embedded SoCs: performance evaluation of visual analytics applications
1. Computer systems organization
  1. Architectures
    1. Distributed architectures

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Published In

cover image ACM Conferences

DAC '12: Proceedings of the 49th Annual Design Automation Conference

June 2012

1357 pages

ISBN:9781450311991

DOI:10.1145/2228360

General Chair:
Patrick Groeneveld
Magma Design Automation, Inc., San Jose, CA
,
Program Chairs:
Donatella Sciuto
Politecnico di Milano, Milano, Italy
,
Soha Hassoun
Tufts Univ., Medford, MA

Copyright © 2012 ACM.

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

Sponsors

EDAC: Electronic Design Automation Consortium
SIGDA: ACM Special Interest Group on Design Automation
IEEE-CEDA

In-Cooperation

SIGBED: ACM Special Interest Group on Embedded Systems

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Association for Computing Machinery

New York, NY, United States

Publication History

Published: 03 June 2012

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DAC '12

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EDAC
SIGDA

DAC '12: The 49th Annual Design Automation Conference 2012

June 3 - 7, 2012

California, San Francisco

Acceptance Rates

Overall Acceptance Rate 1,770 of 5,499 submissions, 32%

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DAC '25

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62nd ACM/IEEE Design Automation Conference

June 22 - 26, 2025

San Francisco , CA , USA

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Cited By

Hu NWang CZhou X(2022)FLIA: Architecture of Collaborated Mobile GPU and FPGA Heterogeneous ComputingElectronics10.3390/electronics1122375611:22(3756)Online publication date: 16-Nov-2022
https://doi.org/10.3390/electronics11223756
Oh HKim JHwang GLee S(2021)The Design of a 2D Graphics Accelerator for Embedded SystemsElectronics10.3390/electronics1004046910:4(469)Online publication date: 15-Feb-2021
https://doi.org/10.3390/electronics10040469
Penna PSouto JUller JCastro MFreitas HMéhaut J(2021)Inter-kernel communication facility of a distributed operating system for NoC-based lightweight manycoresJournal of Parallel and Distributed Computing10.1016/j.jpdc.2021.04.002154(1-15)Online publication date: Aug-2021
https://doi.org/10.1016/j.jpdc.2021.04.002
Fellipe Uller JVicente Souto JHenrique Penna PCastro MFreitas HMéhaut J(2021)LWMPI: An MPI library for NoC‐based lightweight manycore processors with on‐chip memory constraintsConcurrency and Computation: Practice and Experience10.1002/cpe.669335:17Online publication date: 8-Nov-2021
https://doi.org/10.1002/cpe.6693
Wittig RHasler MMatus EFettweis G(2019)Queue Based Memory Management Unit for Heterogeneous MPSoCs2019 Design, Automation & Test in Europe Conference & Exhibition (DATE)10.23919/DATE.2019.8715129(1297-1300)Online publication date: Mar-2019
https://doi.org/10.23919/DATE.2019.8715129
Teimouri NTabkhi HSchirner G(2019)Alleviating Scalability Limitation of Accelerator-Based PlatformsIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2018.284663238:7(1317-1330)Online publication date: Jul-2019
https://doi.org/10.1109/TCAD.2018.2846632
Penna PSouto JLima DCastro MBroquedis FFreitas HMehaut J(2019)On the Performance and Isolation of Asymmetric Microkernel Design for Lightweight Manycores2019 IX Brazilian Symposium on Computing Systems Engineering (SBESC)10.1109/SBESC49506.2019.9046080(1-8)Online publication date: Nov-2019
https://doi.org/10.1109/SBESC49506.2019.9046080
Chang XPan HZhang DSun QLin W(2019)A Memory-Optimized and Energy-Efficient CNN Acceleration Architecture Based on FPGA2019 IEEE 28th International Symposium on Industrial Electronics (ISIE)10.1109/ISIE.2019.8781162(2137-2141)Online publication date: Jun-2019
https://doi.org/10.1109/ISIE.2019.8781162
Turki MBertozzi D(2019)An Interconnect-Centric Approach to the Flexible Partitioning and Isolation of Many-Core Accelerators for Fog Computing2019 XXXIV Conference on Design of Circuits and Integrated Systems (DCIS)10.1109/DCIS201949030.2019.8959943(1-6)Online publication date: Nov-2019
https://doi.org/10.1109/DCIS201949030.2019.8959943
Stoutchinin ABenini L(2019)StreamDriveJournal of Signal Processing Systems10.1007/s11265-018-1351-191:3-4(275-301)Online publication date: 1-Mar-2019
https://dl.acm.org/doi/10.1007/s11265-018-1351-1
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