research-article

A Comparative Analysis of Front-End and Back-End Compatible Silicon Photonic On-Chip Interconnects

Authors:

Ishan G. Thakkar,

Sai Vineel Reddy Chittamuru,

Sudeep PasrichaAuthors Info & Claims

SLIP '16: Proceedings of the 18th System Level Interconnect Prediction Workshop

Article No.: 1, Pages 1 - 8

https://doi.org/10.1145/2947357.2947362

Published: 04 June 2016 Publication History

Abstract

Photonic devices fabricated with back-end compatible silicon photonic (BCSP) materials can provide independence from the complex CMOS front-end compatible silicon photonic (FCSP) process, to significantly enhance photonic network-on-chip (PNoC) architecture performance. In this paper, we present a detailed comparative analysis of a number of design tradeoffs for CMOS front-end and back-end compatible devices for silicon photonic interconnects. A cross-layer optimization of multiple device-level and link-level design parameters is performed to enable the design of energy-efficient on-chip photonic interconnects using BCSP devices. The optimized design of BCSP on-chip links renders more energy-efficiency and aggregate bandwidth than FCSP on-chip links, in spite of the inferior opto-electronic properties of BCSP devices. Our experimental analysis compares the use of BCSP and FCSP links at the architecture level, and shows that the optimized design of the BCSP-based Firefly PNoC achieves 1.15x greater throughput and 12.4% less energy-per-bit on average than the optimized design of FCSP-based Firefly PNoC. Similarly, the optimized design of the BCSP-based Corona PNoC achieves 3.5x greater throughput and 39.5% less energy-per-bit on average than the optimized design of FCSP-based Corona PNoC.

References

[1]

S. Feng et al., "Silicon Photonics: from a Microresonator Perspective," in Laser Photonics Rev., vol. 6, no. 2, pp. 145--177, 2012.

[2]

D. J. Thomson et al., "High contrast 40Gbit/s optical modulation in silicon," in Opt. Express, vol. 19, no. 12, p. 11507, 2011.

[3]

S. Liao et al., "36 GHz submicron silicon waveguide germanium photodetector," in Opt. Express, vol. 19, no. 11, p. 10967, 2011.

[4]

L. Vivien et al., "40Gbit/s germanium waveguide photodiode," in OFC/NFOEC, 2013.

[5]

Y. Lee and M. Lipson, "Back-End Deposited Silicon Photonics for Monolithic Integration on CMOS," in IEEE JSTQE, vol. 19, no. 2, 2013.

[6]

I. A. Young et al., "Optical I/O Technology for Tera-Scale Computing," IEEE JSSC, vol. 45, no. 1, pp. 235--248, 2010.

[7]

J. M. Fedeli et al., "Integration issues of a photonic layer on top of a CMOS circuit," in Proc. SPIE {Online}, 2006.

[8]

K. Preston et al.,"Polysilicon photonic resonators for large-scale 3D integration of optical networks," in Opt. Express, vol.15, no.25, 2007.

[9]

N. Sherwood-Droz et al., "Scalable 3D dense integration of photonics on bulk silicon," in Opt. Express, vol. 19, no. 18, p. 17758, 2011.

[10]

A. Gondarenko et al., "High confinement micron-scale silicon nitride high Q ring resonator," in Opt. Express, vol. 17, no. 14, p. 11366, 2009.

[11]

K. Preston et al., "Deposited silicon high-speed integrated electro-optic modulator," in Opt. Express, vol. 17, no. 7, p. 5118, 2009.

[12]

N. Sherwood-Droz et al., "Device Guidelines for WDM Interconnects Using Silicon Microring Resonators", in WINDS, 2010.

[13]

K. Preston et al., "Performance guidelines for WDM interconnects based on silicon microring resonators," in CLEO, 2011.

[14]

Z. Li et al., "Device modeling and system simulation of nanophotonic on-chip networks for reliability, power and performance," DAC, 2011.

Digital Library

[15]

M. Mohamed et al., "Modeling and analysis of micro-ring based silicon photonic interconnect for embedded systems," in CODES+ISSS, 2011.

Digital Library

[16]

N. Ophir et al., "Silicon Photonic Microring Links for High-Bandwidth-Density, Low-Power Chip I/O," in IEEE Micro, 2013.

Digital Library

[17]

R. Hendry et al., "Physical layer analysis and modeling of silicon photonic WDM bus architectures," in Proc. HiPEAC Workshop, 2014.

[18]

D. Vantrease et al., "Light speed arbitration and flow control for nanophotonic interconnects," in Micro, 2009.

Digital Library

[19]

Y. Pan et al., "Firefly: Illuminating Future Network-on-chip with Nanophotonics," in ISCA, 2009.

Digital Library

[20]

K. Padmaraju et al., "Intermodulation crosstalk characteristics of WDM silicon microring modulators," in IEEE PTL, vol. 26, no. 14, 2014.

[21]

W. Bogaerts et al., "Silicon microring resonators," Laser Photonics Rev., vol. 6, no. 1, pp. 47--73, 2012.

[22]

A. Fallahkhair et al., "Vector Finite Difference Modesolver for Anisotropic Dielectric Waveguides," J. Light. Technol., vol. 26, no. 11, 2008.

[23]

Q. Xu et al., "Silicon microring resonators with 1.5-μm radius," in Opt. Express, vol. 16, no. 6, p. 4309, 2008.

[24]

G. T. Reed and A. P. Knights, Silicon Photonics: An Introduction. John Wiley & Sons, 2004.

[25]

R. Soref et al., "Electrooptical effects in silicon," IEEE JQE, vol. 23, no. 1, pp. 123--129, 1987.

[26]

D.A. Neamen, Semiconductor Physics And Devices: Basic Principles, 4th edition. New York, NY: McGraw-Hill, 2011.

[27]

Q. Xu et al., "Micrometre-scale silicon electro-optic modulator," nature, vol. 435, no. 7040, pp. 325--327, 2005.

[28]

G. Li et al., "25Gb/s 1V-driving CMOS ring modulator with integrated thermal tuning," Opt. Express, vol. 19, no. 21, p. 20435, 2011.

[29]

J. Levy, "Integrated nonlinear optics in silicon nitride waveguides and resonators," PhD Thesis, 2011.

[30]

M. Bahadori et al., "Optimization of Microring-based Filters for Dense WDM Silicon Photonic Interconnects," IEEE OI, 2015.

[31]

J. Reis et al., "Architectural optimization of coherent ultra-dense WDM based optical access networks," in OFCC, 2011.

[32]

C. Bienia et al., "The PARSEC Benchmark Suite: Characterization and Architectural Implications," in PACT, 2008.

Digital Library

[33]

N. Binkert et al., "The Gem5 Simulator," in Comp. Arch. News, 2011.

Digital Library

[34]

R. Wu et al., "Compact Modeling and System Implications of Microring Modulators in Nanophotonic Interconnects, " in SLIP, 2015.

[35]

A. Johnson et al., "Chip-based frequency combs with sub-100 GHz repetition rates", in Optics Letters, OSA, 2012.

[36]

D. Moss et al., "New CMOS-compatible platforms based on silicon nitride and Hydex for nonlinear optics", in NPHOTON, 2013.

[37]

D. Pierce et al., "Electronic Structure of Amorphous Si from Photoemission and Optical Studies", in Phys. Rev. B, 1972.

[38]

C. Salzberg et al., "Infrared Refractive Indexes of Silicon Germanium and Modified Selenium Glass", in J. Opt. Soc. Am., 1957.

[39]

S. Chittamuru, I. Thakkar, S. Pasricha, "Process Variation Aware Crosstalk Mitigation for DWDM based Photonic NoC Architectures", in ISQED, 2016.

[40]

A. Udipi et al., "Combining memory and a controller with photonics through 3D-stacking to enable scalable and energy-efficient systems", in ISCA, 2011.

Digital Library

[41]

I. Thakkar, S. Pasricha, "3D-ProWiz: An Energy-Efficient and Optically-Interfaced 3D DRAM Architecture with Reduced Data Access Overhead", in TMSCS, 2015.

[42]

S. Bahirat, S. Pasricha, "Exploring Hybrid Photonic Networks-on-Chip for Emerging Chip Multiprocessors", in CODES+ISSS, 2009.

Digital Library

[43]

S. Pasricha, S. Bahirat, "OPAL: A Multi-Layer Hybrid Photonic NoC for 3D ICs", in ASPDAC, 2011.

Digital Library

[44]

S. Bahirat, S. Pasricha, "A Particle Swarm Optimization Approach for Synthesizing Application-specific Hybrid Photonic Networks-on-Chip", in ISQED, 2012.

Cited By

Karempudi VBashir JThakkar I(2023)An Analysis of Various Design Pathways Towards Multi-Terabit Photonic On-Interposer InterconnectsACM Journal on Emerging Technologies in Computing Systems10.1145/363503120:2(1-34)Online publication date: 1-Dec-2023
https://dl.acm.org/doi/10.1145/3635031
Sunny FNikdast MPasricha S(2023)Design of Sparsity Optimized Photonic Deep Learning AcceleratorsEmbedded Machine Learning for Cyber-Physical, IoT, and Edge Computing10.1007/978-3-031-39932-9_13(329-347)Online publication date: 10-Oct-2023
https://doi.org/10.1007/978-3-031-39932-9_13
Sunny FMirza ANikdast MPasricha S(2023)Co-designing Photonic Accelerators for Machine Learning on the EdgeEmbedded Machine Learning for Cyber-Physical, IoT, and Edge Computing10.1007/978-3-031-39932-9_10(249-269)Online publication date: 10-Oct-2023
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Published In

cover image ACM Conferences

SLIP '16: Proceedings of the 18th System Level Interconnect Prediction Workshop

June 2016

57 pages

ISBN:9781450344302

DOI:10.1145/2947357

General Chair:
Baris Taskin
Drexel University
,
Program Chair:
Tsung-Yi Ho
National Tsing Hua University, Taiwan

Copyright © 2016 ACM.

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Published: 04 June 2016

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Cited By

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https://dl.acm.org/doi/10.1145/3635031
Sunny FNikdast MPasricha S(2023)Design of Sparsity Optimized Photonic Deep Learning AcceleratorsEmbedded Machine Learning for Cyber-Physical, IoT, and Edge Computing10.1007/978-3-031-39932-9_13(329-347)Online publication date: 10-Oct-2023
https://doi.org/10.1007/978-3-031-39932-9_13
Sunny FMirza ANikdast MPasricha S(2023)Co-designing Photonic Accelerators for Machine Learning on the EdgeEmbedded Machine Learning for Cyber-Physical, IoT, and Edge Computing10.1007/978-3-031-39932-9_10(249-269)Online publication date: 10-Oct-2023
https://doi.org/10.1007/978-3-031-39932-9_10
Karempudi VSunny FThakkar IChittamuru SNikdast MPasricha S(2022)Photonic Networks-on-Chip Employing Multilevel Signaling: A Cross-Layer Comparative StudyACM Journal on Emerging Technologies in Computing Systems10.1145/348736518:3(1-36)Online publication date: 22-Mar-2022
https://dl.acm.org/doi/10.1145/3487365
Karempudi VDatta SThakkar I(2021)Design Exploration and Scalability Analysis of a CMOS-Integrated, Polymorphic, Nanophotonic Arithmetic-Logic UnitProceedings of the 19th ACM Conference on Embedded Networked Sensor Systems10.1145/3485730.3494042(628-634)Online publication date: 15-Nov-2021
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Vatsavai SKarempudi VThakkar I(2020)PROTEUS: Rule-Based Self-Adaptation in Photonic NoCs for Loss-Aware Co-Management of Laser Power and Performance2020 14th IEEE/ACM International Symposium on Networks-on-Chip (NOCS)10.1109/NOCS50636.2020.9241712(1-8)Online publication date: 24-Sep-2020
https://doi.org/10.1109/NOCS50636.2020.9241712
Pasricha SNikdast M(2020)A Survey of Silicon Photonics for Energy-Efficient Manycore ComputingIEEE Design & Test10.1109/MDAT.2020.298262837:4(60-81)Online publication date: Aug-2020
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Pasricha SChittamuru SThakkar IBhat VLu ZVangal SXu JBogdan P(2018)Securing photonic NoC architectures from hardware trojansProceedings of the Twelfth IEEE/ACM International Symposium on Networks-on-Chip10.5555/3306619.3306634(1-8)Online publication date: 4-Oct-2018
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Pasricha SChittamuru SThakkar IChen DHomayoun HTaskin B(2018)Cross-Layer Thermal Reliability Management in Silicon Photonic Networks-on-ChipProceedings of the 2018 Great Lakes Symposium on VLSI10.1145/3194554.3194608(317-322)Online publication date: 30-May-2018
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Chittamuru SThakkar IPasricha S(2018)HYDRA: Heterodyne Crosstalk Mitigation With Double Microring Resonators and Data Encoding for Photonic NoCsIEEE Transactions on Very Large Scale Integration (VLSI) Systems10.1109/TVLSI.2017.274996726:1(168-181)Online publication date: Jan-2018
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