research-article

Improving the Reliability and Energy-Efficiency of High-Bandwidth Photonic NoC Architectures with Multilevel Signaling

Authors:

Ishan G. Thakkar,

Sai Vineel Reddy Chittamuru,

Sudeep PasrichaAuthors Info & Claims

NOCS '17: Proceedings of the Eleventh IEEE/ACM International Symposium on Networks-on-Chip

Article No.: 4, Pages 1 - 8

https://doi.org/10.1145/3130218.3130226

Published: 19 October 2017 Publication History

Abstract

Photonic network-on-chip (PNoC) architectures employ photonic waveguides with dense-wavelength-division-multiplexing (DWDM) for signal traversal and microring resonators (MRs) for on-off-keying (OOK) based signal modulation, to enable high bandwidth on-chip transfers. Unfortunately, the use of larger number of DWDM wavelengths to achieve higher bandwidth requires sophisticated and costly laser sources along with extra photonic hardware, which adds extra noise and increases the power and area consumption of PNoCs. This paper presents a novel method (called 4-PAM-P) of generating four-amplitude-level optical signals in PNoCs, which doubles the aggregate bandwidth without increasing utilized wavelengths, photonic hardware, and incurred noise, thereby reducing the bit-error-rate (BER), area, and energy consumption of PNoCs. Our experimental analysis shows that our 4-PAM-P signaling method achieves equal bandwidth with 4.2x better BER, 19.5% lower power, 16.3% lower energy-per-bit, and 5.6% less photonic area compared to the best known 4-amplitude-level optical signaling method from prior work.

References

[1]

L. Zhou, A. K. Kodi, "PROBE: Prediction-based optical bandwidth scaling for energy-efficient NoCs," in NOCS, 2013.

[2]

S. Pasricha, S. Bahirat, "OPAL: A Multi-Layer Hybrid Photonic NoC for 3D ICs", in IEEE/ACM ASPDAC, Jan 2011.

Digital Library

[3]

S. Bahirat, S. Pasricha, "METEOR: Hybrid Photonic Ring-Mesh Network-on-Chip for Multicore Architectures", in TECS, 13(3), 2014.

Digital Library

[4]

T. Kao et al., "Design of High Bandwidth Photonic Network-on-Chip Architectures Using Optical Multilevel Signaling," in NOCS, 2016.

[5]

C. H. Chen et al., "A comb laser-driven DWDM silicon photonic transmitter based on microring modulators", in OE, 23(16), 2015.

[6]

S.V.R. Chittamuru et al., "PICO: Mitigating Heterodyne Crosstalk Due to Process Variations and Intermodulation Effects in Photonic NoCs", in DAC, 2016.

Digital Library

[7]

T. J. Kao et al., "Optical Multilevel Signaling for High Bandwidth and Power-Efficient On-Chip Interconnects", in PTL, 27(19), 2015.

[8]

S. V. R. Chittamuru, et al., "SWIFTNoC: A Reconfigurable Silicon-Photonic Network with Multicast Enabled Channel Sharing for Multicore Architectures," in ACM Journal on Emerging Technologies in Computing Systems (JETC), vol. 13(4), no. 58, Feb. 2017.

Digital Library

[9]

S. V. R. Chittamuru et al., "Crosstalk Mitigation for High-Radix and Low-Diameter Photonic NoC Architectures", in IEEE Design and Test, 2015.

[10]

I. Thakkar et al., "A Comparative Analysis of Front-End and BackEnd Compatible Silicon Photonic On-Chip Interconnects", SLIP, 2016.

Digital Library

[11]

I. Thakkar, et al., "Mitigation of Homodyne Crosstalk Noise in Silicon Photonic NoC Architectures with Tunable Decoupling," in ACM/IEEE International Conference on Hardware/Software Codesign and System Synthesis (CODES+ISSS), Oct. 2016.

Digital Library

[12]

T. Y. Elganimi, "Performance Comparison between OOK, PPM and PAM Modulation Schemes for Free Space Optical (FSO) Communication Systems: Analytical Study", in IJCA, 79(11), 2013.

[13]

I. Thakkar, et al., "Run-Time Laser Power Management in Photonic NoCs with On-Chip Semiconductor Optical Amplifiers," in IEEE/ACM International Symposium on Networks-on-Chip (NOCS), Aug. 2016.

[14]

S. K. Selvaraja., "Wafer-Scale Fabrication Technology for Silicon Photonic Integrated Circuits," PhD thesis, Ghent University, 2011.

[15]

C. Bienia et al., "The PARSEC Benchmark Suite: Characterization and Architectural Implications," in PACT, 2008.

Digital Library

[16]

N. Binkert et al., "The Gem5 Simulator," in Comp. Arch. News, 2011.

Digital Library

[17]

C. Sun et al., "DSENT---A tool connecting emerging photonics with electronics for opto-electronic networks-on-chip modeling," in NOCS, 2012.

Digital Library

[18]

K. Padmaraju et al., "Wavelength Locking and Thermally Stabilizing Microring Resonators Using Dithering Signals", JLT, 32(3), 2014.

[19]

R. D.-Demers et al., "Ultrafast pulse-amplitude modulation with a femtojoule silicon photonic modulator", Optica, 3(6), 2016.

[20]

K. Szczerba et al., "4-PAM for High-Speed Short-Range Optical Communications", JOCN, 4(11), 2012.

[21]

A. Roshan-Zamir et al., "A 40 Gb/s PAM4 silicon microring resonator modulator transmitter in 65nm CMOS", in OIC, 2016.

[22]

S. Moazeni and V. Stojanovic. Technical Report No. UCB/EECS-2017-23. http://www2.eecs.berkeley.edu/Pubs/TechRpts/2017/EECS-2017-23.html.

[23]

K. Padmaraju and K. Bergman. "Resolving the thermal challenges for silicon microring resonator devices," Nanophotonics, 3(4-5), 2014.

[24]

M. Bahadori, "Optimization of Microring-based Filters for Dense WDM Silicon Photonic Interconnects", IEEE OI, 2015.

[25]

I. Thakkar, S. Pasricha, "3D-Wiz: A Novel High Bandwidth, Optically Interfaced 3D DRAM Architecture with Reduced Random Access Time," ICCD, Oct 2014.

[26]

I. Thakkar, S. Pasricha, "3D-ProWiz: An Energy-Efficient and Optically-Interfaced 3D DRAM Architecture with Reduced Data Access Overhead", IEEE TMSCS, 2015.

[27]

M. Bahadori et al., "Crosstalk Penalty in Microring-Based Silicon Photonic Interconnect Systems", JLT, 34(17), pp. 4043--4052, 2016.

[28]

S. V. R. Chittamuru et al., "Analyzing Voltage Bias and Temperature Induced Aging Effects in Photonic Interconnects for Manycore Computing", SLIP, 2017.

[29]

R. Wu et al., "Compact Modeling and System Implications of Microring Modulators in Nanophotonic Interconnects", in SLIP, 2015.

[30]

R. Hendry et al., "Physical layer analysis and modeling of silicon photonic WDM bus architectures," in Proc. HiPEAC Workshop, 2014.

[31]

S. Sarangi et al., "Varius: A model of process variation and resulting timing errors for microarchitects," IEEE TSM, 21(1), pp. 3--13, 2008.

[32]

Y. Xu, S. Pasricha, "Silicon Nanophotonics for Future Multicore Architectures: Opportunities and Challenges", IEEE D&T, pp. 9--17, Sept/Oct 2014.

Cited By

Sunny FTaheri ENikdast MPasricha S(2023)Machine Learning Accelerators in 2.5D Chiplet Platforms with Silicon Photonics2023 Design, Automation & Test in Europe Conference & Exhibition (DATE)10.23919/DATE56975.2023.10137317(1-6)Online publication date: Apr-2023
https://doi.org/10.23919/DATE56975.2023.10137317
Karempudi VBashir JThakkar I(2023)An Analysis of Various Design Pathways Towards Multi-Terabit Photonic On-Interposer InterconnectsACM Journal on Emerging Technologies in Computing Systems10.1145/363503120:2(1-34)Online publication date: 1-Dec-2023
https://dl.acm.org/doi/10.1145/3635031
Baharloo MAbdollahi MBaniasadi A(2023)System-level reliability assessment of optical network on chipMicroprocessors and Microsystems10.1016/j.micpro.2023.10484399(104843)Online publication date: Jun-2023
https://doi.org/10.1016/j.micpro.2023.104843
Show More Cited By

Index Terms

Improving the Reliability and Energy-Efficiency of High-Bandwidth Photonic NoC Architectures with Multilevel Signaling
1. Hardware
  1. Integrated circuits
    1. Interconnect
      1. Photonic and optical interconnect
2. Networks
  1. Network types
    1. Network on chip

Recommendations

A Comparative Analysis of Front-End and Back-End Compatible Silicon Photonic On-Chip Interconnects
SLIP '16: Proceedings of the 18th System Level Interconnect Prediction Workshop

Photonic devices fabricated with back-end compatible silicon photonic (BCSP) materials can provide independence from the complex CMOS front-end compatible silicon photonic (FCSP) process, to significantly enhance photonic network-on-chip (PNoC) ...
Photonic Networks-on-Chip Employing Multilevel Signaling: A Cross-Layer Comparative Study
Photonic network-on-chip (PNoC) architectures employ photonic links with dense wavelength-division multiplexing (DWDM) to enable high throughput on-chip transfers. Unfortunately, increasing the DWDM degree (i.e., using a larger number of wavelengths) to ...
Mitigation of homodyne crosstalk noise in silicon photonic NoC architectures with tunable decoupling
CODES '16: Proceedings of the Eleventh IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis

Photonic network-on-chip (PNoC) architectures employ photonic waveguides with dense-wavelength-division-multiplexing (DWDM) for signal traversal and microring resonators (MRs) for signal modulation, to enable high bandwidth on-chip transfers. ...

Comments

Information & Contributors

Information

Published In

cover image ACM Conferences

NOCS '17: Proceedings of the Eleventh IEEE/ACM International Symposium on Networks-on-Chip

October 2017

170 pages

ISBN:9781450349840

DOI:10.1145/3130218

Copyright © 2017 ACM.

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

Sponsors

Publisher

Association for Computing Machinery

New York, NY, United States

Publication History

Published: 19 October 2017

Permissions

Request permissions for this article.

Request Permissions

Check for updates

Author Tags

Qualifiers

Research-article
Research
Refereed limited

Conference

NOCS '17

Sponsor:

NOCS '17: International Symposium on Networks-on-Chip

October 19 - 20, 2017

Seoul, Republic of Korea

Acceptance Rates

NOCS '17 Paper Acceptance Rate 14 of 44 submissions, 32%;

Overall Acceptance Rate 14 of 44 submissions, 32%

Contributors

Other Metrics

View Article Metrics

Bibliometrics & Citations

Bibliometrics

Article Metrics

25
Total Citations
View Citations
1,182
Total Downloads

Downloads (Last 12 months)352
Downloads (Last 6 weeks)58

Reflects downloads up to 11 Feb 2025

Other Metrics

View Author Metrics

Citations

Cited By

Sunny FTaheri ENikdast MPasricha S(2023)Machine Learning Accelerators in 2.5D Chiplet Platforms with Silicon Photonics2023 Design, Automation & Test in Europe Conference & Exhibition (DATE)10.23919/DATE56975.2023.10137317(1-6)Online publication date: Apr-2023
https://doi.org/10.23919/DATE56975.2023.10137317
Karempudi VBashir JThakkar I(2023)An Analysis of Various Design Pathways Towards Multi-Terabit Photonic On-Interposer InterconnectsACM Journal on Emerging Technologies in Computing Systems10.1145/363503120:2(1-34)Online publication date: 1-Dec-2023
https://dl.acm.org/doi/10.1145/3635031
Baharloo MAbdollahi MBaniasadi A(2023)System-level reliability assessment of optical network on chipMicroprocessors and Microsystems10.1016/j.micpro.2023.10484399(104843)Online publication date: Jun-2023
https://doi.org/10.1016/j.micpro.2023.104843
Sunny FNikdast MPasricha S(2023)Design of Sparsity Optimized Photonic Deep Learning AcceleratorsEmbedded Machine Learning for Cyber-Physical, IoT, and Edge Computing10.1007/978-3-031-39932-9_13(329-347)Online publication date: 10-Oct-2023
https://doi.org/10.1007/978-3-031-39932-9_13
Sunny FMirza ANikdast MPasricha S(2023)Co-designing Photonic Accelerators for Machine Learning on the EdgeEmbedded Machine Learning for Cyber-Physical, IoT, and Edge Computing10.1007/978-3-031-39932-9_10(249-269)Online publication date: 10-Oct-2023
https://doi.org/10.1007/978-3-031-39932-9_10
Peng JAlkabani YFavry EMehrabian ASun SSorger VEl-Ghazawi T(2023)Adaptive Routing for Hybrid Photonic–Plasmonic (HyPPI) Interconnection Network for Manycore Processors Using DDDAS on the ChipHandbook of Dynamic Data Driven Applications Systems10.1007/978-3-031-27986-7_34(903-925)Online publication date: 6-Sep-2023
https://doi.org/10.1007/978-3-031-27986-7_34
Karempudi VSunny FThakkar IChittamuru SNikdast MPasricha S(2022)Photonic Networks-on-Chip Employing Multilevel Signaling: A Cross-Layer Comparative StudyACM Journal on Emerging Technologies in Computing Systems10.1145/348736518:3(1-36)Online publication date: 22-Mar-2022
https://dl.acm.org/doi/10.1145/3487365
Thakkar IChittamuru SBhat VVatsavai SPasricha S(2022)Hardware Security in Emerging Photonic Network-on-Chip ArchitecturesEmerging Computing: From Devices to Systems10.1007/978-981-16-7487-7_9(291-313)Online publication date: 9-Jul-2022
https://doi.org/10.1007/978-981-16-7487-7_9
Karempudi VDatta SThakkar I(2021)Design Exploration and Scalability Analysis of a CMOS-Integrated, Polymorphic, Nanophotonic Arithmetic-Logic UnitProceedings of the 19th ACM Conference on Embedded Networked Sensor Systems10.1145/3485730.3494042(628-634)Online publication date: 15-Nov-2021
https://dl.acm.org/doi/10.1145/3485730.3494042
Abdollahi MBaharloo MShokouhinia FEbrahimi M(2021)RAP-NoCProceedings of the Eight Annual ACM International Conference on Nanoscale Computing and Communication10.1145/3477206.3477455(1-7)Online publication date: 7-Sep-2021
https://dl.acm.org/doi/10.1145/3477206.3477455
Show More Cited By

View Options

Login options

Check if you have access through your login credentials or your institution to get full access on this article.

Full Access

Get this Publication

View options

PDF

View or Download as a PDF file.

eReader

View online with eReader.

Figures

Tables

Media

View Table of Conten