research-article

Improving scan chain diagnostic accuracy using multi-stage artificial neural networks

Authors:

Kun-Han (Hans) Tsai,

Wu-Tung ChengAuthors Info & Claims

ASPDAC '19: Proceedings of the 24th Asia and South Pacific Design Automation Conference

Pages 341 - 346

https://doi.org/10.1145/3287624.3287692

Published: 21 January 2019 Publication History

Abstract

Diagnosis of intermittent scan chain failures remains a hard problem. We demonstrate that Artificial Neural Networks (ANNs) can be used to achieve significantly higher accuracy. The key is to take on domain knowledge and use a multi-stage process incorporating ANNs with gradually refined focuses. Experimental results on benchmark circuits show that this method is, on average, 20% more accurate than a state-of-the-art commercial tool for intermittent stuck-at faults, and improves the hit rate from 25.3% to 73.9% for some test-case.

References

[1]

S. Kundu, "On Diagnosis of Faults in a Scan Chain," Proc. of VLSI Test Symposium (VTS), pp. 303--308, 1993.

[2]

R. Guo and S. Venkataraman, "A Technique for Fault Diagnosis of Defects in Scan Chains," Proc. of Int'l Test Conf. (ITC), pp. 268--277, 2001.

Digital Library

[3]

Y. Huang, R Guo, W.T. Cheng, and J. C.-M. Li, "Survey of Scan Chain Diagnosis", IEEE Design & Test of Computers, Vol. 25, No. 3, pp.240--248, 2008.

Digital Library

[4]

J. Hirase, "Scan Chain Diagnosis Using Iddq Current Measurement," Proc. of Asian Test Symposium (ATS), pp. 153--157, 1999.

Digital Library

[5]

P. Song et al., "A Novel Scan Chain Diagnostics Technique Based on Light Emission from Leakage Current", Proc. of Int'l Test Conf., pp. 140--147, 2004.

Digital Library

[6]

K. Khusyari, W.T. Ng, N. Jaarsma, R. Abraham, P. W. Ng, B. H. Ang, and C. H Ong, "Diagnosis of Voltage Dependent Scan Chain Failure Using VBUMP Scan Debug Method", Proc. Asian Test Symp., pp 271, 2008.

Digital Library

[7]

J. Hwang et al., "Deterministic Localization and Analysis of Scan Hold-Time Faults", Proc. Int'l Symp. for Testing and Failure Analysis, pp. 396--401, 2008.

[8]

J. L. Schafer, "Partner SRLs for Improved Shift Register Diagnosis," Proc. of VLSI Test Symposium (VTS), pp. 198--201, 1992.

[9]

S. Edirisooriva and G. Edirisooriva, "Diagnosis of Scan Path Failures," Prof. of VLSI Test Symposium (VTS), pp. 250--255, 1995.

Digital Library

[10]

S. Narayanan and A. Das, "An Efficient Scheme to Diagnose Scan Chains," Proc. of Int'l Test Conf. (ITC), pp.704--713, 1997.

Digital Library

[11]

Y. Wu, "Diagnosis of Scan Chain Failures," Prof. of Int'l Symp. on Defect and Fault Tolerance in VLSI Systems (DFT), pp. 217--222, 1998.

Digital Library

[12]

K. Stanley, "High-Accuracy Flush-and-Scan Software Diagnostics," IEEE Design and Test of Computers, pp. 56--62, 2001.

Digital Library

[13]

Y. Huang et al., "Using Fault Model Relaxation to Diagnose Real Scan Chain Defects", Proc. Asia and South Pacific Design Automation Conf., 2005, pp. 1176--1179.

Digital Library

[14]

Y. Huang, "Dynamic Learning Based Scan Chain Diagnosis", Proc. Design, Automation & Test in Europe, pp.510--515, 2007.

Digital Library

[15]

J.C.-M. Li, "Diagnosis of Single Stuck-At Faults and Multiple Timing Faults in Scan Chains", IEEE Trans. Very Large Scale Integration (VLSI) Systems, Vol. 13, No. 6, pp. 708--718, 2005.

Digital Library

[16]

J.-S. Yang and S.-Y. Huang, "Quick Scan Chain Diagnosis Using Signal Profiling", Proc. of Int'l Conf. on Computer Design, Oct., pp. 157--160, 2005.

Digital Library

[17]

J.-J. Hsu, C.-W. Tzeng, and S.-Y. Huang, "A New Robust Paradigm for Diagnosing Hold-Time Faults in Scan Chains," Proc. IEEE Int'l Symp. on VLSI Design, Automation and Test, pp 171--174, 2006.

[18]

C.-W. Tzeng, J.-J. Hsu, and S-.Y. Huang, "A Robust Paradigm for Diagnosing Hold-Time Faults in Scan Chains," IET Proc. on Computers and Digital Techniques, Vol. 1, No. 6, pp. 706--715, 2007.

[19]

Y. Huang, W.-T. Cheng, R. Kuo, T.-P. Tai, F.-M. Kuo, Y.-S. Chen, "Scan Chain Diagnosis by Adaptive Signal Profiling with Manufacturing ATPG Patterns", Proc. Asian Test Symp., pp.35--40, 2009.

Digital Library

[20]

Y. Huang, W.-T. Cheng, S.-M. Reddy, C.-J. Hsieh, and Y.-T. Hung, "Statistical Diagnosis for Intermittent Scan Chain Hold-Time Fault," Proc. of Int'l Test Conf. (ITC), pp. 319--328, 2003.

[21]

Y. Huang, B. Benware, R. Klingenberg, H. Tang, Jayant Dsouza and W.-T. Cheng, "Scan Chain Diagnosis Based on Unsupervised Machine Learning", Proc. of Asian Test Symp. (ATS), 2017.

[22]

J. Li, Y. Huang, W.-T. Cheng, C. Schuermyer, and D. Xiang, "A Supervised ANN Method for Memory Failure Signature Classification", Proc. of Solid-State and Integrated Circuit Technology, pp. 1--3, 2012.

[23]

D. J.C. Mackay, "Information Theory, Inference, and Learning Algorithms", Cambridge University Press, 2005.

Digital Library

[24]

"TensorFlow. Large-Scale Machine Learning on Heterogeneous Systems" Google Research. November 9, 2015.

Cited By

Zeng YCui X(2024)A High Performance PODEM Algorithm with the Improved Backtrace Process2024 IEEE International Test Conference in Asia (ITC-Asia)10.1109/ITC-Asia62534.2024.10661307(1-6)Online publication date: 18-Aug-2024
https://doi.org/10.1109/ITC-Asia62534.2024.10661307
Roy SMillican SAgrawal V(2024)A Survey and Recent Advances: Machine Intelligence in Electronic TestingJournal of Electronic Testing10.1007/s10836-024-06117-740:2(139-158)Online publication date: 15-Apr-2024
https://doi.org/10.1007/s10836-024-06117-7
Kim SJang SKang S(2023)Scan Chain Architecture With Data Duplication for Multiple Scan Cell Fault DiagnosisIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2022.322489942:8(2717-2727)Online publication date: Aug-2023
https://doi.org/10.1109/TCAD.2022.3224899
Show More Cited By

Recommendations

Characterizing and improving the fault tolerance of artificial neural networks
Acute appendicitis diagnosis using artificial neural networks
Papers from the 3rd International Conference on Biomedical Engineering and Technology (iCBEB 2014), 25–28 September 2014, Beijing, China

BACKGROUND: Artificial neural networks is one of pattern analyzer method which are rapidly applied on a bio-medical field.

OBJECTIVE: The aim of this research was to propose an appendicitis diagnosis system using artificial neural networks (ANNs).

METHODS: ...
Evolving feedforward artificial neural networks using a two-stage approach
Highlights
- A collaborative binary-real DE is developed for optimization problem with mixed variables.
Abstract
This paper presents a two-stage approach, denoted as CBRDE-LM, to evolve the architecture and weights of feedforward artificial neural networks. In the first stage, a collaborative binary-real differential evolution (CBRDE) is used to ...

Comments

Information & Contributors

Information

Published In

cover image ACM Conferences

ASPDAC '19: Proceedings of the 24th Asia and South Pacific Design Automation Conference

January 2019

794 pages

ISBN:9781450360074

DOI:10.1145/3287624

General Chair:
Toshiyuki Shibuya
Fujitsu Laboratories

Copyright © 2019 ACM.

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

Sponsors

SIGDA: ACM Special Interest Group on Design Automation

In-Cooperation

IEICE ESS: Institute of Electronics, Information and Communication Engineers, Engineering Sciences Society
IEEE CAS
IEEE CEDA
IPSJ SIG-SLDM: Information Processing Society of Japan, SIG System LSI Design Methodology

Publisher

Association for Computing Machinery

New York, NY, United States

Publication History

Published: 21 January 2019

Permissions

Request permissions for this article.

Request Permissions

Check for updates

Qualifiers

Research-article

Conference

ASPDAC '19

Sponsor:

SIGDA

ASPDAC '19: 24th Asia and South Pacific Design Automation Conference

January 21 - 24, 2019

Tokyo, Japan

Acceptance Rates

Overall Acceptance Rate 466 of 1,454 submissions, 32%

Upcoming Conference

ASPDAC '25

Sponsor:
sigda

30th Asia and South Pacific Design Automation Conference

January 20 - 23, 2025

Tokyo , Japan

Contributors

Other Metrics

View Article Metrics

Bibliometrics & Citations

Bibliometrics

Article Metrics

12
Total Citations
View Citations
230
Total Downloads

Downloads (Last 12 months)9
Downloads (Last 6 weeks)1

Reflects downloads up to 04 Oct 2024

Other Metrics

View Author Metrics

Citations

Cited By

Zeng YCui X(2024)A High Performance PODEM Algorithm with the Improved Backtrace Process2024 IEEE International Test Conference in Asia (ITC-Asia)10.1109/ITC-Asia62534.2024.10661307(1-6)Online publication date: 18-Aug-2024
https://doi.org/10.1109/ITC-Asia62534.2024.10661307
Roy SMillican SAgrawal V(2024)A Survey and Recent Advances: Machine Intelligence in Electronic TestingJournal of Electronic Testing10.1007/s10836-024-06117-740:2(139-158)Online publication date: 15-Apr-2024
https://doi.org/10.1007/s10836-024-06117-7
Kim SJang SKang S(2023)Scan Chain Architecture With Data Duplication for Multiple Scan Cell Fault DiagnosisIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2022.322489942:8(2717-2727)Online publication date: Aug-2023
https://doi.org/10.1109/TCAD.2022.3224899
Zhao ZCai Z(2023)A Review of Intelligent Design for Test Based on Machine Learning2023 International Symposium of Electronics Design Automation (ISEDA)10.1109/ISEDA59274.2023.10218713(116-120)Online publication date: 8-May-2023
https://doi.org/10.1109/ISEDA59274.2023.10218713
Amuru DZahra AVudumula HCherupally PGurram SAhmad AAbbas Z(2023)AI/ML algorithms and applications in VLSI design and technologyIntegration, the VLSI Journal10.1016/j.vlsi.2023.06.00293:COnline publication date: 1-Nov-2023
https://dl.acm.org/doi/10.1016/j.vlsi.2023.06.002
Sun YMillican S(2022)Applying Artificial Neural Networks to Logic Built-in Self-test: Improving Test Point InsertionJournal of Electronic Testing10.1007/s10836-022-06016-938:4(339-352)Online publication date: 4-Aug-2022
https://doi.org/10.1007/s10836-022-06016-9
Roy SMillican SAgrawal V(2021)Special Session – Machine Learning in Test: A Survey of Analog, Digital, Memory, and RF Integrated Circuits2021 IEEE 39th VLSI Test Symposium (VTS)10.1109/VTS50974.2021.9441051(1-14)Online publication date: 25-Apr-2021
https://doi.org/10.1109/VTS50974.2021.9441051
Roy SMillican SAgrawal V(2021)Training Neural Network for Machine Intelligence in Automatic Test Pattern Generator2021 34th International Conference on VLSI Design and 2021 20th International Conference on Embedded Systems (VLSID)10.1109/VLSID51830.2021.00059(316-321)Online publication date: Feb-2021
https://doi.org/10.1109/VLSID51830.2021.00059
Lim HCheong MKang S(2020)Scan-Chain-Fault Diagnosis Using Regressions in Cryptographic Chips for Wireless Sensor NetworksSensors10.3390/s2017477120:17(4771)Online publication date: 24-Aug-2020
https://doi.org/10.3390/s20174771
Chern MLee SHuang SHuang YVeda GTsai KCheng W(2020)Diagnosis of Intermittent Scan Chain Faults Through a Multistage Neural Network Reasoning ProcessIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems10.1109/TCAD.2019.295735639:10(3044-3055)Online publication date: Oct-2020
https://doi.org/10.1109/TCAD.2019.2957356
Show More Cited By

View Options

Get Access

Login options

Check if you have access through your login credentials or your institution to get full access on this article.

Full Access

Get this Publication

View options

PDF

View or Download as a PDF file.

eReader

View online with eReader.

Media

Figures

Other

Tables

View Table of Contents