research-article

InterLock: an intercorrelated logic and routing locking

Authors:

Hadi Mardani Kamali,

Kimia Zamiri Azar,

Houman Homayoun,

Avesta SasanAuthors Info & Claims

ICCAD '20: Proceedings of the 39th International Conference on Computer-Aided Design

Article No.: 78, Pages 1 - 9

https://doi.org/10.1145/3400302.3415667

Published: 17 December 2020 Publication History

Abstract

In this paper, we propose a canonical prune-and-SAT (CP&SAT) attack for breaking state-of-the-art routing-based obfuscation techniques. In the CP&SAT attack, we first encode the key-programmable routing blocks (keyRBs) based on an efficient SAT encoding mechanism suited for detailed routing constraints, and then efficiently re-encode and reduce the CNF corresponded to the keyRB using a bounded variable addition (BVA) algorithm. In the CP&SAT attack, this is done before subjecting the circuit to the SAT attack. We illustrate that this encoding and BVA-based pre-processing significantly reduces the size of the CNF corresponded to the routing-based obfuscated circuit, in the result of which we observe 100% success rate for breaking prior art routing-based obfuscation techniques. Further, we propose a new intercorrelated logic and routing locking technique, or in short InterLock, as a countermeasure to mitigate the CP&SAT attack. In Interlock, in addition to hiding the connectivity, a part of the logic (gates) in the selected timing paths are also implemented in the keyRB(s). We illustrate that when the logic gates are twisted with keyRBs, the BVA could not provide any advantage as a pre-processing step. Our experimental results show that, by using InterLock, with only three 8×8 or only two 16×16 keyRBs (twisted with actual logic gates), the resilience against existing attacks as well as our new proposed CP&SAT attack would be guaranteed while, on average, the delay/area overhead is less than 10% for even medium-size benchmark circuits.

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cover image ACM Conferences

ICCAD '20: Proceedings of the 39th International Conference on Computer-Aided Design

November 2020

1396 pages

ISBN:9781450380263

DOI:10.1145/3400302

General Chair:
Yuan Xie
Univ. of California, Santa Barbara, CA

Copyright © 2020 ACM.

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Published: 17 December 2020

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https://doi.org/10.23919/DATE58400.2024.10546894
McDaniel IZuzak MSrivastava A(2024)Removal of SAT-Hard Instances in Logic Obfuscation Through Inference of FunctionalityACM Transactions on Design Automation of Electronic Systems10.1145/367490329:4(1-23)Online publication date: 25-Jun-2024
https://dl.acm.org/doi/10.1145/3674903
Wang JChen ZZhang JXu YYu TZheng ZYe EGeorge SYang HLiu YNi KNarayanan VLi X(2024)A Module-Level Configuration Methodology for Programmable Camouflaged LogicACM Transactions on Design Automation of Electronic Systems10.1145/364046229:2(1-31)Online publication date: 14-Feb-2024
https://dl.acm.org/doi/10.1145/3640462
Halder DLiu YAmberiadis KSrivastava ARay S(2024)PoTeNt: Post-Synthesis Obfuscation for Secure Network-on-Chip Architectures2024 IEEE 37th International System-on-Chip Conference (SOCC)10.1109/SOCC62300.2024.10737820(1-6)Online publication date: 16-Sep-2024
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Zhang YHalak BWang H(2024)ZeKi: A Zero-Knowledge Dynamic Logic Locking Implementation with Resilience to Multiple Attacks2024 IEEE 37th International System-on-Chip Conference (SOCC)10.1109/SOCC62300.2024.10737800(1-6)Online publication date: 16-Sep-2024
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Tehranipoor MZamiri Azar KAsadizanjani NRahman FMardani Kamali HFarahmandi FTehranipoor MZamiri Azar KAsadizanjani NRahman FMardani Kamali HFarahmandi F(2024)Rethinking Hardware WatermarkHardware Security10.1007/978-3-031-58687-3_3(143-182)Online publication date: 3-Apr-2024
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