I am a PhD student with the Viterbi School of Engineering of the University of Southern California. My research interests include: Computer Aided Design of Digital Systems, VLSI implementation of digital systems, Low Power and Reliable Electronics, Machine Learning, Stochastic and Approximate Computing, and Implantable and Wearable Biomedical Electronics.
—In this paper, we present a new 8T design for SRAM cell that is based on traditional Si technolo... more —In this paper, we present a new 8T design for SRAM cell that is based on traditional Si technology and reduces leakage power considerably compared to a conventional design. Proposed design can be fully functional at smaller supply voltages over the conventional 6T SRAM cell. To verify the proposed design, a 32kb SRAM is designed and simulated in 90nm CMOS technology using the proposed 8T and conventional 6T SRAM cells. Operating at their V DDmin, simulations show improvement of 58% and 67% for write and read power per operation, respectively for our design. To address the challenge of half selection during write operation, a new low-power internal write-back scheme is presented. Finally, designing proposed cell using FinFET transistors shows less sensitivity to variations and also improvement of 2.08X in read SNM at VDD=1.0V over bulk-CMOS based SRAM cell.
In this paper, we present a new 8T design for static random access memory (SRAM) cell that is bas... more In this paper, we present a new 8T design for static random access memory (SRAM) cell that is based on traditional Si technology and reduces leakage power considerably compared with a conventional design. Proposed design can be fully functional at smaller supply voltages over the conventional 6T SRAM cell. To verify the proposed design, a 32 kb SRAM is designed and simulated in 90 nm CMOS technology using the proposed 8T and conventional 6T SRAM cells. Operating at their VDD (_{min }) , simulations show improvement of 58% and 67% for write and read power per operation, respectively, for our design. To address the challenge of half-selection during write operation, a new low-power internal write-back scheme is presented. Finally, designing proposed cell using fin-shaped field effect transistors shows less sensitivity to variations and also improvement of (2.08times ) in read static noise margin at ({rm VDD}=1.0) V over bulk-CMOS-based SRAM cell.
2013 21st Iranian Conference on Electrical Engineering (ICEE), 2013
ABSTRACT In this paper we present a new Static Random Access Memory (SRAM) that has 7 transistors... more ABSTRACT In this paper we present a new Static Random Access Memory (SRAM) that has 7 transistors in each cell. This idea allows for bit-interleaving that makes the SRAM more reliable against the soft errors. One of the challenges of a conventional 6 transistor (6T) SRAM cell in sub-threshold region is sizing of its access transistors. Here by separating access transistors of reading and writing, we mitigate this challenge. By using a minimum-size access transistor for reading, probability of unsuccessful read reduces. To have a more successful write operation, we make one of the inverters of the cell that is fighting with the write access transistor, weaker during write operation by floating its supply voltage and ground rails. After write operation, this inverter returns back to normal mode. Simulation results in 90 nm CMOS technology show that our design satisfies 4.5-sigma criterion for reading and writing at supply voltage of 300 mV. Compared to conventional 6T SRAM cell, our design improves read-time and write-time significantly. For example at supply voltage of 500 mV, these improvements are 137 and 83 percents, respectively. Comparing power and energy consumption for single write operation of the proposed 7T SRAM cell at supply voltage of 300mV with conventional 6T SRAM cell at 800mV (i.e. minimum achievable voltage for this SRAM cell) shows improvements of 133.4X and 266.78X, respectively.
—In this paper, we present a new 8T design for SRAM cell that is based on traditional Si technolo... more —In this paper, we present a new 8T design for SRAM cell that is based on traditional Si technology and reduces leakage power considerably compared to a conventional design. Proposed design can be fully functional at smaller supply voltages over the conventional 6T SRAM cell. To verify the proposed design, a 32kb SRAM is designed and simulated in 90nm CMOS technology using the proposed 8T and conventional 6T SRAM cells. Operating at their V DDmin, simulations show improvement of 58% and 67% for write and read power per operation, respectively for our design. To address the challenge of half selection during write operation, a new low-power internal write-back scheme is presented. Finally, designing proposed cell using FinFET transistors shows less sensitivity to variations and also improvement of 2.08X in read SNM at VDD=1.0V over bulk-CMOS based SRAM cell.
In this paper, we present a new 8T design for static random access memory (SRAM) cell that is bas... more In this paper, we present a new 8T design for static random access memory (SRAM) cell that is based on traditional Si technology and reduces leakage power considerably compared with a conventional design. Proposed design can be fully functional at smaller supply voltages over the conventional 6T SRAM cell. To verify the proposed design, a 32 kb SRAM is designed and simulated in 90 nm CMOS technology using the proposed 8T and conventional 6T SRAM cells. Operating at their VDD (_{min }) , simulations show improvement of 58% and 67% for write and read power per operation, respectively, for our design. To address the challenge of half-selection during write operation, a new low-power internal write-back scheme is presented. Finally, designing proposed cell using fin-shaped field effect transistors shows less sensitivity to variations and also improvement of (2.08times ) in read static noise margin at ({rm VDD}=1.0) V over bulk-CMOS-based SRAM cell.
2013 21st Iranian Conference on Electrical Engineering (ICEE), 2013
ABSTRACT In this paper we present a new Static Random Access Memory (SRAM) that has 7 transistors... more ABSTRACT In this paper we present a new Static Random Access Memory (SRAM) that has 7 transistors in each cell. This idea allows for bit-interleaving that makes the SRAM more reliable against the soft errors. One of the challenges of a conventional 6 transistor (6T) SRAM cell in sub-threshold region is sizing of its access transistors. Here by separating access transistors of reading and writing, we mitigate this challenge. By using a minimum-size access transistor for reading, probability of unsuccessful read reduces. To have a more successful write operation, we make one of the inverters of the cell that is fighting with the write access transistor, weaker during write operation by floating its supply voltage and ground rails. After write operation, this inverter returns back to normal mode. Simulation results in 90 nm CMOS technology show that our design satisfies 4.5-sigma criterion for reading and writing at supply voltage of 300 mV. Compared to conventional 6T SRAM cell, our design improves read-time and write-time significantly. For example at supply voltage of 500 mV, these improvements are 137 and 83 percents, respectively. Comparing power and energy consumption for single write operation of the proposed 7T SRAM cell at supply voltage of 300mV with conventional 6T SRAM cell at 800mV (i.e. minimum achievable voltage for this SRAM cell) shows improvements of 133.4X and 266.78X, respectively.
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Papers by Ghasem Pasandi