a b s t r a c t In this paper, a 7T SRAM cell with differential write and single ended read opera... more a b s t r a c t In this paper, a 7T SRAM cell with differential write and single ended read operations working in the near-threshold region is proposed. The structure is based on modifying a recently proposed 5T cell which uses high and low V TH transistors to improve the read and write stability. To enhance the read static noise margin (RSNM) while keeping the high write margin and low write time, an extra access transistor is used and the threshold voltages of the SRAM transistors are appropriately set. In addition, to maintain the low leakage power of the cell and increase the I on /I off ratio of its access transistors, a high V TH transistor is used in the pull down path of the cell. To assess the efficacy of the proposed cell, its characteristics are compared with those of 5T, 6T, 8T, and 9T SRAM cells. The characteristics are obtained from HSPICE simulations using 20 nm, 16 nm, 14 nm, 10 nm, and 7 nm FinFET technologies assuming a supply voltage of 500 mV. The results reveal ...
Proceedings of the 2018 on Great Lakes Symposium on VLSI, 2018
In this work, the application of a voltage over-scaling (VOS) technique for improving the lifetim... more In this work, the application of a voltage over-scaling (VOS) technique for improving the lifetime and reliability of coarse-grained reconfigurable architectures (GCRAs) is presented. The proposed technique, which may be applied to CGRAs used as accelerators for low-power, error-tolerant applications, reduces the (strongly voltage-dependent) wearout effects and the energy consumption of processing elements (PEs) whenever the error impact on the output quality degradation can be tolerated. This provides us with the ability to lessen the wearout and reduce energy consumption of PEs when accuracy requirement for the results is rather low. Multiple degrees of computational accuracy can be achieved by using different overscaled voltage levels for the PEs. The efficacy of the proposed technique is studied by considering the bias temperature instability. The study is performed for two error-resilient applications. The CGRAs are implemented with 15nm FinFET operating at a nominal supply vol...
In this paper, a low-power accuracy-configurable block-based Carry Look-ahead Adder (AC-CLA) is p... more In this paper, a low-power accuracy-configurable block-based Carry Look-ahead Adder (AC-CLA) is proposed. The structure employs the voltage over scaling and number of approximate blocks as the approximation knobs for improving the energy consumption as well as the reliability and lifetime of the adder. While the former may be set in the design time as well as the runtime, the latter may only be invoked in the design time. In this adder, for a given accuracy level, some of the blocks work in the approximate mode by using over-scaled voltages. The block-based structure enables applying the overscaled voltage for each block independently. The efficacy of the adder depends on the number of the approximate blocks as well as the VOS voltage levels used for these blocks. The use of lower VOS voltage levels for the blocks responsible for lower significant bits which have higher switching activities is the key for reducing the power consumption of the adder while having the error within a to...
ABSTRACT In this work, we investigate the co-dependency of die temperature and bias temperature i... more ABSTRACT In this work, we investigate the co-dependency of die temperature and bias temperature instability (BTI) and their combined effect on the lifetime of VLSI circuits. The investigation considers the impact of die temperature in increasing the effect of the BTI as well as changes in the die temperature due to the BTI-induced threshold voltage alterations. In addition, the impact of workloads on the degree of the BTI-induced degradation in VLSI circuits is studied. This impact accounts for the direct influence of the signal probability of the internal nodes under the given workload as well as its indirect influence due to power consumption and temperature changes of the circuits. The study is performed by using a simulation framework that captures dynamic changes in the operating temperature and application workload. Simultaneous consideration of the dynamic workload and operating temperature enables one to accurately predict the circuit lifetime. To assess the accuracy of the proposed approach, the estimated delay degradations caused by the Negative BTI (NBTI) for some large circuits from ISCAS'89 and ITC'99 benchmark suites when circuits are simulated under dynamic (both temperature and workload are updated periodically), semi-static (either temperature or workload is updated periodically), and static (no updating is performed) scenarios are compared. Simulation results obtained in a 45 nm CMOS technology, reveal that the predicted timing degradation in the case of the dynamic scenario is significantly different than those of the other scenarios. The differences ranged from − 135% to + 98% for the considered circuits in this work. The large differences demonstrate that for accurate estimation of the circuit lifetime under the BTI effect, the dynamic scenario should be adopted as part of the standard design flows.
2012 International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design (SMACD), 2012
Abstract In this paper, we propose a novel 8T subthreshold SRAM cell for improving the writing “0... more Abstract In this paper, we propose a novel 8T subthreshold SRAM cell for improving the writing “0” characteristics of the conventional 8T cell. In addition, a new 10T subthreshold SRAM cell based on FinFET structures which has a lower standby power is suggested. The characteristics of the proposed and conventional 8T and 10T structures in 32 nm planar bulk and FinFET technologies are compared. The results show that the 10T structures have better write characteristics thanks to the differential write and consume less static power while ...
a b s t r a c t In this paper, a 7T SRAM cell with differential write and single ended read opera... more a b s t r a c t In this paper, a 7T SRAM cell with differential write and single ended read operations working in the near-threshold region is proposed. The structure is based on modifying a recently proposed 5T cell which uses high and low V TH transistors to improve the read and write stability. To enhance the read static noise margin (RSNM) while keeping the high write margin and low write time, an extra access transistor is used and the threshold voltages of the SRAM transistors are appropriately set. In addition, to maintain the low leakage power of the cell and increase the I on /I off ratio of its access transistors, a high V TH transistor is used in the pull down path of the cell. To assess the efficacy of the proposed cell, its characteristics are compared with those of 5T, 6T, 8T, and 9T SRAM cells. The characteristics are obtained from HSPICE simulations using 20 nm, 16 nm, 14 nm, 10 nm, and 7 nm FinFET technologies assuming a supply voltage of 500 mV. The results reveal ...
Proceedings of the 2018 on Great Lakes Symposium on VLSI, 2018
In this work, the application of a voltage over-scaling (VOS) technique for improving the lifetim... more In this work, the application of a voltage over-scaling (VOS) technique for improving the lifetime and reliability of coarse-grained reconfigurable architectures (GCRAs) is presented. The proposed technique, which may be applied to CGRAs used as accelerators for low-power, error-tolerant applications, reduces the (strongly voltage-dependent) wearout effects and the energy consumption of processing elements (PEs) whenever the error impact on the output quality degradation can be tolerated. This provides us with the ability to lessen the wearout and reduce energy consumption of PEs when accuracy requirement for the results is rather low. Multiple degrees of computational accuracy can be achieved by using different overscaled voltage levels for the PEs. The efficacy of the proposed technique is studied by considering the bias temperature instability. The study is performed for two error-resilient applications. The CGRAs are implemented with 15nm FinFET operating at a nominal supply vol...
In this paper, a low-power accuracy-configurable block-based Carry Look-ahead Adder (AC-CLA) is p... more In this paper, a low-power accuracy-configurable block-based Carry Look-ahead Adder (AC-CLA) is proposed. The structure employs the voltage over scaling and number of approximate blocks as the approximation knobs for improving the energy consumption as well as the reliability and lifetime of the adder. While the former may be set in the design time as well as the runtime, the latter may only be invoked in the design time. In this adder, for a given accuracy level, some of the blocks work in the approximate mode by using over-scaled voltages. The block-based structure enables applying the overscaled voltage for each block independently. The efficacy of the adder depends on the number of the approximate blocks as well as the VOS voltage levels used for these blocks. The use of lower VOS voltage levels for the blocks responsible for lower significant bits which have higher switching activities is the key for reducing the power consumption of the adder while having the error within a to...
ABSTRACT In this work, we investigate the co-dependency of die temperature and bias temperature i... more ABSTRACT In this work, we investigate the co-dependency of die temperature and bias temperature instability (BTI) and their combined effect on the lifetime of VLSI circuits. The investigation considers the impact of die temperature in increasing the effect of the BTI as well as changes in the die temperature due to the BTI-induced threshold voltage alterations. In addition, the impact of workloads on the degree of the BTI-induced degradation in VLSI circuits is studied. This impact accounts for the direct influence of the signal probability of the internal nodes under the given workload as well as its indirect influence due to power consumption and temperature changes of the circuits. The study is performed by using a simulation framework that captures dynamic changes in the operating temperature and application workload. Simultaneous consideration of the dynamic workload and operating temperature enables one to accurately predict the circuit lifetime. To assess the accuracy of the proposed approach, the estimated delay degradations caused by the Negative BTI (NBTI) for some large circuits from ISCAS'89 and ITC'99 benchmark suites when circuits are simulated under dynamic (both temperature and workload are updated periodically), semi-static (either temperature or workload is updated periodically), and static (no updating is performed) scenarios are compared. Simulation results obtained in a 45 nm CMOS technology, reveal that the predicted timing degradation in the case of the dynamic scenario is significantly different than those of the other scenarios. The differences ranged from − 135% to + 98% for the considered circuits in this work. The large differences demonstrate that for accurate estimation of the circuit lifetime under the BTI effect, the dynamic scenario should be adopted as part of the standard design flows.
2012 International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design (SMACD), 2012
Abstract In this paper, we propose a novel 8T subthreshold SRAM cell for improving the writing “0... more Abstract In this paper, we propose a novel 8T subthreshold SRAM cell for improving the writing “0” characteristics of the conventional 8T cell. In addition, a new 10T subthreshold SRAM cell based on FinFET structures which has a lower standby power is suggested. The characteristics of the proposed and conventional 8T and 10T structures in 32 nm planar bulk and FinFET technologies are compared. The results show that the 10T structures have better write characteristics thanks to the differential write and consume less static power while ...
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Papers by Hassan Afzali Kusha