Analytical computation of electrical parameters in GAAQWT and CNTFET with identical configuration using NEGF method

International Journal of Electronics ISSN: 0020-7217 (Print) 1362-3060 (Online) Journal homepage: http://www.tandfonline.com/loi/tetn20 Analytical computation of electrical parameters in GAAQWT and CNTFET with identical configuration using NEGF method Arpan Deyasi & Angsuman Sarkar To cite this article: Arpan Deyasi & Angsuman Sarkar (2018): Analytical computation of electrical parameters in GAAQWT and CNTFET with identical configuration using NEGF method, International Journal of Electronics, DOI: 10.1080/00207217.2018.1494339 To link to this article: https://doi.org/10.1080/00207217.2018.1494339 Accepted author version posted online: 28 Jun 2018. Published online: 14 Jul 2018. Submit your article to this journal Article views: 3 View Crossmark data Full Terms & Conditions of access and use can be found at http://www.tandfonline.com/action/journalInformation?journalCode=tetn20 INTERNATIONAL JOURNAL OF ELECTRONICS https://doi.org/10.1080/00207217.2018.1494339 Analytical computation of electrical parameters in GAAQWT and CNTFET with identical configuration using NEGF method Arpan Deyasia and Angsuman Sarkarb a Department of Electronics and Communication Engineering, RCC Institute of Information Technology, Kolkata, India; bDepartment of Electronics and Communication Engineering, Kalyani Govt Engineering College, Nadia, India ABSTRACT ARTICLE HISTORY A two-dimensional quantum mechanical model is presented for calculating carrier transport in ultra-thin gate-all-around quantum wire transistor (GAAQWT) and carbon nanotube field effect transistor (CNTFET) using coupled mode space approach. Schrödinger and Poisson’s equations are self-consistently solved involving Non-Equilibrium Green’s Function (NEGF) formalism under the ballistic limit along with dissipative effects in terms of self-energy at both the source and drain ends. Effect of structural parameters on drain current, channel length modulation parameter, quantum capacitance, transconductance, subthreshold swing (SS) and drain induced barrier lowering (DIBL) are studied assuming occupancy of only a few lower sub-bands, where comparison is performed taking all other factors, biases and dimensions identical. High-k dielectric (HfO2) independently surrounding the quantum wire (GaAs) and carbon nanotube shows higher drain current and transconductance for GAAQWT but lower quantum capacitance than that obtained for CNTFET. A smaller variation of CLM for CNFET speaks in favour of it for digital quantum circuit applications, whereas GAAQWT is suitable candidate for low-power applications. Effect of structural parameters is investigated within fabrication limit to analyse the effect on electrical characteristics under lower biasing ranges. Received 23 August 2017 Accepted 24 June 2018 KEYWORDS Quantum wire transistor; gate-all-around structure; carbon nanotube FET; NEGF technique; high k-dielectric; quantum capacitance; transconductance 1. Introduction Consistent reduction of dimension of conventional transistor in nanometric regime affects the drain current due to higher gate leakage current, less control over short-channel effect, higher power dissipation and larger subthreshold swing (SS). (Taur & Ning, 1998). This raises the demand of multigate structure along with the usage of appropriate material for effective control of drain current (Clément, Han, & Larrieu, 2013; Zhang, Chen, Fang, & Jun, 2010). Owing to variable transport mechanisms, conventional scaling techniques are not sufficient for drain current control, and thus nanoscale transistor becomes a topic of research interest (Chowdhury & Chattopadhyay, 2014; Jin, Amherst, Fischetti, & Tang, 2008; Lundstrom & Ren, 2002). More precisely, nanowire field effect transistors (NWFET) emerge as a promising candidate for the next generation electronics due to its superiority in structural, electronic and transport properties to its conventional counterparts (Fitriwan, Ogawa, Souma, & Miyoshi, 2008). Numerical modelling of such nanotransistors using nanowire is reported (Luisier, Schenk, & Fichtner, 2006; Venugopal, Ren, Datta, & Lundstrom, 2002) in recent past with different geometries (Vashaee et al., 2006) and involving different methods (Fiori & Iannaccone, 2007; Marconcini, Fiori, Macucci, & Iannaccone, 2008) of calculation. CONTACT Arpan Deyasi deyasi_arpan@yahoo.co.in Institute of Information Technology 700015, INDIA © 2018 Informa UK Limited, trading as Taylor & Francis Group Department of Electronics and Communication Engineering, RCC 2 A. DEYASI AND A. SARKAR Computation of quantum transport and charge density in quantum wire transistor (QWT) in presence of external bias is performed using Non-Equilibrium Green’s Function (NEGF) technique (Guo, Wang, Polizzi, Datta, & Lundstrom, 2003; Jiang, Shao, Cai, & Zhang, 2008), as canonical theories are unable to calculate accurate carrier transport. A few results have already been reported in recent past regarding simulation of quantum devices (Rajabi, Shahhoseini, & Faez, 2012; Sabry, Abdolkader, & Farouk, 2011) using NEGF method. Conventional parabolic dispersion relation is considered while making the computation. In nanoscale transistor, mobile charges are quantum confined within the channel, and hence, computation is carried out by expanding the characteristic modes of 2D Hamiltonian in the confined direction. This is nomenclature as mode space approach, which has been already applied to double gate (DG) metal oxide semiconductor field effect transistor (MOSFET) (Venugopal et al., 2002) within NEGF framework. In this approach, both Poisson’s equation and Schrödinger equations are self-consistently solved to obtain electric potential and eigenfunction (Datta, 2000). After calculating charge density by solving coupled transport equations using NEGF method, potential is re-evaluated until it converges. After convergence, drain current is calculated. In the last few years, there is a tremendous growth in the field of material science precisely in the field of optoelectronic sensor (Shinde & Rajpure, 2012; Shinde, Shinde, Bhosale, & Rajpure, 2011; Shinde et al., 2008), where photocurrent measurement along with reflectance (Shinde, Bhosale, & Rajpure, 2012; Shinde & Rajpure, 2011) plays the crucial role in determining efficiency of the device. Fabricated results show that magnitude of device current can be altered by varying thickness of the different material layers (Shinde et al., 2012; Shinde & Rajpure, 2012; Shinde et al., 2008), and this concept paved the way of designing nanoscale devices where dimension of insulating layer thickness or channel diameter exhibit similar effect, as shown in this article. Beyond 22 nm, scaling of Si-based device causes a lot of problems due to SCE, where one potential solution already emerges out as to use of strained Si or other suitable semiconductors having lower effective mass, i.e. higher carrier velocity as the material for channel (Huang et al., 2009). Another possible solution is to replace the conventional SiO2 layer by high-k dielectric, which enhances the possibility of fabricating ultra-thin device. In this article, authors considered the combination of Si (as substrate) and HfO2 (as dielectric) as one of the right substitute pair of conventional technology, and drain current as a function of different applied biases is computed. Thickness of the insulating layer and channel dimension are independently varied for analytical purpose. For carbon nanotube field effect transistor (CNTFET), drain current as a function of contact potential along with surface potential are already measured experimentally (Mizutani, Nosho, & Ohno, 2008). Compatible with 45 nm technology, logic level developments using CNTFET is analysed in recent past (Tan, Lentaris, & Amaratunga, 2012). NEGF method is also used to calculate the properties of T-CNTFET (Karimi & Pourasad, 2016) based on p-i-n structure. But all the results reported so far are for higher channel length, and also vis-a-vis analysis with gate-all-around quantum wire transistor (GAAQWT) structure is not reported as far the knowledge of the authors. Also for cylindrical structural configuration, analysis of GAAQWT is yet to be published. Novelty of the work lies in the fact of choosing suitability of these identical devices [identical in terms of dimensions and subject to applied biases] for low power applications, and also in nano-digital circuits, which is established from simulated characteristics. The applicability of each device is derived from the simulated characteristics profile. Here lies the importance of the present work as illustrated in the following sections. In Section 2, mathematical modelling is presented for computation of electrical parameters after obtaining selfconsistency. Results obtained from simulation are discussed in Section 3. Finally, in Section 4, conclusion is given by highlighting the pros and cons of the devices from the computed results. 2. Mathematical formulation Let us consider the structure of quantum wire MOSFET shown in Figure 1, where carrier transport is considered along z-axis. To compute the drain current (Datta., 1997; Wang et al., 2016) in QWT, INTERNATIONAL JOURNAL OF ELECTRONICS Sou rce Dielect ric Dielec tric Gate 3 Dr ain Figure 1. Schematic diagram of a cylindrical quantum wire/carbon nanotube transistor. Different layers are mentioned inside the figure. transmission coefficient between source and drain junctions needs to be evaluated. The problem can be solved using coupled mode space approach, uncoupled mode space approach and fast uncoupled mode space approach (Venugopal et al., 2002), (Wang et al., 2014), (Je, Han, Kim, & Shin, 2000; Ren et al., 2000); but the authors choose the first one because it reduces the size of the problem compared to a full two-dimensional spatial discretisation, depending on the boundary conditions. This, in turn, depends on the dissipative effects at the source and drain ends, which can be calculated, from spectral functions at those nodes (Lenzi et al., 2008; Lundstorm, 2000; Michetti, Mugnaini, & Iannaccone., 2009). Diagonal elements of spectral functions give local density of states, which are important for achieving self-consistent potential function by estimating the charge density. In order to accomplish self-consistency, at first Hamiltonian function from the Schrödinger equation needs to be evaluated for arbitrary potential function. That is substituted into Poisson’s equation and the iterative process will continue until the convergence is reached. Next the modelling is described in four different sub-sections for ease of understanding. A. Calculation of drain current Let us consider the schematic structure of GAAQWT/CNTFET shown in Figure 1, where carrier transport is considered along z-axis. Drain current for transport of electrons from source to drain (Wang et al., 2014) may be written in the following form: IDS q ¼ πh 1 ð TS D ðEÞ½f ðμS ; EÞ f ðμD ; EފdE (1) 1 where TS-D(E) is the transmission coefficient due to carrier transport form source to drain, µS and µD are the Fermi levels at source and drain ends, and f gives the Fermi function at the respective terminals. Transmission coefficient can be obtained using the following expression (Ren et al., 2000): TS D ðEÞ ¼ trace½ΓS ðEÞGðEÞΓD ðEÞG0 ðEފ (2) where G(E) denotes the retarded Green’s function (Wang et al., 2014), (Ren et al., 2000), G′(E) denotes its complex conjugate, ΓS(E) and ΓD(E) denote the dissipative effects due to the transport of carriers between device and contact, given by: X X 0 ΓS ðEÞ ¼ jð ðEÞ ðEÞÞ (3:1) ΓD ðEÞ ¼ jð S S X X D where P S E and P D ðEÞ 0 ðEÞÞ (3:2) D E are the self-energies at the source and drain ends (Datta, 1997), defined by: 4 A. DEYASI AND A. SARKAR X E¼ X ½p; qŠ ¼ S S X D E¼  2 h amn ðzÞjx¼0 expðjkm;1 aÞδp;ðm 2a2  X ½p; qŠ ¼ D   2 h amn ðzÞjx¼ðR 2a2 1Þa expðjkm;R aÞδp;mR δq;mR Retarded Green’s function is given by (Wang et al., 2014) : X X ðEފ ðEÞ GðEÞ ¼ ½EI H S where H is the Hamiltonian which can be 2 3 2 ϕ1 ðzÞ h11 h12 6 ϕ2 ðzÞ 7 6 h21 h22 6 7 6 7 6 H6 ::: 6 ::: 7 ¼ 6 ::: 4 ::: 5 4 ::: ::: ϕM ðzÞ hM1 hM2 1ÞRþ1 δq;ðm 1ÞRþ1 1 (4) (5) (6) D obtained from Schrödinger equation: 2 3 3 32 ϕ1 ðzÞ ϕ1 ðzÞ ::: ::: h1M 6 ϕ2 ðzÞ 7 6 7 ::: ::: h2M 7 6 7 76 ϕ2 ðzÞ 7 7 6 7 7 ::: ::: ::: 76 ::: 7 ¼ E6 6 ::: 7 4 ::: 5 ::: ::: ::: 54 ::: 5 ϕM ðzÞ ϕM ðzÞ ::: ::: hMM (7) The dissipative effects are used to define spectral density functions AS(E) and AD(E) at source and drain ends, respectively. AS ðEÞ ¼ GðEÞΓS ðEÞG0 ðEÞ (8:1) AD ðEÞ ¼ GðEÞΓD ðEÞG0 ðEÞ (8:2) Spectral density function adds the effect of electron exchange rates between the contacts and the active region of device. The potential function (V) associated with Schrödinger equation (Equation (7)) can be computed from Poisson’s equation if electron density in the channel is known. Ñ2 Vðr; θ; zÞ ¼ n3D;m =ε (9) where n3D ¼ n1D;m ðzÞjm ðr; θ : zÞj2 (10) ε is the permittivity of the medium, n1D is the 1D electron density for mode ‘m’, which can be obtained from local density of states function as (Ren et al., 2000): n1D;m ¼ 1 ð 1   DS;m f ðμs ; EÞ þ DD;m f ðμD ; EÞ dE (11) where, DS,m and DD,m are the local density of states functions. In ballistic limit, both the source and drain injected levels are mutually independent. Local density of states function can be obtained from the diagonal elements of spectral density function, which is given in Equation (8). After calculating the potential function by substituting 3D electron density in Poisson’s equation, the modified potential is again used to re-evaluate the coupled mode-space Hamiltonian obtained from Schrödinger equation. The sequence of steps is shown through a flow-chart in Figure 2. For the potential function, each time retarded Green’s function, dissipative effects and spectral density functions are computed. When the potential function obtained from Schrödinger’s equation becomes numerically equal to the potential substituted after solving Poisson’s equation, i. e. once self-consistency is achieved, drain current is computed. When the maximum energy of sub-band becomes larger than both of the Fermi levels, then Equation (1) can be calculated as: INTERNATIONAL JOURNAL OF ELECTRONICS 5 Figure 2. Flowchart for achieving self-consistent potential function. IDS ¼ G0 kB T X 1 þ exp½ðμS gi ln q i 1 þ exp½ðμD Ei0 Þ=kB TŠ Ei0 Þ=kB TŠ (12) where Ei0 represents the energy of ith sub-band, gi is the spin degeneracy. When the device is in weak inversion region, then Fermi statistics can be replaced by Boltzmann statistics. Then expression of current density becomes:        kB T μ μ0 X E00 Ei0 E00 Ei0 qVD exp (13) IDS ¼ G0 gi exp exp S kB T kB T kB T q i where E00 is the value of μD when μS is measured from it with knowledge on VGS, VDS, VT and band structure. B. Subthreshold swing and quantum capacitance Total charge density in the device can be expressed as 6 A. DEYASI AND A. SARKAR Figure 3. Comparative analysis of the theoretical findings with earlier available results (Lenzi et al., 2008) for static output characteristics with two different values of VGS for ballistic DGMOSFET; lines indicate simulated results whereas symbol signifies earlier available data. Q¼ CG VG þ CP VP (14) where CG is channel-gate capacitance and CP is channel-substrate capacitance, VG and VP are the bias voltages respectively applied at the gate and substrate. Measure of the potentials in terms of barrier heights gives: ðVG VT Þ α μS μ0 q ¼ jQj CG (15) Equation (15) suggests that with increase of gate bias, potential applied to the gate insulator is reduced by an equal amount to the increase in chemical potential because of the enhancement of carrier flow. µ0 is the potential measured at the bottom of the sub-band in channel region, and α is  the parameter given byα ¼ 1 þ CCGP . Differentiating Equation (15) w.r.t VG assuming the total charge density as negligible for VG < VT, we can write d ðμ dVG S μ0 Þ ¼ q α (16) Substituting the value of α in Equation (16), one can obtain: d ðμ dVG S μ0 Þ ¼ CG q CG þ CP Again, differentiating Equation (12) after taking logarithm, we can write (Je et al., 2000)     dðlogðID ÞÞ 1 1 dðμs μ0 Þ 1 ¼ S¼ dVG kB T lnð10Þ dV G Substituting Equation (17) in Equation (18), SS may be written as (17) (18) INTERNATIONAL JOURNAL OF ELECTRONICS  1 CG q S¼ kB T lnð10Þ CG þ CP  7 1 (19) From Equation (19), it is found that short channel effect degrades the SS as the first order differential is negative. This can be improved by covering the total channel by gate, i.e. by using GAA structure which effectively enhances the effect of gate bias. Quantum capacitance is originated in nanowire MOSFET due to small density of states for channel carriers. It is defined as X CQ ¼ q2 gi ½DS ðμS μ0 Þ þ DD ðμD μ0 ފ (20) i Assuming μ = μD = μS, one can write CQ ¼ q2 X gi ½DS ðμ μ0 Þ þ DD ðμ μ0 ފ (21) i Charge inside the quantum wire can be computed considering the carrier distribution within the sub-band including spin degeneracy factor (Ren et al., 2000). 2 3 kimin 1 ð ð X q dk dk 6 7   (22) jQj ¼ gi 4 þ 5 Ei ðkÞ μS Ei ðkÞ μD π i 1 þ exp 1 þ exp k T k T 1 B B k imin Assuming absence of parasitic capacitance, Equation (21) is modified as: 21 3 ð qX 4 dk 5  gi jQj ¼ π i 1 þ exp Ei ðkÞ μ which may be put in the following form 21 ð qX 4 jQj ¼ gi ½DS ðμ μ0 Þ þ DD ðμ π i μ0 ފf ðE μ0 ; μ 1 as the Fermi-Dirac distribution function is given by   E fFD ðE μÞ ¼ 1 þ exp Differentiation of Equation (23) gives 21 ð X djQj gi 4 ½DS ðμ ¼q dVG i kT μ0 Þ þ DD ðμ 1 (23) kB T 1  μ 3 μ0 ÞdE 5 (23) 1 3 dðμ μ0 Þ5 μ0 ފ dVG (24) (25) Again, differentiation of Equation (15) provides d ðμ dVG S  μ0 Þ ¼ q 1 1 djQj CG dVG  Substituting Equation (26) in Equation (25), one can write 21 3   ð X djQj 1 d Q j j 5 gi 4 ½DS ðμ μ0 Þ þ DD ðμ μ0 ފ 1 þ ¼ q2 C dVG dV G G i 1 (26) (27) 8 A. DEYASI AND A. SARKAR Substituting Equation (21) in Equation (27), we can obtain   d j Qj 1 d j Qj ¼ CQ 1 CG dVG dVG Rearranging Equation (28), it may be written in the following form   d j Qj 1 djQj CQ ¼ = 1 CG dVG dVG (28) (29) Equation (29) suggests that quantum capacitance depends on the effective potential at any of the contact terminal measured w.r.t sub-band bottom potential at channel. 3. Results and discussions Using Equation (1), first drain current is calculated for a ballistic MOSFET with double-gate configuration, and simulated findings are verified with the already available results (Rahman, Guo, Datta, & Lundstorm, 2003). For computation purpose, doping concentration is considered as 1026 m−3. The simulation is carried out for channel length within 1–5 nm, and same range for channel thickness also. These magnitudes are also taken for CNTFET also for comparative study. For CNTFET, we consider armchair nanotube. From the comparative analysis, as shown in Figure 3, it is seen that the results are in close agreement, more precisely in the low bias region. Thus the theoretical model presented in the Section 2 of the article is justified, and the calculation can safely be used for our choice of material parameters. Verification has been carried out for two different gate biases, VGS = 0.8 V and VGS = 1 V. In Figure 4(a), output characteristics is computed and plotted for different gate voltages with SiHfO2 combination, and results are compared with that obtained for CNTFET. One point may be noted in this context that the growth of HfO2 is considered over a very thin layer of SiO2, as per the fabrication procedure. It may be observed from the plot that drain current for CNTFET is higher than that obtained for GAAQWT irrespective of VGS when the applied horizontal bias is closed to pinch-off, and the difference is more distinguishable when VGS is high. This is due to the additional confinement imposed in DG MOSFET for multiple gates, which is absent for CNTFET. Though computation shows the magnitude of drain current is very high (~ 80 µA) but some other tides exhibit the same of the order of 30–40 µA (Rahman et al., 2003). The difference arises due to the fact that the present analysis is carried out by considering the realistic sub-band structure under ballistic limit along with quantum capacitance formation, whereas the works of Natori (2008) considered only first sub-band is occupied. In Figure 4(b), the plot is shown for different thicknesses of insulating layer (t). It shows that with increase in t, drain current reduces. It is also seen that pinch-off condition appears at lower VDS for higher thickness. In Figure 4(c), plot is shown for different channel widths (d). It is seen that current increases with increase of ‘d’ because of increased available space for carrier transport. This can be explained in detailed as: in the CNTFET, scattering inside the channel is comparatively less if other structural conditions are kept constant, and thus the velocity of mobile charge for the chosen range of applied biases is more for carbon based devices. Thus the opposing resistance is lower in CNTFET, which results in higher drain current. The significant observation from the result is that due to the movement of pinch-off point towards the source after attaining the saturation condition, current slowly increases with VDS. Therefore, the chosen material combination provides much higher drain current. The important findings from these two results are that the difference of drain current between the devices under consideration increases for higher thickness and lower channel diameter. Channel length modulation parameter (λ) is computed and plotted in Figure 5 as a function of different structural parameters. By increasing the thickness of insulating layer, it is seen that channel length modulation parameter monotonically decreases. Result is plotted for both the devices, as depicted in Figure 5(a). Interestingly, it is seen that the rate of change of the CLM INTERNATIONAL JOURNAL OF ELECTRONICS 9 Figure 4. Comparative analysis of output characteristics between GAAFET and CNTFET with identical structural parameters and applied bias. Static characteristics of GAAQWT and CNTFET for (b) different insulating layer thicknesses keeping VGS = 1 V, (c) different channel widths keeping VGS = 1 V. 10 A. DEYASI AND A. SARKAR Figure 5. Channel length modulation parameter of GAAQWT and CNTFET for (a) different insulating layer thicknesses keeping VGS = 1 V, (b) different channel widths keeping VGS = 1 V. parameter is higher in NWFET than that obtained for CNTFET, which speaks the fact that rate of change of saturation current for CNTFET is comparatively low than that for NWFET, therefore ensures better candidature for CNTFET in digital applications. Henceforth, it may be concluded as the material of the channel makes a critical consideration regarding application of the device in digital circuit as higher change in drain current indicates non-stable higher logic region. Hence, layer thickness should be critically monitored. In Figure 5(a), it is also observed that small change of insulating layer thickness makes a rapid fluctuation in current. This is due to decrease of drain induced barrier lowering (DIBL) after pinch-off condition. It is also noted in this context that higher VDS provides higher λ, so bias conditions at operating point plays a crucial role in this regard. In Figure 5(b), it is observed that as channel width increases, λ increases; but the rate of increment is negligibly small for CNTFET. It may also be concluded that for NWFET; with larger channel width, slope of the current-voltage characteristics curve reduces. The computation is carried out for VGS = 1 V. This is due to the fact that with increase of channel diameter, DIBL effect becomes more significant which speaks about lowering of resistance. Thus, current increases with much higher rate than normally expected. Therefore, C.L.M parameter increases. This result is also favourable for CNTFET in quantum circuits. Simulation also ensures that slope of ID-VDS characteristics can be tuned by controlling the channel width or by insulating layer thickness, which plays vital role in designing analogue very-large-scale integrator (VLSI) circuits, precisely current mirror circuit using QWT. Transfer characteristics are plotted in Figure 6 keeping drain-to-source voltage 1 V. From the plot, it is shown that with increasing dielectric layer thickness, drain current reduces (Figure 6(a)) whereas it increases with enhancing channel dimension. However, current for CNTFET is higher than that calculated for GAAQWT at any particular gate bias, though the difference is insignificant at lower gate bias. From Figure 6(b), it is observed that higher channel diameter increases the drain current, supporting the earlier obtained simulated findings. For Si QWT embedded with SiO2, drain current attains 30–35 µA with VGS = 1 V (Rahman et al., 2003), whereas the proposed combination gives double drain current which also ensures higher transconductance. While calculating drain current, we have considered that carrier concentration is considered as function of density of states, band gap and Fermi energy. Again, DOS depends on the chiral indices of the nanotube. Hence, the total computation of drain current is critically dependent on the geometry of the nanotube. The total analysis is made for zigzag nanotube as its fabrication is more reported in referred literatures than the armchair one. Corresponding study of mobile charge INTERNATIONAL JOURNAL OF ELECTRONICS 11 Figure 6. Transfer characteristics of GAAQWT and CNTFET for (a) different insulating layer thickness, (b) different channel dimension. variation with different applied biases are individually studied. With increase of gate voltage, the mobile charge increases, whereas with drain voltage, mobile charge deceases. Transconductance, calculated from the knowledge of transfer characteristics, is plotted as a function of gate voltage in Figure 7 for constant drain voltage for both the devices. In Figure 7(a), plot is shown for different values of insulating layer thickness. With increase in bias, transconductance (gm) increases linearly, and then becomes almost constant. This is because current follows in a similar fashion with increasing VDS. Again, at a particular VGS, as insulator thickness increases, inversion layer charge density decreases to reduce the drain current. This, in turn, reduces gm. In Figure 7(b), plot is shown for different values of channel width. For lower thickness, a particular value of gate voltage is obtained after which transconductance begins to saturate. It is seen that as channel width increases, gm increases. This is due to increase in current with increase in width of the channel. So, a proper choice of channel width and dielectric thickness along with VGS and VDS, required transconductance can be achieved for designing QWT-based circuit. Using Equation (29), variation of quantum capacitance (CQ) with vertical bias is graphically represented in Figure 8. It may be noted that magnitude of capacitance is in ~ pF range and Figure 7. Transconductance of GAAQWT and CNTFET for (a) different insulating layer thickness, (b) different channel dimension. 12 A. DEYASI AND A. SARKAR Figure 8. Quantum capacitance of GAAQWT and CNTFET for (a) different insulating layer thickness, (b) different channel dimension. even may be less than that depending on choice of applied bias and structural parameters. It is seen for Figure 8(a) that with increase of VGS, capacitance at first increases, then starts decreasing. The peak value of capacitance signifies that for that particular composition of the electrical and structural parameters, the device can store the maximum permissible charge. Storing capability depends on the dimension of the channel as well as applied bias. The rate of decrement reduces with higher value of VGS. If channel width is varied keeping insulator thickness constant, then similar variation is observed, as shown in Figure 8(b). However, the effect of channel width is almost negligible for higher VGS, where it is quite distinguishable in the overall range for different thickness of insulating layers. One key observation form the result is that magnitude of quantum capacitance is higher for NWFET than that computed for CNTFET, which ensures better switching action for the former device. Again the peak value of capacitance is different w.r.t VGS for NWFET when dielectric thickness is varied, whereas it remains same for CNTFET. Figure 9(a) shows the variation of SS with channel width for different channel diameters for GAAQWT. By increasing channel width, SS decreases. For a given width of the channel, SS increases with increasing insulator thickness. This is due to the fact that higher channel width enhances drain current which makes on-current to off-current ratio larger. This reduces SS. With increasing insulator thickness, drain current reduces due to increased potential barrier, which makes the ratio lower. For Si-SiO2 composition, reported values of SS lies in the region between 90 and Figure 9. Subthreshold swing with gate voltage for (a) different insulating layer thicknesses keeping VGS = 1 V, (b) different channel widths keeping VGS = 1 V. INTERNATIONAL JOURNAL OF ELECTRONICS 13 Figure 10. Drain induced barrier lowering with gate voltage for (a) different insulating layer thicknesses keeping VGS = 1 V, (b) different channel widths keeping VGS = 1 V. 110 mV/decade (Rahman et al., 2003), while for GaAs-HfO2 combination (present work), value of SS lies between 140 and 150 mV/V depending on the channel thickness. Hence, use of HfO2 slightly enhances the swing, but it can be tailored by decreasing the thickness of insulating region. In Figure 9(b), SS is plotted with insulating layer thickness for different channel widths. From the plot, it is seen that SS increases almost linearly with increasing insulator thickness. With increasing channel width, SS decreases due to increase of drain current. Thus, structural parameters can tune the SS for QWT. Variation of DIBL with channel width is computed and plotted in Figure 10(a). From the plot, it is observed that with increase of width, DIBL decreases. The rate of fall decreases for higher width. With increasing thickness, DIBL increases, as shown in Figure 8(b). It is already reported that for SiSiO2 transistor, DIBL varies between 120 and 250 mV/V (Rahman et al., 2003). In the present work, the magnitude is very low (~ 51 mV/V) for GaAs-HfO2 combination. Hence, use of HfO2 as high-k dielectric predicts lower DIBL compared to the earlier obtained result (Rahman et al., 2003). This signifies higher on-current to off-current ratio. Thus, Si-HfO2 device can be considered as a better candidate than Si-SiO2 device for implementing digital VLSI circuits. Though there is not direct relation between the structural parameters and the applied voltages, but it may be found with an insight view that at lower biasing ranges, dimensional effects are studied in order to observe the confinement effect. At higher applied bias, electric field in the nanodevices will become very high so that the device physically may not sustain that condition. Also due to nanometric dimensions, quantum confinement effect is severe, and small change of voltage will cause a great change in current and transconductance. This is the reason behind choice of voltage range. Result shown in tabular form supports this statement. 4. Conclusion A comparative analysis of the proposed Si-HfO2 GAAQWT with CNTFET suggests that higher drain current can be achievable for CNTFET when external operating conditions and structural parameters remain identical. Also channel length modulation parameter for CNTFET remains almost unaffected with variation in device dimension. Transconductance, when compared between the devices, is also found higher for CNTFET. Comparative study as seen from Table I reveals that much higher drain current, compatible SS and smaller DIBL is obtained for the present material configuration with higher transconductance and quantum capacitance, which speaks in favour of the simulated data with the material system. This comparison is made w.r.t Si-SiO2 material system. Combining these three important findings, it may be considered that for low power application, 14 Ref (Manisha & Kumar., 2016) Ref (Mozahid & Ali, 2015) Ref (Farhana, Alam, & Khan., 2014) Ref (Javey et al., 2005) Ref (Aravind, Shravan, Shrijan, Sanjeev, & Sundari, 2016) Ref (Farhana, Alam, & Khan, 2015) Present material composition Saturated drain current 35 µA at VGS = 1 V ––––– 720 µA at VGS = 1 V ––––– 18 µA at VGS = 0.8 V 66 µA at VGS = 1 V 81.4 µA [at VGS = 1 V] 58.2 µA [at VGS = 0.8 V] Subthreshold swing ––––– DIBL ––––- Quantum capacitance ––––– –––––– –––––- 36 mV/decade [14 nm length & 28 nm width] 113.67 mV/decade [45 nm length & 125 nm width] ––––– 54.73 mV/V [14 nm length & 28 nm width] 3 pF at VGS = 0.5 V 2.2 pF at VGS = 0.75 V 1 pF at VGS = 1 V ––––– 83.89 mV/V [45 nm length & 125 nm width] ––––– –––––- ––––– 150 mV/decade at 5 nm channel length 150.4 mV/decade [at 5 nm channel length] 275 mV/V at 5 nm channel length 51.6 mV/V [at 5 nm channel length] –––––2.54 pF at VGS = 0.5 V 2.02 pF at VGS = 0.75 V 1.98 pF at VGS = 1 V Transconductance [normalised] gm/ID –––––– 19 V−1 [at VGS = 0.1 V] 15 V−1 [at VGS = 0.5 V] 2.5 V−1 [at VGS = 1 V] 34.01 V−1 [at VGS = 0.1 V] 6.261 V−1 [at VGS = 0.5 V] 1.621 V−1 [at VGS = 1 V] A. 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