zyxwvutsrqpo zyxw zyx Summary: This Letter has described a low voltage bipolar logic form suitable for use in communications applications. The 64/65 dual modulus divider was operational to over 800MHz, with some devices just reaching 1GHz. A divider connected D-type, running at twice the nominal current, achieved 2GHz operation. The bipolar-SO1 process, which has a very low collector-to-substrateparasitic capacitance, gave an approximately 2.1 advantage in the power-delay product over conventional bipolar processing. Acknowledgments: The author acknowledges the help and support of GEC Plessey Semiconductors, who also carried out the processing. This project is funded by the UK Department of Trade and Industry @TI) as Project No: IED2/470/30/05. The project partners are:- GEC Plessey Semiconductors, Defence Research Agency Electronics Division, Phoenix VLSI Consultants Ltd., Cambridge Consultants Ltd., BCO Technologies Ltd., and The Queen’s University of Belfast. Improved circuit designs: Simple feed-back transistor: The first circuit uses the output signal to assist the discharge of node x and hence also of any other nodes in the connected chain. The circuit is shown in Fig. 3 with an extra transistor connecting nodes x and w, and driven by out. As soon as x crosses the switching voltage of the output inverter, the rising output switches on the extra transistor to discharge x. In practical terms, therefore, the maximum number of transistors on a discharge path becomes three, rather than the full pass-transistor chain. As a consequence, the delay becomes linearly dependent on the number of bits. zyxwvu zyxw zyxwvutsrqpon zyxwvutsrqp zyxwvutsrq zyxwv ‘7 0 IEE 1998 Electronics Letters Online No: 19980112 P.H. Saul (Suul Research, 51 Windsor Northumptonshire “12 6JB, United Kingdom) 5 December 1997 Close, Towcester, E-mail: petersaul@compuserve.com I? References out -1I ABIDI, A.: ‘The future of CMOS wireless transceivers’. ISSCC 97 Dig. Tech. Papers, 1997, pp. 118-119 RUDELL, J., ou, J.-J., CHO, T., CHIEN, G., BRIANTI, F., WELDON, J., and GRAY, P.: ‘A I.9GHz wide-band IF double conversion CMOS integrated receiver for cordless telephone’. ISSCC 97 Dig. Tech. Papers, 1997, pp. 304-305 HEINEN, S., HADJIZADA, K., MATTER, U,, GEPPERT, W., THOMASL, V., WEBERL, s., BEYERL, s., FENKL, J., and MATSCHKEL, E.: ‘A 2.7V 2.5GHz bipolar chipset for digital wireless communication’. ISSCC 97 Dig. Tech. Papers, 1997, pp. 307-307 SAUL, P.H., and GOODY, S.B.: ‘Bipolar-SO1 active filters for UHF radio communications’. BCTM Proc., September 1996, Minneapolis, Minnesota, pp. 161-164 SLOB, A.: ‘Fast logic circuits with low energy consumption’, Philips Tech. Rev., 1968, 29, (12), pp. 363-361 Circuit improvements for high-speed domino logic: for the Manchester carry chain * @ Fig. 1 I bit circuit for Manchester carry chain CI Fig. 2 Ten bit Manchester curry chain There are three disadvantages to this circuit. The feed-back transistor only helps the discharge of x once it has passed the inverter switching voltage. This is also delayed by the capacitance of out, thus making the speed dependent on such factors as external routing and fanout. Finally, the discharge path must pass through the clocked pull-down transistor, as well as the feedback transistor, to avoid short circuits during the precharge phase without short circuits. G.M. Blair 1 c: 4 Gypy Cicuit techniques are introduced to reduce the delay of passtransistor chains within the domino-logic implementation of a Manchester carry chain: the quadraticdependency on the number of bits is made linear without increasing transistor sizes. c‘k Introduction: Multiple-output domino logic can be used for high- I p -L speed adder design, especially in the implementation of the Manchester carry-chain [I]. The basic architecture of a single bit is shown in Fig. 1 and a ten bit carry chain is shown in Fig. 2. Propagate (P) and generate (G) signals are generated externally. During precharge (when clk is low) the nodes x are charged to V D D ; during evaluation (when clk is high) an x node may be discharged either by the corresponding G input or by the P input if the x node on the less-significant bit is itself (being) discharged. The worst-case delay occurs when all nodes x are discharged by the chain of pass-transistors with the P signals all high and the G signals all low. If the transistor sizes are the same along the discharge path, the distributed RC results in a delay which is quadratic in the number of bits. Rabaey has shown [2] that increasing the pass-transistor sizes by a constant factor k along the chain will reduce this delay and (for large k) can lead to a nearly linear dependency, but with a severe area penalty. This Letter considers two circuit techniques to achieve a low, linearly dependent delay without increasing transistor sizes. type transistor, and node z is discharged turning off the feedback transistor. When clk rises, z is isolated but remains low unless x begins to fall. If x partially discharges, it switches on the extra p type transistor, which allows charge to flow onto z and, in turn, switches on the feedback transistor to accelerate the discharge. ELECTRONICS LETTERS No. 3 wL zyxwv m Fig. 3 Improvement with simple feedback transistor Ampl@er circuit: The second circuit is borrowed from ROM sense amplifier techniques [3] and is shown in Fig. 4 (without the output inverter). When clk is low, x is precharged turning off the extra p - zyxwvutsr 5th February 1998 Vol. 34 2 47 zyxw zyxwvutsr zyxwvuts zyxwvut This circuit has two advantages in that the feed-back transistor: is connected directly to ground (making a single transistor path to discharge x) (ii) assists the discharge of node x as soon as it drops by V,, (rather than to the inverter switching threshold) (i) 7- context of the long delay-paths associated with the Manchester carry-chain. Without transistor sue optimisation, these techniques lead to a 40% reduction in the delay on a 10 bit carry-chain. Furthermore, the delay dependency is linear with the number of bits, rather than being quadratic. zyxw IO November 1997 0 IEE 1998 Electronics Letters Online No: 19980236 G.M. Blair (The Department of Electrical Engineering, The University of Edinburgh, The King’s Buildings, Edinburgh EH9 3JL, Scotland, United Kingdom) References and FISHER, A.L.: ‘Ultrafast compact 32-bit CMOS adders in multiple-output domino logic’, IEEE J. Solid-State Circuits, 1989, 24, (2), pp. 358-369 2 RABAEY, J.M.: ‘Digital integrated circuits: a design perspective’ (Ptentice Hall, 1996), ISBN 0-13-394271-6 3 KOHDA, S., MASUDA, K., MATSUZAWA, I<., and KITANO, Y . : ‘A giant chip multigate transistor ROM circuit design’, IEEE J. Solid-State Circuits, 1986, 21, (5), pp. 713-719 1 HWANG, I.s., zyxwvutsrqpo * /40114/ Fig. 4 Improvement with sense amplifier B.Y. Kim and Y.S. Chang ................. time,ns Introduction: The need for stable, high speed disk storage has led to the increased use of fault-tolerant disk arrays or RAID [l, 2, 41. This Letter focuses on the performance enhancement of the RAID 5 controller. It has a form of disk cache, constructed with non-volatile RAM, to reduce the IO service time by using a suitable destage algorithm that decides when and which wnte request in the write cache is serviced [3, 71. Recent researches on improving RAID 5 performance have focused on improving the destage algorithm of the RAID 5 controller. However, they largely ignore the fact that the performance of the disk array is affected not only by the service time at each disk, but also by the load distribution among the disks. This is due to the fact that a single large host request must usually be serviced by a striped request to multiple disks in the array. Therefore, we must consider not only the performance of each disk, but also the load distribution among the disks. The destage algorithms of the existing RAID 5 controllers, however, do not take into consideration the overall performance of all the disks in the array, but destage write requests for optimal performance at each individual disk, may lead to the overload of a few disks. This Letter suggests a new RAID 5 controller using the new load-balanced destage (LBD) algorithm that destages write requests based on the load distribution among the disks in the array. zyxwvutsrq @GI Fig. 5 HSPICE simulation results using Figs. I , 3 and 4 Ten stage Manchester carry chain In the existing RAID 5 controllers, destage algorithms do not take into consideration the overall performance of the disk array but rather the optimal performance at each individual disk, and ths may eventually decrease the RAID performance. Ths authors suggest a new RAID 5 controller using a load-balanced destage algorithm adopted at the disk array level, and show that the new controller has a hgher performance than existing controllers. There are two disadvantages, however: the inverse clk signal must be generated and distributed, and node z is isolated when the clk is low and must be guarded (by careful layout) against cross-coupling, since even small changes in its voltage may lead to a false discharge of node x. zyxwvutsrqp Comparison: Simulation results are shown in Fig. 5 using HSPICE with Alcatel Mietec, 0 . 7 CMOS, ~ level 3 parameters and all transistors of size 1I-Lm/0.7p. In each case, the elk signal is raised (crossing the midpoint) at 1 ns and the display shows the discharge of the 10 nodes x in Fig. 2 and the last out signal to rise (with a capacitive load of three transistor gates). The top display shows the delays associated with the original design, demonstrating the quadratic dependency. The middle display shows the results for the single feedback transistor, and the bottom display is for the amplifier circuit. The results for the two new circuits clearly show the reduction in the delay and its linear dependency. To show the effect of different circuit techniques alone, the simulations were performed without transistor-size optimisation, using the same minimum transistor size throughout. However, in the final circuit, an increase in width to 3 p of the feedback and P-input transistors results in a further 20% reduction in delay as measured by the mid-point rise of the final out signal. Conclusion: We have shown two simple and area-efficient circuit techniques to reduce the delay of domino-logic, particularly in the 248 LBD Algorithm: The service of the host request in the disk cache is more complicated in RAID 5 than just a single disk. When a host read request misses in the cache, the controller divides the request into striping units and generates multiple striped read requests. These striped requests are then serviced by individual disks. Because each disk services requests using an individual IO queue, the service time of each striped request is different. The service time of each striped read request T r e a d ( i ) at each disk i can be calculated as follows, T-read(i) = T..queuing(i) + T-seek(i) + T-transfer(i) where i is the disk index, 0 < i < k , and k is the size of the disk array. ELECTRONICS LETTERS 5th February 1998 Vol. 34 No. 3