A new single photon avalanche diode in CMOS high-voltage technology

3B1.3 A NEW SINGLE PHOTON AVALANCHE DIODE IN CMOS HIGH-VOLTAGE TECHNOLOGY Z. Xiao1, D. Pantic2, and R. S. Popovic1 1 Institute of Microelectronics and Microsystems, Ecole Polytechnique Fédérale de Lausanne (EPFL), Lausanne, SWITZERLAND (Tel : +41-21-693-6742; E-mail: zhen.xiao@epfl.ch) 2 Department of Microelectronics, University of Niš, Niš, SERBIA (Tel : +381-18-529-105; E-mail: panta@elfak.ni.ac.yu) TRANSDUCERS & EUROSENSORS ’07 The 14th International Conference on Solid-State Sensors, Actuators and Microsystems, Lyon, France, June 10-14, 2007 Abstract: We report a new single photon avalanche diode (SPAD) implemented in a commercially available high-voltage CMOS technology. The SPAD was designed with relatively low-doped layers to form p-/n- junction, instead of commonly adopted p+/n- or n+/p- structures. We used the readily available layers as given by the technology without any customization or post-processing. Careful design measures were taken to ensure planar junction breakdown. Compared with a p+/n- diode, a p-/n- SPAD has relative deep junction, wide depletion region, and thus improves probability of photon detection. The measurement shows a maximum photon detection efficiency of 34.4%, and remains above 20% from 400nm to 620nm, whereas the dark count rate is only 50cps at room temperature with 5V excess voltage. Keywords: Single Photon Detection, Avalanche Photodiode, Geiger mode, CMOS SPAD. denoted as p+ or n+. A commonly adopted p+/nstructure [2-5] is shown in Fig. 1. 1. INTRODUCTION Photodiodes operating in Geiger mode are generally referred to as single photon avalanche diodes (SPADs), since the absorption of a single photon can initiate a strong avalanche current pulse. They are of particular interest in applications utilizing the quantum nature of light, such as fluorescence lifetime imaging (FLIM), fluorescence correlation spectroscopy, optical quantum cryptography, and rangefinding based on time-of-flight (TOF) of light. Although solid-state SPADs have been available for decades [1], they are generally fabricated in customized processes, which results in bulky and expensive devices. Another main drawback is their incompatibility with integrated electronics, and the difficulty of fabricating SPAD arrays. Since a few years, SPADs based on CMOS processes have been successfully implemented [25]. This greatly eases the integration of electronics, and enables the compact array implementation. However, existing CMOS SPADs utilize heavily-doped shallow junctions only. More specifically, they are implemented with layers used for the drain / source of CMOS transistors, p+ n+ n+ p+ p-tub p+ p-tub deep n-tub p-substrate Fig. 1 Schematic of commonly adopted p+/nSPAD structure in CMOS technologies. This structure limits the performances of SPADs in several ways. Firstly, the photon detection efficiency (PDE) is relatively low due to the narrow depletion width and multiplication region. Besides, the junction depth of p+/n- is too shallow to detect efficiently red and near infra-red photons. The typical spectral response of such a device has peak efficiency in blue region and then decays drastically. However, the low-energy photons are of interest in many applications, for example, fluorescence detection in bio-imaging. Noise performance is another concern as the heavily-doped CMOS layers are prone to have generation and trapping centers. The likelihood of tunneling-induced dark counts also increases with 1365 1-4244-0842-3/07/$20.00©2007 IEEE 3B1.3 the periphery. Moreover, a floating diffusion ring is added to further reduce the electric field at the corners. p+ Shallow p-tub p+ n+ n+ p+ Deep p-tub deep n-tub p-substrate Fig. 2 Schematic of our proposed SPAD structure using p-/n- junction in CMOS technology. All these layers are used as given in a 0.35µm CMOS technology which is designed for highvoltage electronics. The process parameters are extracted from doping profile measurements, and used for simulations in Silvaco’s ATHENA and ATLAS tools. To ensure uniform breakdown at the planar junction, various structures have been studied to find a reliable guard ring design. The simulation results of three different structures are presented in Fig. 3. 2. DESIGN AND SIMULATION TRANSDUCERS & EUROSENSORS ’07 The 14th International Conference on Solid-State Sensors, Actuators and Microsystems, Lyon, France, June 10-14, 2007 the doping levels. As the feature-size shrinks in advanced CMOS technology, the dark count rate and afterpulsing will be worsened if p+ or n+ is still used to form SPAD junctions. In this paper, we demonstrate a new SPAD structure using relatively low-doped layers available in commercial CMOS technology. With p-/n- junction, we increase the junction depth and extend the depletion region considerably, thus improving the spectral response while ensuring low dark counts. The design concept and simulation of the structure is elaborated in Section 2; Section 3 presents the experimental results of the implemented SPAD. Fig. 2 illustrates the concept of our proposed SPAD structure. The cathode is a deep n-tub isolating the device from p-substrate, and the anode is now a combination of deep p-tub and shallow p-tub. The shallow p-tub is sized smaller than the deep p-tub, in order to reduce doping concentration and hence the electrical field along P2 P4 P6 (a) (c) (b) Fig. 3 Simulations of 3 different SPAD structures with p-/n- junctions, namely P2, P4 and P6. Results are shown in cross-sectional view with half planes only: (a) doping concentrations, (b) electrical fields, and (c) current distributions. 1366 1-4244-0842-3/07/$20.00©2007 IEEE 3B1.3 corresponding to a peak current of 30A. The persistent accumulated waveform shows a long recharge time of 3.7s due to the large parasitic capacitances in the hybrid setup. Rq 50Ÿ Fig. 5 Setup of hybrid passive quenching configuration. A persistent accumulated waveform of avalanche current pulses is shown on the right. Finally, the SPAD is operated with an active quenching module developed by [6], where a gated mode is available. This setup was then used to perform the optical and dark count rate measurements [7-8], in order to avoid false counts due to afterpulses. The experimental results of the optimized structure P6 are presented in Fig. 6~8. With an active area of 5um in diameter and an excess bias of 5V, the photon detection efficiency (PDE) reaches the peak value of 34.4%. There is a visible plateau from 450nm to 520nm, where the PDE does not vary more than 1.5% from the maximum. The efficiency remains above 20% from 410nm to 640nm, and reaches 10% at 750nm and 5% at 840nm. The falling-off towards red and near IR is more gradual than those of CMOS SPADs with p+/n- [2-5]. 1.00E-06 1.00E-07 Vd (V) 30 35 40 45 50 Time (1µs/div) Oscilloscope After CMOS fabrication, the devices were first measured statically. Experimental data of reverse I-V characteristics, shown in Fig. 4, corroborated the simulation results. As expected, P6 has the highest breakdown voltage, 50V. 1.00E-05 Voltage (5mV/div) Vop 3. MEASUREMENT RESULTS Id (A) 55 P2 P4 P6 35% 1.00E-08 30% 1.00E-09 25% 1.00E-10 PDE TRANSDUCERS & EUROSENSORS ’07 The 14th International Conference on Solid-State Sensors, Actuators and Microsystems, Lyon, France, June 10-14, 2007 The first structure, namely P2, is constructed with equally-sized deep p-tub and shallow p-tub. The high electrical field is clearly observed at the edge due to the high doping levels there, and the current flows near the surface. In the second structure, namely P4, the size of shallow p-tub is reduced compared to the deep p-tub. It effectively lowers the peripheral electrical fields, but the high fields concentrate at the junction corners where the curvature effect dominates. The current distribution shows the localized breakdown phenomenon. Finally, the optimal structure P6 adds a floating diffusion ring around to leverage the electrical field. The current distribution proves the planar junction breakdown. One shall note that the depletion region is as wide as 2.5m, and extends to both sides of the junction at a depth of 0.8m. This is more than twice the values of p+/n- junctions in the same CMOS technology. However, this suggests that the breakdown voltage is considerably increased as well. Fig. 4 Measured reverse characteristics of the three implemented SPADs, P2, P4 and P6. Ve=5V Ve=4V 20% 15% 10% 5% Device P6 was then tested in Geiger mode operation, with a discrete quenching resistor of 250KŸ. As shown in Fig. 5, the avalanche current pulses are sensed through a 50Ÿ resistance. The maximum signal value is about 15mv, 0% 370 420 470 520 570 620 670 720 770 820 870 920 970 Wavelength [nm] Fig. 6 Measured photon detection efficiency of P6 with excess bias voltages of 4V and 5V. 1367 1-4244-0842-3/07/$20.00©2007 IEEE 3B1.3 Fig. 6 shows the typical exponential increase of the dark count rate (DCR) versus the excess bias voltage. The DCR is below 50cps at room temperature (about 24C) with 5V excess voltage. Such a low level of dark noise enables further increase of the active area, and hence the fill factor to further improve the performance. 4. CONCLUSIONS A new SPAD structure using p-/n- junction was successfully designed and implemented in a CMOS technology. Without any technology customization or post-processing steps, the optimized SPAD exhibits favorable results in dark count rate and photon detection efficiency, while timing jitter remains comparable to existing p+/nSPADs. Thanks to the full CMOS compatibility, it can be easily integrated with electronics to realize large arrays of single photon detectors. 10 ACKNOWLEDGEMENTS 1 This work is supported by Swiss National Science Foundation. The authors are grateful to Cristiano Niclass for his contributions to measurement setup, and Marc Lany for helpful discussions. Reverse Bias Voltage (V) 50.0 51.0 52.0 53.0 54.0 55.0 56.0 Fig. 7 Measured dark count rate of P6 at room temperature of 24C. Timing jitter was measured with a picosecond laser source of 637nm. The passive quenching is used to avoid extra jitter introduced by active electronics. As shown in Fig. 7, a FWHM of 80ps is achieved with 5V excess voltage. Number of counts 1000 180 160 100 10 140 FWHM [ps] TRANSDUCERS & EUROSENSORS ’07 The 14th International Conference on Solid-State Sensors, Actuators and Microsystems, Lyon, France, June 10-14, 2007 D C R (1 /s ) 100 1 248.5n 120 249.0n 249.5n Time (s) 250.0n 250.5n 100 80 60 50 51 52 53 54 55 56 Reverse Bias Voltage [V] Fig. 8 Measured timing jitter of P6 in terms of FWHM versus bias voltages. Insert: Timing distribution at excess voltage of 5V. REFERENCES [1] R. J. Mc Intyre, “Recent developments in silicon avalanche photodiodes”, Measurement, vol. 3, pp. 146-152, 1985. [2] A. Rochas et al., “Single Photon Detector Fabricated in CMOS High Voltage Technology”, Review of Scientific Instruments, vol. 74, pp. 3263-3270, 2003. [3] F. Zappa et al., “Monolithic CMOS Detector Module for Photon Counting and Picosecond Timing”, IEEE, ESSDERC, pp. 341344, Sept. 2004. [4] C. Niclass et al., “Design and Characterization of a CMOS 3D Image Sensor based on SPADs”, IEEE Journal of Solid-State Circuits, pp. 1847-1854, Sep 2005. [5] C. Niclass et al., “A SPAD Array Fabricated in 0.35um CMOS and based on an Event-Driven Readout for TCSPC Experiments”, Proc. of SPIE, Vol. 6372, Oct. 2006. [6] Id Quantique, www.idquantique.com. [7] A. Lacaita et al., “Single-Photon Detection beyond 1µm: Performance of Commercially Available InGaAs/InP Detectors”, Applied Optics, vol.35, no. 16, pp. 2986-2996, 1996. [8] C. P. Morath et al., “Comparator-Based Measurement Scheme for Dark-Count Rates in SPADs”, IEEE Trans. Instrumentation and Measurement, vol. 54, pp. 2020-2026, 2005. 1368 1-4244-0842-3/07/$20.00©2007 IEEE