Energy Efficient Code Converters using Reversible Logic Gates

Energy Efficient Code Converters using Reversible Logic Gates Chapter 1 INTRODUCTION 1.1Project Introduction Department of VLSI and EMBEDDED SYSTEM GHRCEM, Pune 1 Energy Efficient Code Converters using Reversible Logic Gates 1.2Motivation of the Project Energy dissipation is one of the major issues in present day technology. Energy dissipation due to information loss in high technology circuits and systems constructed using irreversible hardware was demonstrated by R. Landauer in the year 1960. According to Landauers[1] principle, the loss of one bit of information lost, will dissipate kT*ln (2) joules of energy where, k is the Boltzmanns constant, T is the absolute temperature. In 1973, Bennett [2], showed that in order to avoid kTln2 joules of energy dissipation in a circuit it must be built from reversible circuits. According to Moores law the numbers of transistors will double every 18 months. Thus energy conservative devices are the need of the day. The amount of energy dissipated in a system bears a direct relationship to the number of bits erased during computation. Reversible circuits are those circuits that do not lose information. The current irreversible technologies will dissipate a lot of heat and can reduce the life of the circuit. The reversible logic operations do not erase (lose) information and dissipate very less heat. Synthesis of reversible logic circuit differs from the combinational one in many ways. Reversible logic has become one of the most promising research areas in the past few decades and has found its applications in several technologies; such as low power CMOS, nanotechnology and optical computing. The main purposes of designing reversible logic code converter are to decrease Department of VLSI and EMBEDDED SYSTEM GHRCEM, Pune 2 Energy Efficient Code Converters using Reversible Logic Gates quantum cost, depth of the circuits and the number of garbage outputs. 1.2.1 Reversible logic Regular new innovation which is quicker, littler and more unpredictable than its ancestor is being produced. The increment in clock recurrence to accomplish more prominent speed and increment in number of transistors stuffed onto a chip to accomplish intricacy of a traditional framework brings about expanded force utilization. All the huge number of doors used to perform sensible operations in an ordinary PC are irreversible. That is, each time a coherent operation is performed some data about the info is eradicated or lost and is dispersed as warmth. In computerized outline vitality misfortune is considered as a vital execution parameter. More elevated amounts of mix and new creation procedures have significantly lessened the warmth misfortune in the course of the most recent decades. The force dissemination in a circuit can be lessened by the utilization of Reversible rationale.[3] Reversible rationale permits you to do some of your energy administration and warmth administration in the computerized area. What do advanced force administration and computerized warmth administration even mean? Advanced force alludes to requested bit designs, which can be utilized to do computerized work. Advanced warmth alludes to cluttered bit designs that are horrible to anybody. Administration of computerized force includes moving it to where it is required. Administration of computerized warmth includes moving it to where it can be dumped. Inside an advanced domain there are expansive scope of segments accessible for these errands - and they are alertly reconfigurable.[6] One advantage is that advanced warmth funnels are accessible that direct in one heading profoundly productively without disseminating computerized warmth in different headings. That permits you to pipe entropy far from the area where the processing is being performed while it is still in a reasonable, advanced structure - before changing it into genuine warmth. The era of genuine warmth might likewise be conceded - by putting away computerized warmth in a repository. Computerized warmth funnels may be connected where they are most required, and their areas can change over the long haul in a way controlled by programming. There are comparative favorable circumstances to doing computerized force administration. The outcome is similar to having a scope of diverse voltage force rails accessible, and having the capacity to control their areas. Advanced capacitors of configurable sizes can be built, so power is accessible when and where it is needed.[5] Blunder amendment ought to likewise be done basically digitally. Figuring equipment ought to be made solid, yet ought not endeavor to perform blunder adjustment - because of the extra multifaceted nature and warmth issues this presents. Advanced blunder adjustment is surely knew, and is monstrously adaptable and versatile contrasted with doing mistake amendment in equipment. Obviously, without running things in reverse, such advanced force administration should in the end be went down by a genuine power supply. Also a computerized warmth scattering framework should inevitably radiate the warmth into this present reality. However the extra control offered by taking care of these things digitally merits something. These advantages may well result [7]in a humble lessening of warmth era - and in lower force prerequisites. However presumably their Department of VLSI and EMBEDDED SYSTEM 7 GHRCEM, Pune Energy Efficient Code Converters using Reversible Logic Gates primary noteworthiness is that they make it less demanding for most power supply and warmth dispersal issues to be kept remote from the principle registering gadget. That ought to help make preparing units more uniform - and ought to disentangle the outline requirements on individual segments. Those impacts ought to help encourage their development by means of sub-atomic selfgathering. The presence of amazingly powerful advanced warmth channels ought to additionally help diminish a portion of the warmth dispersal issues of registering in three measurements. 1) Power Management 2) Heat Management Some important points of power management and heat management • Digital power refers to ordered bit patterns, which can be used to do digital work. • Digital heat refers to disordered bit patterns that are no good to anyone. • Management of digital power involves moving it to where it is needed. • Management of digital heat involves moving it to where it can be dumped. Power management Intersil’s advanced and simple controllers, power modules and exchanging controllers give a complete arrangement of answers for the end client. By expanding on to innovation created for registering applications, Intersil gives better power administration frameworks than a much more extensive arrangement of utilizations. Intersil is one of only a handful couple of organizations with not just low power, low voltage, high-effectiveness arrangements, additionally higher cell check voltage, higher-power, high-productivity arrangements and propelled bundling strategies. Heat Management Heat management of high performance VLSIs is becoming one of the most important issues for scaled CMOS technologies. These issues include power and junction temperature approximation for normal and stress conditions, long term consistency in normal working conditions and consistency screening of the chip under stress conditions. Some of these issues were described and some novel methodologies to address them were developed. In chapter two, burn-in as screening test and the burn-in issues with respect to technology scaling were discussed. In chapter three, after reviewing the concept of the thermal resistance of the CMOS, a novel technique was introduced to estimate the junction temperature in normal and burn-in conditions. The technique was used for burning optimization with respect to reliability and yield. In chapter four a new insight for thermal runaway as a threat to the yield of VLSI chips during burn-in was discussed. Department of VLSI and EMBEDDED SYSTEM GHRCEM, Pune 4 Energy Efficient Code Converters using Reversible Logic Gates 1.3 System Related Information In this section, fundamentals related to reversible logic are presented. A Reversible gate is a k-input, k-output circuit that produces a unique output pattern for each possible input pattern. Reversible gates are circuits in which the number of outputs is equal to the number of inputs and there is one to one correspondence between the vector of inputs and outputs, i.e., it can generate unique output vector from each input vector and vice versa. Unwanted or unused output of a reversible gate is known as Garbage output. More formally, the outputs, which are needed only to maintain reversibility, are called garbage outputs. Quantum cost refers to the cost of the circuit in terms of the cost of a primitive gate. It is calculated knowing the number of primitive reversible logic gates required to realize the circuit. The delay of a logic circuit is the maximum number of gates in a path from any input line to any output line. This is based on the following assumptions (i) Each gate performs computation in one unit time. (ii) All inputs to the circuit are available before the computation begins. 1.3.1 The Use of ReversibleLogic in the system The n-input and k-output Boolean function f(x1, x2, x3 xn) (referred to as (n, k) function) is called reversible if 1) The number of outputs is equal to the number of inputs 2) Each input pattern maps to unique output patterns Reversible Logic Gate Reversible Gates are circuits in which number of outputs is equal to the number of inputs .And there is a one to one mapping between the vector of inputs and outputs . It helps to determine the outputs from the inputs as well as helps to uniquely recover the inputs from the outputs. Ancilla inputs/Constant inputs This can be defined as the number of inputs that are to be maintain constant at either 0 or 1 in order to synthesize the given logical function. Garbage Outputs Additional inputs or outputs can be added so as to make the number of inputs and outputs equal whenever required. This also indicates the number of outputs which are not used in the synthesis of a given function. In certain cases these become mandatory to attain reversibility. Therefore garbage is the number of outputs added to make an n-input k-output function ((n; k) function) reversible. Constant inputs are used to denote the present value inputs that are added to an (n; k) function to Department of VLSI and EMBEDDED SYSTEM GHRCEM, Pune 5 Energy Efficient Code Converters using Reversible Logic Gates make it reversible. The following simple formula shows the relation between the number of garbage outputs and constant inputs. Input + constant input = output + garbage. Quantum Cost Quantum cost may be defined as the cost of the circuit in terms of the cost of a primitive gate. It is calculated by the number of primitive reversible logic gates (1*1 or 2*2) required to realize the circuit. The quantum cost of a circuit is the minimum number of 2*2 unitary gates to represent the circuit keeping the output unchanged. The quantum cost of a 1*1 gate is 0 and that of any 2*2 gate is the same, which is 1 1.4 Reversible Gates The NOT gate The basic and simplest Reversible gate is conventional NOT gate and is a 1*1 gate. The block diagram is given in Figure1. The quantum cost of Reversible NOT gate is 0. Figure 1.4.1:Reversible NOT gate The Feynman Gate : The block diagram for 2 * 2 Feynman gate, also known as Controlled NOT gate is shown in Figure 2.2. This gate is one through because it passes one of its inputs. Every linear reversible function can be built by using only 2 * 2 Feynman gate and inverters. Since this is a 2 * 2 gate, the quantum cost is 1. The quantum equivalent circuit is shown in Figure 2.3. The reasons to use this gate in reversible circuits are (i) Make the copy of an input (by putting any of the input a constant 0); (ii) To invert an input bit (by putting any of the input a constant 1). Figure 1.4.2 Feynman Gate or CNOT gate Figure 1.4.3: Quantum equivalent of Feynman gate Department of VLSI and EMBEDDED SYSTEM GHRCEM, Pune 6 Energy Efficient Code Converters using Reversible Logic Gates The Toffoli gate : The input vector, Iv and output vector, Ov for 3*3 Toffoli gate is defined as follows Iv=(A,B,C) and Ov=(P=A,Q=B,R= ). The block diagram for 3 * 3 Toffoli gate is shown in Figure 4. Toffoli gate plays an important role in the reversible logic synthesis. It is also used in the design of any Boolean function and hence it can be considered as a universal reversible gate. Figure 5 shows the equivalent quantum realization of three input Toffoli gate. Figure 6 shows the equivalent Toffoli gate (which uses 2 * 2 gates only). Cost of the Toffoli gate in Figure 5 and Figure 6 is 5. In Figure 6 V is a square-root-of NOT gate and V+ is its Hermitian. Thus VV+ creates a unitary matrix of NOT gate and VV+ = 1 (an identity matrix, describing just a quantum wire). Figure 1.4.4: TofolligateorCCNOTgate Figure1.4.5:Quantum equivalent ofT offoli gate Figure 1.4.6: Minimized Toffoli gate The performance of the reversible circuit based on the following parameters 1. Garbage output The number of unused outputs present in the reversible logic circuit. 2. Number of reversible logic gates Total number of reversible logic gates used in the circuit. 3. Delay Maximum number of unit delay gates in the path of propagation of inputs to outputs. 4. Constant inputs The number of input which are maintained constant at O or 1 in order to get the required function. Department of VLSI and EMBEDDED SYSTEM GHRCEM, Pune 7 Energy Efficient Code Converters using Reversible Logic Gates Table1.4.1: Existing Reversible Logic Gates Department of VLSI and EMBEDDED SYSTEM GHRCEM, Pune 8 Chapter 2 LITERATURE SURVEY ⇒ Landauers [1] showed , the amount of energy (heat) dissipated for every irreversible bit operation is given by kTln2, where k is the Boltzmanns constant (1.3807*10-23JK-1) and T is the operating temperature. At room temperature (300 K), kTln2 is approximately 2.8 *10-21 J, which is small but not negligible. He also showed that only the logically irreversible steps in a computation carry an unavoidable energy penalty. If we could compute entirely with reversible operations, there would be no lower limit on energy consumption. ⇒ C. H. Bennett [2] in 1973 revealed that the power dissipation in any device can be made zero or negligible if the computation is done using reversible model. He proved his theory with the help of the Turing machine which is a symbolic model for computation introduced by Turing. Bennett also showed that the computations that are performed on irreversible or classical machine can be performed with same efficiency on the reversible machine. The research on the reversibility was started in 1980’s based on the above concept. ⇒ Edward Fredkin and Tommaso Toffoli [5, 6] introduced new reversible gates known as Fredkin and Toffoli reversible gates based on the concept of reversibility . These gates have zero power dissipation and are used as universal gates in the reversible circuits. These gates have three outputs and three inputs, hence they are known as 3*3 reversible gates. ⇒ Feynman [8] introduces new reversible gate known as Feynman gate. ⇒ M.L. Chuang and C.Y. Wang [11] proposed that the numbers of gates, the number of garbage output were reduced in implementing the Latches and when the results will be compared [9] with 25% improvement was achieved. ⇒ Mohammadi [7] proposed a synthesis method to realize a Reversible Binary Coded Decimal adder/subtractor circuit. Genetic algorithms and dont care concepts are used to design and optimize all parts of a Binary Coded Decimal adder circuit in terms of number of garbage inputs/outputs and quantum cost. 9 Energy Efficient Code Converters using Reversible Logic Gates Paper Title Irreversibilty and Heat Generation in the Computational Process Author Landauers Publication IBM Journal of Research 1961 System Work • (heat) dissipated for every irreversible bit • irreversible steps in a computation carry an energy penalty Logical reversibility of Computation Conservative Logic Quantum Mechanical Computers VHDL Implementation of Reversible Energy Efficient Code Converters using Reversible Logic Gates C. H. Bennett IBM Journal of Research 1973 Edward Fredkin, Tommaso Toffoli International Journal of Theory 1979 Feymam Optical News. 1985 • power dissipation in any device can be made zero if the computation is done using reversible model • (heat) Introduced new gates • gates have zero power dissipation and are used as universal gates in the reversible circuits Devendra Goyal International Journal of Advanced Technology and Engineering Research 2012 M.Saravan IEEE International Dr.K.Suresh Conference on Green Manic High Performance Computing2013 • Introduced new gate called Feynman gate Has Quantum cost 1 • Worked on VHDL codes of reversible gates •Described working of reversible code converters Table 2.0.1: Glossary Department of VLSI and EMBEDDED SYSTEM GHRCEM, Pune 10 Energy Efficient Code Converters using Reversible Logic Gates Chapter 3 Software tools used 3.1 Beginning Verilog was the first modern hardware description language to be invented. It was created by Phil Moorby and Prabhu Goel during the winter of 1983/1984. The wording for this process was ”Automated Integrated Design Systems” (later renamed to Gateway Design Automation in 1985) as a hardware modeling language. Gateway Design Automation was purchased by Cadence Design Systems in 1990. Cadence now has full proprietary rights to Gateway’s Verilog and the Verilog-XL, the HDL-simulator that would become the de-facto standard (of Verilog logic simulators) for the next decade. Originally, Verilog was intended to describe and allow simulation; only afterwards was support for synthesis added. 3.2 Verilog-95 With the increasing success of VHDL at the time, Cadence decided to make the language available for open standardization. Cadence transferred Verilog into the public domain under the Open Verilog International (OVI) (now known as Accellera) organization. Verilog was later submitted to IEEE and became IEEE Standard 1364-1995, commonly referred to as Verilog-95. In the same time frame Cadence initiated the creation of Verilog-A to put standards support behind its analog simulator Spectre. Verilog-A was never intended to be a standalone language and is a subset of Verilog-AMS which encompassed Verilog-95. 3.3 Verilog 2001 Extensions to Verilog-95 were submitted back to IEEE to cover the deficiencies that users had found in the original Verilog standard. These extensions became IEEE Standard 1364-2001 known as Verilog-2001. Verilog-2001 is a significant upgrade from Verilog-95. First, it adds explicit support for (2’s complement) signed nets and variables. Previously, code authors had to perform signed Department of VLSI and EMBEDDED SYSTEM GHRCEM, Pune 11 Energy Efficient Code Converters using Reversible Logic Gates operations using awkward bit-level manipulations (for example, the carry-out bit of a simple 8-bit addition required an explicit description of the Boolean algebra to determine its correct value). The same function under Verilog-2001 can be more succinctly described by one of the built-in operators +, -, /, *, >>>. A generate/endgenerate construct (similar to VHDL’s generate/endgenerate) allows Verilog-2001 to control instance and statement instantiation through normal decision operators (case/if/else). Using generate/endgenerate, Verilog-2001 can instantiate an array of instances, with control over the connectivity of the individual instances. File I/O has been improved by several new system tasks. And finally, a few syntax additions were introduced to improve code readability (e.g. always @*, named parameter override, C-style function/task/module header declaration). Verilog-2001 is the dominant flavor of Verilog supported by the majority of commercial EDA software packages. 3.4 Verilog 2005 Not to be confused with SystemVerilog, Verilog 2005 (IEEE Standard 1364-2005) consists of minor corrections, spec clarifications, and a few new language features (such as the uwire keyword). A separate part of the Verilog standard, Verilog-AMS, attempts to integrate analog and mixed signal modeling with traditional Verilog. Example A hello world program looks like this module main; initial begin $display(”Hello world!”); $finish; end endmodule A simple example of two flip-flops follows module toplevel(clock,reset); input clock; input reset; reg flop1; reg flop2; always @ (posedge reset or posedge clock) if (reset) begin flop1 <= 0; flop2 <= 1; end Department of VLSI and EMBEDDED SYSTEM GHRCEM, Pune 12 Energy Efficient Code Converters using Reversible Logic Gates else begin flop1 <= flop2; flop2 <= flop1; end end module The ”<=” operator in Verilog is another aspect of its being a hardware description language as opposed to a normal procedural language. This is known as a ”non-blocking” assignment. Its action doesn’t register until the next clock cycle. This means that the order of the assignments is irrelevant and will produce the same result flop1 and flop2 will swap values every clock. The other assignment operator, ”=”, is referred to as a blocking assignment. When ”=” assignment is used, for the purposes of logic, the target variable is updated immediately. In the above example, had the statements used the ”=” blocking operator instead of ”<=”, flop1 and flop2 would not have been swapped. Instead, as in traditional programming, the compiler would understand to simply set flop1 equal to flop2 (and subsequently ignore the redundant logic to set flop2 equal to flop1.) The always clause above illustrates the other type of method of use, i.e. it executes whenever any of the entities in the list (the b or e) changes. When one of these changes, a is immediately assigned a new value, and due to the blocking assignment, b is assigned a new value afterward (taking into account the new value of a). After a delay of 5 time units, c is assigned the value of b and the value of c e is tucked away in an invisible store. Then after 6 more time units, d is assigned the value that was tucked away. Signals that are driven from within a process (an initial or always block) must be of type reg. Signals that are driven from outside a process must be of type wire. The keyword reg does not necessarily imply a hardware register. 3.5 Definition of constants The definition of constants in Verilog supports the addition of a width parameter. The basic syntax is <Width in bits>’<base letter> <number> Examples • 12’h123 - Hexadecimal 123 (using 12 bits) • 20’d44 - Decimal 44 (using 20 bits - 0 extension is automatic) • 4’b1010 - Binary 1010 (using 4 bits) • 6’o77 - Octal 77 (using 6 bits) Department of VLSI and EMBEDDED SYSTEM GHRCEM, Pune 13 Energy Efficient Code Converters using Reversible Logic Gates 3.5.1Synthesizable constructs There are several statements in Verilog that have no analog in real hardware, e.g. $display. Consequently, much of the language can not be used to describe hardware. The examples presented here are the classic subset of the language that has a direct mapping to real gates. // Mux examples - Three ways to do the same thing. // The first example uses continuous assignment wire out; assign out = sel ? a b; // the second example uses a procedure // to accomplish the same thing. reg out; always @(a or b or sel) begin case(sel) 1’b0 out = b; 1’b1 out = a; Endcase; main end // Finally - you can use if/else in a // procedural structure. reg out; always @(a or b or sel) if (sel) out = a; else out = b; The next interesting structure is a transparent latch; it will pass the input to the output when the gate signal is set for ”pass-through”, and captures the input and stores it upon transition of the gate signal to ”hold”. The output will remain stable regardless of the input signal while the gate is set to ”hold”. In the example below the ”pass-through” level of the gate would be when the value of the if clause is true, i.e. gate = 1. This is read ”if gate is true, the din is fed to latchout continuously.” Once the if clause is false, the last value at latchout will remain and is independent of the value of din. // Transparent latch example reg out; always @(gate or din) if(gate) out = din; // Pass through state // Note that the else isn’t required here. The variable // out will follow the value of din while gate is high. Department of VLSI and EMBEDDED SYSTEM GHRCEM, Pune 14 Energy Efficient Code Converters using Reversible Logic Gates // When gate goes low, out will remain constant. The flip-flop is the next significant template; in Verilog, the D-flop is the simplest, and it can be modeled as reg q; always @(posedge clk) q <= d; The significant thing to notice in the example is the use of the non-blocking assignment. A basic rule of thumb is to use <= when there is a posedge or negedge statement within the always clause. A variant of the D-flop is one with an asynchronous reset; there is a convention that the reset state will be the first if clause within the statement. reg q; always @(posedge clk or posedge reset) if(reset) q <= 0; else q <= d; The next variant is including both an asynchronous reset and asynchronous set condition; again the convention comes into play, i.e. the reset term is followed by the set term. reg q; always @(posedge clk or posedge reset or posedge set) if(reset) q <= 0; else if(set) q <= 1; else q <= d; Note If this model is used to model a Set/Reset flip flop then simulation errors can result. Consider the following test sequence of events. 1) reset goes high 2) clk goes high 3) set goes high 4) clk goes high again 5) reset goes low followed by 6) set going low. Assume no setup and hold violations. In this example the always @ statement would first execute when the rising edge of reset occurs which would place q to a value of 0. The next time the always block executes would be the rising edge of clk which again would keep q at a value of 0. The always block then executes when set goes high which because reset is high forces q to remain at 0. This Department of VLSI and EMBEDDED SYSTEM GHRCEM, Pune 15 Energy Efficient Code Converters using Reversible Logic Gates condition may or may not be correct depending on the actual flip flop. However, this is not the main problem with this model. Notice that when reset goes low, that set is still high. In a real flip flop this will cause the output to go to a 1. However, in this model it will not occur because the always block is triggered by rising edges of set and reset - not levels. A different approach may be necessary for set/reset flip flops. The final basic variant is one that implements a D-flop with a mux feeding its input. The mux has a d-input and feedback from the flop itself. This allows a gated load function. // Basic structure with an EXPLICIT feedback path always @(posedge clk) if(gate) q <= d; else q <= q; // explicit feedback path // The more common structure ASSUMES the feedback is present // This is a safe assumption since this is how the // hardware compiler will interpret it. This structure // looks much like a latch. The differences are the // ”’@(posedge clk)”’ and the non-blocking ”’<=”’ always @(posedge clk) if(gate) q <= d; // the ”else” mux is ”implied” Note that there are no ”initial” blocks mentioned in this description. There is a split between FPGA and ASIC synthesis tools on this structure. FPGA tools allow initial blocks where reg values are established instead of using a ”reset” signal. ASIC synthesis tools don’t support such a statement. The reason is that an FPGA’s initial state is something that is downloaded into the memory tables of the FPGA. An ASIC is an actual hardware implementation. 3.6 Initial and always There are two separate ways of declaring a Verilog process. These are the always and the initial keywords. The always keyword indicates a free-running process. The initial keyword indicates a process executes exactly once. Both constructs begin execution at simulator time 0, and both execute until the end of the block. Once an always block has reached its end, it is rescheduled (again). It is a common misconception to believe that an initial block will execute before an always block. In fact, it is better to think of the initial-block as a special-case of the always-block, one which Department of VLSI and EMBEDDED SYSTEM GHRCEM, Pune 16 Energy Efficient Code Converters using Reversible Logic Gates terminates after it completes for the first time. //Examples initial begin a = 1; // Assign a value to reg a at time 0 1; // Wait 1 time unit b = a; // Assign the value of reg a to reg b end always @(a or b) // Any time a or b CHANGE, run the process begin if (a) c = b; else d = b; end // Done with this block, now return to the top (i.e. the @ event-control) always @(posedge a)// Run whenever reg a has a low to high change a <= b; These are the classic uses for these two keywords, but there are two significant additional uses. The most common of these is an always keyword without the @(...) sensitivity list. It is possible to use always as shown below always begin // Always begins executing at time 0 and NEVER stops clk = 0; // Set clk to 0 1; // Wait for 1 time unit clk = 1; // Set clk to 1 1; // Wait 1 time unit end // Keeps executing - so continue back at the top of the begin The always keyword acts similar to the ”C” construct while(1) .. in the sense that it will execute forever. The other interesting exception is the use of the initial keyword with the addition of the forever keyword. The example below is functionally identical to the always example above. initial forever // Start at time 0 and repeat the begin/end forever begin clk = 0; // Set clk to 0 1; // Wait for 1 time unit clk = 1; // Set clk to 1 1; // Wait 1 time unit; end Department of VLSI and EMBEDDED SYSTEM GHRCEM, Pune 17 Energy Efficient Code Converters using Reversible Logic Gates 3.7 xilinx ise 3.8 Simulation Department of VLSI and EMBEDDED SYSTEM GHRCEM, Pune 18 Energy Efficient Code Converters using Reversible Logic Gates Chapter 4 VLSI Design 4.1 VLSI Design VLSI chiefly comprises of Front End Design and BackEnd design these days.While front end design includes digital design using HDL,design verification through simulation and other verification techniques,the design from gates and design for test ability,backend design comprises of CMOS library design and its characterization.It also covers the physical design and fault simulation. 4.2 VLSI TECHNOLOGY Gone are the days when huge computers made of vacuum tubes sat humming in entire dedicated rooms and could do about 360 multiplications of 10 digit numbers in a second. Though they were heralded as the fastest computing machines of that time, they surely dont stand a chance when compared to the modern day machines. Modern day computers are getting smaller, faster, and cheaper and more power efficient every progressing second. But what drove this change? The whole domain of computing ushered into a new dawn of electronic miniaturization with the advent of semiconductor transistor by Bardeen (1947-48) and then the Bipolar Transistor by Shockley (1949) in the Bell Laboratory. Since the invention of the first IC (Integrated Circuit) in the form of a Flip Flop by Jack Kilby in 1958, our ability to pack more and more transistors onto a single chip has doubled roughly every 18 months, in accordance with the Moores Law. Such exponential development had never been seen in any other field and it still continues to be a major area of research work. The development of microelectronics spans a time which is even lesser than the average life expectancy of a human, and yet it has seen as many as four generations. Early 60s saw the low density fabrication processes classified under Small Scale Integration (SSI) in which transistor count was limited to about 10. This rapidly gave way to Medium Scale Integration in the late 60s when around 100 transistors could be placed on a single chip. Department of VLSI and EMBEDDED SYSTEM GHRCEM, Pune 19 Energy Efficient Code Converters using Reversible Logic Gates Figure 4.2.1: Comparison: First plannerIC(1961) and Intel Nehalem Quad core die It was the time when the cost of research began to decline and private firms started entering the competition in contrast to the earlier years where the main burden was borne by the military. TransistorTransistor logic (TTL) offering higher integration densities outlasted other IC families like ECL and became the basis of the first integrated circuit revolution. It was the production of this family that gave impetus to semiconductor giants like Texas Instruments, Fairchild and National Semiconductors. Early seventies marked the growth of transistor count to about 1000 per chip called the Large Scale Integration. By mid eighties, the transistor count on a single chip had already exceeded 1000 and hence came the age of Very Large Scale Integration or VLSI. Though many improvements have been made and the transistor count is still rising, further names of generations like ULSI are generally avoided. It was during this time when TTL lost the battle to MOS family owing to the same problems that had pushed vacuum tubes into negligence, power dissipation and the limit it imposed on the number of gates that could be placed on a single die. The second age of Integrated Circuits revolution started with the introduction of the first microprocessor, the 4004 by Intel in 1972 and the 8080 in 1974. Today many companies like Texas Instruments, Infineon, Alliance Semiconductors, Cadence, Synopsys, Celox Networks, Cisco, Micron Tech, National Semiconductors, ST Microelectronics, Qualcomm, Lucent, Mentor Graphics, Analog Devices, Intel, Philips, Motorola and many other firms have been established and are dedicated to the various fields in ”VLSI” like Programmable Logic Devices, Hardware Descriptive Languages, Design tools, Embedded Systems etc. Department of VLSI and EMBEDDED SYSTEM GHRCEM, Pune 20 Energy Efficient Code Converters using Reversible Logic Gates Table 4.4.1: Logical Operators 4.3 Operators Four-valued logic The IEEE 1364 standard defines a four-valued logic with four states 0, 1, Z (high impedance), and X (unknown logic value). For the competing VHDL, a dedicated standard for multi-valued logic exists as IEEE 1164 with nine levels. Department of VLSI and EMBEDDED SYSTEM GHRCEM, Pune 21 Chapter 5 Problem statement and Objective 5.1 Problem Defination While Simple logic gates might be considered as SSI devices and multiplexers and parity encoders as MSI, the world of VLSI is much more diverse. Generally, the entire design procedure follows a step by step approach in which each design step is followed by simulation before actually being put onto the hardware or moving on to the next step. The major design steps are different levels of abstractions of the device as a whole 1 Problem Specification It is more of a high level representation of the system. The major parameters considered at this level are performance, functionality, physical dimensions, fabrication technology and design techniques. It has to be a tradeoff between market requirements, the available technology and the economical viability of the design. The end specifications include the size, speed, power and functionality of the VLSI system. 2 Architecture Definition Basic specifications like Floating point units, which system to use, like RISC (Reduced Instruction Set Computer) or CISC (Complex Instruction Set Computer), number of ALUs cache size etc. 3 Functional Design Defines the major functional units of the system and hence facilitates the identification of interconnect requirements between units, the physical and electrical specifications of each unit. A sort of block diagram is decided upon with the number of inputs, outputs and timing decided upon without any details of the internal structure. 4 Logic Design The actual logic is developed at this level. Boolean expressions, control flow, word width, register allocation etc. are developed and the outcome is called a Register Transfer Level (RTL) description. This part is implemented either with Hardware Descriptive Languages like VHDL and/or Verilog. Gate minimization techniques are employed to find the simplest, or rather the smallest most effective implementation of the logic. 22 Energy Efficient Code Converters using Reversible Logic Gates 5 Circuit Design While the logic design gives the simplified implementation of the logic,the realization of the circuit in the form of a netlist is done in this step. Gates, transistors and interconnects are put in place to make a netlist. This again is a software step and the outcome is checked via simulation. 6 Physical Design The conversion of the netlist into its geometrical representation is done in this step and the result is called a layout. This step follows some predefined fixed rules like the lambda rules which provide the exact details of the size, ratio and spacing between components. This step is further divided into sub-steps which are – Circuit Partitioning Because of the huge number of transistors involved, it is not possible to handle the entire circuit all at once due to limitations on computational capabilities and memory requirements. Hence the whole circuit is broken down into blocks which are interconnected. – Floor Planning and Placement Choosing the best layout for each block from partitioning step and the overall chip, considering the interconnect area between the blocks, the exact positioning on the chip in order to minimize the area arrangement while meeting the performance constraints through iterative approach are the major design steps taken care of in this step. – Routing The quality of placement becomes evident only after this step is completed. Routing involves the completion of the interconnections between modules. This is completed in two steps. First connections are completed between blocks without taking into consideration the exact geometric details of each wire and pin. Then, a detailed routing step completes point to point connections between pins on the blocks. – Layout Compaction The smaller the chip size can get, the better it is. The compression of the layout from all directions to minimize the chip area thereby reducing wire lengths, signal delays and overall cost takes place in this design step. – Extraction and Verification The circuit is extracted from the layout for comparison with the original netlist, performance verification, and reliability verification and to check the correctness of the layout is done before the final step of packaging. 7 Packaging The chips are put together on a Printed Circuit Board or a Multi Chip Module to obtain the final finished product. Department of VLSI and EMBEDDED SYSTEM GHRCEM, Pune 23 Energy Efficient Code Converters using Reversible Logic Gates 5.2 Development Scope The first semiconductor chips held two transistors each. Subsequent advances added more and more transistors, and, as a consequence, more individual functions or systems were integrated over time. The first integrated circuits held only a few devices, perhaps as many as ten diodes, transistors, resistors and capacitors, making it possible to fabricate one or more logic gates on a single device. Now known retrospectively as small-scale integration (SSI), improvements in technique led to devices with hundreds of logic gates, known as medium-scale integration (MSI). Further improvements led to large-scale integration (LSI), i.e. systems with at least a thousand logic gates. Current technology has moved far past this mark and today’s microprocessors have many millions of gates and billions of individual transistors. At one time, there was an effort to name and calibrate various levels of large-scale integration above VLSI. Terms like ultra-large-scale integration (ULSI) were used. But the huge number of gates and transistors available on common devices has rendered such fine distinctions moot. Terms suggesting greater than VLSI levels of integration are no longer in widespread use. As of early 2008, billion-transistor processors are commercially available. This is expected to become more commonplace as semiconductor fabrication moves from the current generation of 65 nm processes to the next 45 nm generations (while experiencing new challenges such as increased variation across process corners). A notable example is Nvidia’s 280 series GPU. This GPU is unique in the fact that almost all of its 1.4 billion transistors are used for logic, in contrast to the Itanium, whose large transistor count is largely due to its 24 MB L3 cache. Current designs, unlike the earliest devices, use extensive design automation and automated logic synthesis to lay out the transistors, enabling higher levels of complexity in the resulting logic functionality. 5.3 Objective The main objective of the project is Power Management & Heat Management Some important points of power management and heat management are • Digital power refers to ordered bit patterns,which can be used to do digital work. • Digital heat refers to disordered bit patterns that are no good to anyone. • Management of digital power involves moving it to where it is needed. • Management of digital heat involves moving it to where it can be dumped. Department of VLSI and EMBEDDED SYSTEM GHRCEM, Pune 24 Chapter 6 Modeling And Development of The System 6.1 Basic Block Diagram of the total target system Figure 6.1.1: Proposed system of Energy efficient code converters uses Software Tool: XILINX Language: Verilog HDL In this technological world development in the field of nanometer technology leads to minimize the power consumption of logic circuits. Reversible logic design has been one of the promising technologies gaining greater interest due to less dissipation of heat and low power consumption. Reversible logic has received significant attention in recent years. It has applications in various research areas such as low power CMOS design, optical computing, quantum computing, bioinformatics, thermodynamic technology, DNA computing and nanotechnology. It is not possible to construct quantum circuits without reversible logic gates. Synthesis of reversible logic circuits is significantly more complicated than traditional irreversible logic circuits because in a reversible logic circuit, we are not allowed to use fan-out and feedback. In digital systems code conversion is a widely used process for reasons such as enhancing security of data, reducing the complexity of arithmetic operations and thereby reducing the hardware required, dropping the level of switching activity leading to more speed of operation and power saving etc. 25 Energy Efficient Code Converters using Reversible Logic Gates 6.2 Existing method The design for code conversion such as Binary to Gray code, Gray to Binary code, BCD to Excess 3 code, Excess 3 to BCD code designed by using conventional gates like AND, NOT, XOR etc. using the Boolean expressions. 6.2.1 binary to gray code converter Figure 6.2.2 gray to binary code converter Department of VLSI and EMBEDDED SYSTEM GHRCEM, Pune 26 Energy Efficient Code Converters using Reversible Logic Gates 6.3 Proposed method The development in the field of nanometer technology leads to minimize the power consumption of logic circuits. Reversible logic design has been one of the promising technologies gaining greater interest due to less dissipation of heat and low power consumption. In the digital design, the code converters are widely used process. So, the reversible logic gates and reversible circuits for realizing code converters like as Binary to Gray code, Gray to Binary code, BCD to Excess 3 code, Excess 3 to BCD codes using reversible logic gates is proposed. Designing of reversible logic circuit is challenging task, since not enough number of gates are available for design. Reversible processor design needs its building blocks should be reversible in this view the designing of reversible code converters became essential one. In the digital domain, data or information is represented by a combination of 0s and 1s. A code is basically the pattern of these 0s and 1s used to represent the data. Code converters are a class of combinational digital circuits that are used to convert one type of code in to another. The proposed design leads to the reduction of power consumption compared with conventional logic circuits. 6.3.1 Reversible Binary to Gray and Gray to binary code converter Binary to Gray code converters used to reduce switching activity by achieving single bit transition between logical sequences. If Input vector is I(D,C,B,A) then the output vector o(Z,Y,X,W). The Figure 6.3.1: Circuit diagram of Reversible Binary to Gray code converter Figure 6.3.2: Circuit diagram of Reversible Gray code to Binary converter Department of VLSI and EMBEDDED SYSTEM GHRCEM, Pune 27 Energy Efficient Code Converters using Reversible Logic Gates Table 6.3.1: Truth Table of FG Gate circuit is constructed with the help of Feynman Gate (FG) gate, the Table 3.1 shows the truth table of FG gate and figure 3.1 3.2 shows the circuit diagram of reversible Binary to Gray code converter Gray to Binary code converter. Department of VLSI and EMBEDDED SYSTEM GHRCEM, Pune 28 Energy Efficient Code Converters using Reversible Logic Gates 6.3.2 Reversible BCD to Excess-3 code and Excess-3 to BCD code converter BCD to Excess-3 code converter used in arithmetic operational circuits to reduce the overall hardware complexity, The circuit is constructed with the help of two reversible gates Feynman Gate (FG) and Universal Reversible Gate (URG). Figure 6.3.3: Circuit diagram of Reversible BCD to Excess-3 code converter Figure 6.3.4: Circuit diagram of Reversible Excess-3 to BCD code converter Department of VLSI and EMBEDDED SYSTEM GHRCEM, Pune 29 Energy Efficient Code Converters using Reversible Logic Gates Table 6.3.2: Truth Table of URG Gate Figure 6.3.5 URG gate The truth table of FG gate presented in session 3.1 and the truth table of URG gate presented in table 3.2 and the circuit diagram of Reversible BCD to Excess-3 and Excess-3 to BCD shown in figure3.3 , 3.4 respectively. URG gate has three input A,B and C and three outputs P,Q and R as shown in figure 6.3.5 . Where output Department of VLSI and EMBEDDED SYSTEM GHRCEM, Pune 30 Energy Efficient Code Converters using Reversible Logic Gates Table 6.4.1: Comparative result of different reversible logic circuits For example if T = 2a+3d then the circuit involves 2numbers of XOR logical operation and 3 numbers of OR logical operations. The performance of the design is based on the number of gate, number of garbage (not used terminals) and number of constants, in this proposed design the above said parameters are optimized to greater extent. The proposed design leads to the reduction of power consumption compared with conventional logic circuits, the design proposed is implemented with FG and URG gates only in near future with the invent of new RLG the power consumption may reduced to little more greater extent, not only that there will be a chance of implementing different logic circuits using reversible logic gates and which intern helps to increase the energy efficiency. Department of VLSI and EMBEDDED SYSTEM GHRCEM, Pune 31 Chapter 7 Design Challenges Structured VLSI design is a modular methodology originated by Carver Mead and Lynn Conway for saving microchip area by minimizing the interconnect fabrics area. This is obtained by repetitive arrangement of rectangular macro blocks which can be interconnected using wiring by abutment. An example is partitioning the layout of an adder into a row of equal bit slices cells. In complex designs this structuring may be achieved by hierarchical nesting. Structured VLSI design had been popular in the early 1980s, but lost its popularity later because of the advent of placement and routing tools wasting a lot of area by routing, which is tolerated because of the progress of Moore’s Law. When introducing the hardware description language KARL in the mid’ 1970s, Reiner Hartenstein coined the term ”structured VLSI design” (originally as ”structured LSI design”), echoing Edsger Dijkstra’s structured programming approach by procedure nesting to avoid chaotic spaghetti-structured programs. 7.1 Challenges As microprocessors become more complex due to technology scaling, microprocessor designers have encountered several challenges which force them to think beyond the design plane, and look ahead to post-silicon. • Power usage/Heat dissipation As threshold voltages have ceased to scale with advancing process technology, dynamic power dissipation has not scaled proportionally. Maintaining logic complexity when scaling the design down only means that the power dissipation per area will go up. This has given rise to techniques such as dynamic voltage and frequency scaling (DVFS) to minimize overall power. • Process variation As photolithography techniques tend closer to the fundamental laws of optics, achieving high accuracy in doping concentrations and etched wires is becoming more difficult and prone to errors due to variation. Designers now must simulate across multiple fabrication process corners before a chip is certified ready for production. 32 Energy Efficient Code Converters using Reversible Logic Gates • Stricter design rules Due to lithography and etch issues with scaling, design rules for layout have become increasingly stringent. Designers must keep ever more of these rules in mind while laying out custom circuits. The overhead for custom design is now reaching a tipping point, with many design houses opting to switch to electronic design automation (EDA) tools to automate their design process. • Timing/design closure As clock frequencies tend to scale up, designers are finding it more difficult to distribute and maintain low clock skew between these high frequency clocks across the entire chip. This has led to a rising interest in multicore and multiprocessor architectures, since an overall speedup can be obtained by lowering the clock frequency and distributing processing. • First-pass success As die sizes shrink (due to scaling), and wafer sizes go up (to lower manufacturing costs), the number of dies per wafer increases, and the complexity of making suitable photomasks goes up rapidly. A mask set for a modern technology can cost several million dollars. This non-recurring expense deters the old iterative philosophy involving several ”spin-cycles” to find errors in silicon, and encourages first-pass silicon success. Several design philosophies have been developed to aid this new design flow, including design for manufacturing (DFM), design for test (DFT), and Design for X. Department of VLSI and EMBEDDED SYSTEM GHRCEM, Pune 33 Energy Efficient Code Converters using Reversible Logic Gates Chapter 8 Test Specification and Result Screenshot 1. Below screenshot shows the knowledge about properties of device and software language used for programming means it gives knowledge about project characteristics in terms of both hardware and software. 2. Next step involves adding existing verilog codes of different reversible logic circuits for project implementation and simulation results. Department of VLSI and EMBEDDED SYSTEM GHRCEM, Pune 34 Energy Efficient Code Converters using Reversible Logic Gates 3. The code which we are going to implement that should be set as top module. Below screen shot shows code for Binary to Gray code converter. We can check whether the code is synthetically correct or not from the process window from the synthesize-XST 4. We can see the RTL schematics and Technology schematics from the process window. For Reversible Binary to gray code there are three garbage outputs. 5. We gate RTL schematic for Reversible Binary to Gray as shown in next screen shot which contain input a,b and output p,q output of p is unusable output i.e garbage output Department of VLSI and EMBEDDED SYSTEM GHRCEM, Pune 35 Energy Efficient Code Converters using Reversible Logic Gates 6. Next we can check Technology schematic from the process window which gives knowledge of the device in terms of input output buffers and LUTs. 7. After checking Technology and RTL schematic we can see the Design Summery for device logic utilization in terms of number of slices, number of 4 input LUTs and number of input buffers used. Department of VLSI and EMBEDDED SYSTEM GHRCEM, Pune 36 Energy Efficient Code Converters using Reversible Logic Gates 8. After synthesis we go for simulation, In this process test bench program for binary to gray is verified by checking syntax through Xilinx ISE simulator. 9. When the program is synthetically correct we go for final simulation by clicking on simulate behavioral model and we get simulation result as follows 9.1) Simulation result for Binary to Gray code converter All above steps are repeated to get simulation result for Gray to Binary, BCD to Excess 3 and Excess 3 to BCD code converters 9.2) Simulation result for Gray to Binary code converter Department of VLSI and EMBEDDED SYSTEM GHRCEM, Pune 37 Energy Efficient Code Converters using Reversible Logic Gates 9.3) Simulation result for BCD to Excess 3 code converter 9.4) Simulation result for Excess 3 to BCD code converter Department of VLSI and EMBEDDED SYSTEM GHRCEM, Pune 38 Energy Efficient Code Converters using Reversible Logic Gates 8.1 Synthesis report: Release 9.2i - xst J.36 Copyright (c) 1995-2007 Xilinx, Inc. All rights reserved. –> Parameter TMPDIR set to ./xst/projnav.tmp CPU : 0.00 / 0.12 s | Elapsed : 0.00 / 0.00 s –> Parameter xsthdpdir set to ./xst CPU : 0.00 / 0.12 s | Elapsed : 0.00 / 0.00 s –> Reading design: binarygray.prj 8.1.1 TABLE OF CONTENTS 1 Synthesis Options Summary 2 HDL Compilation 3 Design Hierarchy Analysis 4 HDL Analysis 5 HDL Synthesis 5.1 HDL Synthesis Report 6 Advanced HDL Synthesis 6.1 Advanced HDL Synthesis Report 7 Low Level Synthesis 8 Partition Report 9 Final Report 9.1 Device utilization summary 9.2 Partition Resource Summary 9.3 TIMING REPORT Synthesis Options Summary Department of VLSI and EMBEDDED SYSTEM GHRCEM, Pune 39 Energy Efficient Code Converters using Reversible Logic Gates Department of VLSI and EMBEDDED SYSTEM GHRCEM, Pune 40 Energy Efficient Code Converters using Reversible Logic Gates HDL Compilation Compiling verilog file ”../code converter/converter/fg.v” in library work Compiling verilog file ”../code converter/converter/binarygray.v” in library work Module <fg> compiled Module <binarygray> compiled No errors in compilation Analysis of file <”binarygray.prj”> succeeded. Design Hierarchy Analysis Analyzing hierarchy for module <binarygray> in library <work>. Analyzing hierarchy for module <fg> in library <work>. HDL Analysis Analyzing top module <binarygray>. Module <binarygray> is correct for synthesis. Analyzing module <fg> in library <work>. Module <fg> is correct for synthesis. HDL Synthesis Performing bidirectional port resolution... Synthesizing Unit <fg> Related source file is ”../code converter/converter/fg.v”. Found 1-bit xor2 for signal <q> Unit <fg> synthesized. Synthesizing Unit <binarygray>. Related source file is ”../code converter/converter/binarygray.v”. Unit <binarygray> synthesized. Department of VLSI and EMBEDDED SYSTEM GHRCEM, Pune 41 Energy Efficient Code Converters using Reversible Logic Gates Table 8.1.1: HDL Synthesis Report Table 8.1.2: Advanced HDL Synthesis Report Advanced HDL Synthesis Loading device for application RfDevice from file ’3s100e.nph’ in environment C: Xilinx92i. Low Level Synthesis Optimizing unit <binarygray> ... Mapping all equations... Building and optimizing final netlist ... Found area constraint ratio of 100 (+ 5) on block binarygray, actual ratio is 0. Final Macro Processing ... Final Register Report Found no macro: Partition Report Partition Implementation Status No Partitions were found in this design. Final Report Department of VLSI and EMBEDDED SYSTEM GHRCEM, Pune 42 Energy Efficient Code Converters using Reversible Logic Gates Partition Resource Summary: No Partitions were found in this design. TIMING REPORT NOTE: THESE TIMING NUMBERS ARE ONLY A SYNTHESIS ESTIMATE. FOR ACCURATE TIMING INFORMATION PLEASE REFER TO THE TRACE REPORT GENERATED AFTER PLACE-and-ROUTE. Clock Information: No clock signals found in this design Asynchronous Control Signals Information No asynchronous control signals found in this design Timing Summary: Speed Grade: -4 Department of VLSI and EMBEDDED SYSTEM GHRCEM, Pune 43 Energy Efficient Code Converters using Reversible Logic Gates Timing Detail: All values displayed in nanoseconds (ns) CPU : 2.77 / 2.91 s — Elapsed : 3.00 / 3.00 s –> 8.2 Downloading bit file to FPGA Generating bit file After getting simulation result for downloading bit file to FPGA Sparten XC3S200 we create one Implementation constraint file in current running code. After creating User constraint file we go to the Process window, now we go in Implementation design in that we go for place and route in place and route we select Back annotate pin locations in that we can see locked pin constraint by clicking on View lock pin constraint. We get locked pin constraint for given code for the Device now we can edit these pin constraint by using Constraint window editor we have to copy the locked pin constraint and paste those pin Department of VLSI and EMBEDDED SYSTEM GHRCEM, Pune 44 Energy Efficient Code Converters using Reversible Logic Gates constraint in editor window, according to the Device manual we can assign new values to the pin constraints for device implementation. Now we can generate programming file from process window. By checking all these things it will generate the bit file. Now for downloading bit file to Sparten XC3S200 board we have to connect the board to the system. After turning device on we have to click on configure device in process window, then it will give actually the bit file. By clicking on bit file we can program the bit file, after getting the notation program succeeded we can see the light on the FPGA board turns on. Now we can demonstrate the code conversion within a instant by using the Sparten XC3S200 board. Design Statistics # IOs : 20 Cell Usage: # BELS : 11 # INV : 1 # LUT2 : 5 # LUT3 : 3 # LUT4 : 1 16 # VCC : 1 # IO Buffers : 20 # IBUF : 4 # OBUF : 16 Department of VLSI and EMBEDDED SYSTEM GHRCEM, Pune 45 Energy Efficient Code Converters using Reversible Logic Gates CONCLUSION AND FUTURE SCOPE Conclusion FUTURE SCOPE Department of VLSI and EMBEDDED SYSTEM GHRCEM, Pune 46 References [1] Yiming Liu, Victor O. K. Li,Ka-Cheong Leung,Lin Zhang.Performance Improvement of Topology-Transparent Broadcast Scheduling in Mobile Ad Hoc Networks, IEEE TRANSACTIONS ON VEHICULAR TECHNOLOGY, VOL. 63, NO. 9, NOVEMBER2014. [2] Yiming Liu, Victor O. K. Li,Ka-Cheong Leung,Lin Zhang. Topology-Transparent Scheduling in Mobile Ad Hoc Networks With Multiple Packet Reception Capability IEEE TRANSACTIONS ON WIRELESS COMMUNICATIONS, VOL.13,NO.11,NOVEMBER2014. [3] Yiming Liu, Victor O. K. Li,Ka-Cheong Leung,Lin Zhang. Topology-Transparent Broadcast Scheduling with Erasure Coding in Wireless Networks , IEEE COMMUNICATIONS LETTERS, VOL.17,NO.8,AUGUST2013. [4] Yi-Sheng Su, Szu-Lin Su, and Jung-Shian Li. Topology-Transparent Distributed Multicast and Broadcast Scheduling in Mobile Ad Hoc Networks,IEEE VEHICULAR TECHNOLOGY CONFERENCE (VTC SPRING), YOKOHAMA, JAPAN, 6-9 MAY 2012. [5] Yiming Liu, Victor O. K. Li,Ka-Cheong Leung,Lin Zhang. Is Topology-Transparent Scheduling Really Inefficient in Static Multihop Networks?,IEEE WIRELESS COMMUNICATIONS LETTERS, VOL. 2, NO. 6, DECEMBER 2013. [6] Yiming Liu, Victor O. K. Li, Ka-Cheong Leung, and Lin Zhang. Topology-Transparent Distributed Multicast and Broadcast Scheduling in Mobile Ad Hoc Networks. Department of Electrical and Electronic Engineering, University of Hong Kong, Hong Kong SAR, P.R.China. VOL. 63, NO. 9, NOVEMBER2014. [7] Qiong Sun, Topology-Transparent Distributed Scheduling in Wireless Networks, The University of Hong Kong in August 2010. [8] Guner D. Celik,Gil Zussman,Wajahat F. Khan and Eytan Modiano,MAC for Networks with Multipacket Reception Capability and Spatially Distributed Nodes. 47 Energy Efficient Code Converters using Reversible Logic Gates [9] Zhijun Cai, Mi Lu, and Costas N. Georghiades Topology-Transparent Time Division Multiple Access Broadcast Scheduling in Multihop Packet Radio Networks IEEE TRANSACTIONS ON VEHICULAR TECHNOLOGY, VOL. 52, NO. 4, JULY 2003. [10] Douglas S. Chan,Random Multiple Access Communications On Multipacket Reception Channels. CORNELL UNIVERSITY, JANUARY 2006. [11]. Peres, A., 1985. Reversible logic and quantum computers,Physical Review: A, 32 (6): 3266-3276. [12]. Azad Khan, Md.M.H., 2002. Design of full adder withreversible gate. International Conference on Computer andInformation Technology, Dhaka, Bangladesh, pp: 515-519. [13]. Haghparast, M. and K. Navi, 2007. A Novel ReversibleFull Adder Circuit for Nanotechnology Based Systems. J.Applied Sci., 7 (24): 3995-4000. [14]. Haghparast, M. and K. Navi, 2008. Design of a NovelFault Tolerant Reversible Full Adder ForNanotechnologyBased Systems, World Appl. Sci. J., 3 (1): 114-118. [15]. Perkowski, M. and P. Kerntopf, 2001. Reversible Logic.Invited tutorial, Proc. EURO-MICRO, Sept 2001, Warsaw,Poland [16]. Thapliyal Himanshu, and M.B. Srinivas, 2005.Novelreversible TSG gate and its application for designingreversible carry look ahead adderand other adderarchitectures, Proceedings of the 10th AsiaPacificComputer Systems Architecture Conference (ACSAC 05).Lecture Notes of Computer Science, Springer-Verlag,3740: 775-786. Department of VLSI and EMBEDDED SYSTEM GHRCEM, Pune 48