SIMULATING THE TRIBA NOC ARCHITECTURE

International Journal of Mobile Network Communications & Telematics ( IJMNCT) Vol. 4, No.6,December 2014 Daniel Gakwaya,GaoYuJin, Jean Claude Gombaniro and Jean Pierre Niyigena Department of Computer Science, Beijing Institute of Technology,Beijing, ABSTRACT TriBA(Triplet Based Architecture) is a Network on Chip processor(NoC) architecture which merges the core philosophy of Object Oriented Design with the hardware design of multicore processors[1].We present TriBASim in this paper, a NoC simulator specifically designed for TriBA.In TriBA ,nodes are connected in recursive triplets .TriBA network topology performance analysis have been carried out from different perspectives [2] and routing algorithms have been developed [3][4] but the architecture still lacks a simulator that the researcher can use to run simple and fast behavioural analysis on the architecture based on common parameters in the Network On Chip arena. TriBASim is introduced in this paper ,a simulator for TriBA ,based on systemc[6] .TriBASim will lessen the burden on researchers on TriBA ,by giving them something to just plug in desired parameters and have nodes and topology set up ready for analysis. KEYWORDS Keywords: NOC ,triba ,simulator,systemc 1.INTRODUCTION The last decade has seen Networks on chip emerge as a viable replacement for the traditional bus based interconnection system that has dominated in systems on chip for at least 3 decades. This is due the flexibility of design and most importantly the reduction in energy consumption for computing chips inside our electronic devices Networks on chip offer [5]. Networks on chip were introduced by a few pioneer papers that pointed out that future system on chip designs will be limited the quality of the interconnection system between computing modules [6, 7, 8]. They proposed a brand new idea that views the System on Chip as a micro-network of components. New designs would borrow ideas from the Data Networks research area and replace bus based interconnection systems with packet switched networks between modules within the System on Chip. Although Networks on Chip have a lot of similarities with Data Networks, there are differences one needs to consider .For instance NoCs are constrained to work within small distances inside the SoC while Data Networks can span kilometres of distance [6] .Also the links connection structure is more predictable for NoCs than it is for Data Networks .This led to completely new designs, protocol stacks and routing algorithms new Networks on Chip would be built upon. It is also important to note that the micro-network of components way of thinking used in NoCs allows abstraction in Traffic Modelling [9]. Numerous networks on chip architectures have been proposed in academia and industry, the topologies such as 2-D Mesh, Torus and Hypercube have been used in various network on chip designs. Along with these topologies, new routing algorithms, switching techniques and flow DOI : 10.5121/ijmnct.2014.4603 21 International Journal of Mobile Network Communications & Telematics ( IJMNCT) Vol. 4, No.6,December 2014 control mechanisms are selectively combined to meet the particular needs of the system on chip design [9]. TriBA is a network on chip architecture that enforces the concept of Object Oriented Design in the way SoCs are designed [10] .It is suitable for sophisticated embedded applications with multiple concurrent processing centres. This topology’s advantage over other 2D topologies such as hypercube topology is ease of realization and assembly [1]. Its nodes are connected in triplets, and higher order TriBA networks are recursively deduced from lower order ones. TriBASim is introduced in this paper, a simulator based on systemc specifically designed to meet the daily needs of a researcher working on TriBA . The rest of this paper is organized as follows: Section 2 explores already present NoC simulators and studies their intended use. Section 3 introduces TriBA and discusses the details relevant to our design; a NoC architecture for TriBA is developed in Section 4. The details of our TriBA NoC router are covered in Section 5 and Section 6 shows how we rely on ORION[11,12] for power consumption and area computation analysis for our simulator. Section 7 gives the results of our simulations. Sections 8 and 9 respectively outline future plans for TriBASim and conclude our paper. 2. RELATED WORK Numerous Network on Chip simulators have been developed before, targeting different areas in research and industry .Orion [11,12] was developed to run power and area analysis for Networks On Chips .Users input router and link components to build different network configurations and run their analysis .Power and area analysis for TriBASim was basen on On Orion power models .Noxim[13] NoC simulator is based on systemc ,and it can be used to evaluate the quality of a NoC in terms of delay throughput ,area and power consumption. Modified versions of Noxim have been used to run performance analysis using some popular topologies such as torus and twisted torus [14]. NIGRAM [15] is another Noc Simulator also based on systemc .It uses discrete events and is cycle accurate .It is very useful when testing routing algorithms on some regular topologies .One should also mention Nostrum[16] ,a project focusing on developing Network-on-Chip architecture. It addresses the communication issues from the physical to the application levels .These are the simulators that have been relevant to this research ,interested readers can refer to [17] to dig more and see a more detailed list . 3. TRIBA OVERVIEW “A picture is worth a thousand words!” , Fig[1] and Fig[2] will be the basis for our description of TriBA . Fig[1] displays the low level architecture for a triBA node and Fig[2] emphasizes network aspects of a TriBA interconnection which is the focus of our design .We scratch the surface on the concepts used in our design and the interested reader is referred to more in depth references where appropriate . Just like common computer architectures out there, our architecture is composed of computing modules, memory modules and the interconnection system to allow these two to communicate [18]. For triBA however special care was taken to separate computations from communication .It is composed of three sub-modules as shown in Fig[1] .ProcUnit carries out computations ,DataUnit is simply a chunk of read/write memory store our data and InterUnit ,the focus of our design, takes care of communications [1,18] .ProcUnit and DataUnit are abstracted away in our design to focus on network aspects of triBA and InterUnit is viewed as a node from here on . 22 International Journal of Mobile Network Communications & Telematics ( IJMNCT) Vol. 4, No.6,December 2014 Fig[1] TriBA Architecture Fig[2] IDC132 addressed interconnected nodes Each node is assigned an address .TriBA uses an addressing mechanism specifically designed for nodes in triplets ---IDC132 .It has impressive properties such as the reflexive symmetry of IDC132 addresses and the 120°rotation. These combined with the vertex distance computation help remarkably when computing the distance (hops) between nodes in our routing algorithms [19] . 4. TRIBA NOC ARCHITECTURE Fig[3] shows the main components of a TriBA node . The TriBApplication models end nodes in the TriBA ecosystem, which does not have to be bothered in the process of switching and routing packets (or flits) to their destinations. It represents the Processing Module .Its main task is injecting packets into the network and receiving packets from the network. If node A is communicating (sending information) with node B on a TriBA NoC ,the TribApplication of node A injects packets into the network through its injection channel and the TribApplication of node B receives the packet through its receive channel .It is important to note that the data port of a TriBApplication may have sending or/and receiving capabilities .All this is decided based the specific needs in your design. TriBApplications in TriBASim support both sending and receiving. Data rate is the frequency at which packets are injected into the network .It is expressed in bits per second. The size of packets to be sent through the network can be configured before the simulation .One can use that packet size to deduce the packet injection frequency. Simulation time is the amount of time for which simulation runs .Packets are injected into the network until simulation time runs out .Also the user may be given the capability to specify the maximum number of bits that can be injected into the network by TriBApplications. TriBApplications inject packets into the network synchronously .Packets are injected with a certain injection probability. This is if a TriBApplications injects one packet per clock cycle into the network, each network router routes one packet per clock cycle and receiving applications also receive one packet per clock cycle. Packets are injected for a certain amount of time. This time and the clock frequency are user specified parameters. TriBANode represents a network node .TriBApplications connect to it and embodies packet forwarding and routing capabilities—a router. All this through sub-modules we describe in the following sections. 23 International Journal of Mobile Network Communications & Telematics ( IJMNCT) Vol. 4, No.6,December 2014 Fig[3] The architecture of the TriBASim simulator TriBARouter’s task is to route packets from source to destination through the network. Switching mechanisms allow it to decide output ports the packet being forwarded should choose and routing algorithms help decide the next hop(TriBANode) where the packet will be sent to. Within the TriBASwitchingProtocol module ,a switching technique is specified .This along with other parameters can be specified by the user.Our simulator currently implements a wormhole switching mechanism .Other switching schemes may be subject of further improvements. TriBARoutingProtocol, just like the TriBASwitchingProtocol is a module that embodies the routing techniques used in the TriBA architecture. Routing algorithms have been developed for TriBA , TDRA ( Table Look up Deterministic Routing Algorithm ) is one of them: when a node receives a message ,it has to decide if it is the recipient of the message or if it has to forward it to neighbouring nodes .When determining the route in TDRA , there is no need to store all the network information in the node ,and thus, the transmission overhead it might have generated is avoided[20] . The algorithm uses two tables: a Channel Status Table (CST) that stores the working state of all the output ports of the node and a Route Table, that stores output port to be chosen for each destination node in the network, from the current node. DDRA (Distributed Deterministic Routing Algorithm)[21] is another routing algorithm for TriBA .It has no routing table at all, the transfer of messages is carried out based on the inherent addressing properties of TriBA nodes. IDC 132 enforces locality, this allows the message to get directly to the destination node if it is local and only go across triplet boundaries when there is need to. IDC132 also allows telling the exact location of the node in the entire interconnection network just by looking at its address. The current version of TriBASim supports DDRA . TriBANetDevice can be compared to the Networks Interface Cards of common computers in Data Networks. It is responsible for sending and receiving packets within neighbouring nodes and TriBANodes connect to the network through it. TriBARouter directly connects to TriBANetDevices. Depending on the routing protocol being used ,a TriBANetDevice will be 24 International Journal of Mobile Network Communications & Telematics ( IJMNCT) Vol. 4, No.6,December 2014 chosen to send a packet. The packet will go out through the channel that connect to that TriBANetDevice and will arrive at the node at the other end through the corresponding TriBANetDevice. TriBANetDevices have queues on their input and output terminals, this allows us to implement channel buffering. Users have the capability to tune the size of these queues. It is important to note that the size of these buffers is limited. For this reason, the network might not be able to buffer all the packets that are injected. To deal with this, we store all the data that can’t be sent currently to the local memory of the Processing Element until the network is ready to handle it. The same technique was also used in [24]. TriBANetDevices check input queues to see if there are available packets ready to be sent. If there are any, the router is tasked with computing the route for the packet located at the head of the queue. When the packet is ready to be sent, the only thing that might stand in the way of the send is the availability of the channel. When the channel is available, data is written to the channel and the packet is sent. The TriBANocChannel implements those channels directly connected to the TriBANetDevice.One can use a few parameters to qualify and classify TriBANocChannels.Data rate is the bandwidth of the channel ,in other words it is the number of bits per second that can be sent over the channel. Delay is the amount of time one has to wait until currently available data starts to be sent. The sending of data over the channel can be uni-directional or bidirectional (half-duplex or full-duplex) .We have implemented full-duplex TriBANocChannels in our simulator .The physical length of the link between nodes can also be specified. PACKET FORMAT A Flit is the smallest possible data unit that can be sent over the network, the width of the flit( 8bits ,16bits ,…..) is specified by the width of the buffers at the endpoints of TriBANocChannels. Packets are made of flits .The first flit from a packet is called a head flit. Beside the head flit, a packet can contain other data flits. The last flit in a packet is called a tail flit. The information contained in the header flit (the source and destination of the packet,…) is used to route it through the network. Data in the header of the packet is read and analysed by routers but not the data payload. The head flit is the head of the packet. In addition to the header, a head packet may also contain other body flits (These may be allocated depending on the specifics of a design). Data packets are only made of body flits. The table below shows the contents of each field in our packet header Fig[4] Packet format 25 International Journal of Mobile Network Communications & Telematics ( IJMNCT) Vol. 4, No.6,December 2014 Table [1] Fields of the triBA Noc packet header Fig[5]TriBA NoC packet header format Our simulator currently uses the source, destination and dataFlits fields .The Dist field is not used because our router uses IDC132 addressing .One can easily know the distance form a node to another just by looking at their addresses. We keep this field in our design as it may be used for further improvements to the simulator. 5. THE TRIBASIM ROUTER TriBASim has been implemented in systemC , SystemC is a set of C++ classes and macros which provide an event-driven simulation interface in C++. These facilities enable a designer to simulate concurrent processes; each described using plain C++ syntax. SystemC processes can communicate in a simulated real-time environment, using signals of all the data types offered by C++, some additional ones offered by the SystemC library, as well as user defined. In certain respects, SystemC deliberately mimics the hardware description languages VHDL and Verilog, but is more aptly described as a system-level modelling language [22]. The architecture for our TriBANocRouter is shown in the Fig[6]. It comprises a routing component, a switching component and buffers. The Processing Unit (TriBApplication) uses input channel to send data to the network and the output channel to receive data from the network. The three pairs of buffers reflect the three neighbours each TriBA node may have. The buffers are labelled North, East and West for clarity. The size of the buffers can be specified as a simulation parameter in the simulator. Packets get in the router through input channels from the Processing Element or neighbouring nodes. Packets are stored in the corresponding input buffers until they are forwarded. To be able to forward the packet, the router uses the Routing component to compute the output port out of which the packet will be sent. The routing protocol used within our TriBANoC network is incorporated within this component. It is this routing protocol that is used to determine the route followed by our packet. The router needs to carry out route computation only for the head flit. Other flits within a packet simply follow the head flit. This is achieved through a chunk of memory in the router used to store packets ‘route. When a head flit is sent the route is computed and stored. This route is valid until the tail flit of the packet is forwarded. After this a new packets’ head flit might be sent and the previous route is discarded for the newly computed route. 26 International Journal of Mobile Network Communications & Telematics ( IJMNCT) Vol. 4, No.6,December 2014 Fig[6] TriBA NoC Router Architecture After the route for the packet is computed and known, the packet is ready to be switched to its output port (channel buffer).The switching technique used by our router determines when the flits will leave the router for another one through the output channel. Our switch is implemented as a crossbar. In other words any input channel could be coupled to any output channel. It is important to note that one needs to take into account output buffer space availability though. The switch must prevent from writing to a piece of buffer space that is being used to transfer another packet. Once the flit gets to its output channel it is ready to be forwarded to the other end of the channel and this only if the channel is in idle state, i.e can transmit other flits. One should notice the importance of having output channel buffers in this design. If they were not available the switch would have to prevent packet switching when the channel is not in idle state. At the cost of increased buffer space communication is improved. Virtual channels make our router more robust in that they allow packets that would otherwise be blocked to pass. For example if a packet is coming from the North Port and headed to the West and can’t pass because another packet is using the West port, the North port blocks even if there are other packets that are headed to the East port which is idle for the moment. With virtual channels introduced this packet uses another Channel Buffer and goes East without problems. With virtual channels introduced, an allocator is needed to allocate virtual channels to packets .Also an arbiter is needed to handle situations when there are multiple requests for a single resource. Another example would be two packets one coming from the East another coming from the West both headed to the North, which one do we let pass? In our design the arbiter uses the First In First Out d arbitration mechanism and when there are competing requests for the output buffer ,it serves the request that came first and other requests are stored in a waiting queue. Requests that came first are assigned high priority. TRAFFIC PATTERNS Traffic patterns are communication patterns using permutations that are commonly performed in parallel numerical algorithms [25]. With these patterns a node cannot generate different destination addresses, the generated destination nodes are always the same for one particular 27 International Journal of Mobile Network Communications & Telematics ( IJMNCT) Vol. 4, No.6,December 2014 source node. In the following we present the traffic patterns used by TriBASim. These patterns are implemented as a set of C++ classes whose objects can be embedded in each TriBANode instance. We consider that a nodes’ address is represented by a unique string of n bits (They have , ,……….. , ). to comply with the I DC132 addressing mechanism) : ( IDC 132 ADJUSTED BIT COMPLEMENT TRAFFIC With this traffic pattern, the destination node is obtained by complementing the bits of the source node. ( , ,……….. , ) → ( , ,……….. , . ) We adjust this traffic pattern to IDC132 by discarding invalid addresses and replacing any generated string of two 0’s by a string of two 1’s.The numbers of bits in an address is determined by the order of our TriBA NoC. BIT REVERSE TRAFFIC In this traffic pattern, the destination address is obtained by reversing the bits of the source node. ( , ,……….. , ) → ( , ,............ , ). It is important to note that with this traffic pattern it is possible to generate a destination address that is exactly identical to the source node address. In this case the generated packet is simply ignored and not injected into the network. UNIFORM RANDOM TRAFFIC The above mentioned traffic patterns do not reflect a uniform utilization of the network. We therefore also included a uniform random traffic pattern. The generated destination address is completely random. After generation a purely random process is carried out to make sure the generated address is a valid TriBA NoC IDC132 address. 6. POWER CONSUMPTION AND AREA COMPUTATIONS Our analysis in terms of power consumption and area have been carried out using ORION.ORION is a power and area simulator for Networks on Chip developed at Princeton University. It was initially developed way back in 2002 and it is now widely used by the research community for NoC power consumption estimation. Their first version proposed a power model for Network on Chip routers. Dynamic and leakage power models for the basic components of NoC routers such as crossbars, arbiters and buffers were proposed. Version 2.0 of the simulator, compared to the initial one introduced remarkable improvements. Some new power models were introduced: link and clock power models and router and link area models. Also the technology models were updated. Three operating modes (high, normal and low power modes) were made available at 90 nm and 65 nm technologies, scaling down up to 32 nm. Global power consumed by a SoC can be decomposed into 3 components [26]: dynamic power, short circuit power and leakage power. Dynamic power is the power dissipated when charging 28 International Journal of Mobile Network Communications & Telematics ( IJMNCT) Vol. 4, No.6,December 2014 circuit nodes. Also called active power, this is used while the circuit is performing its functions. Short circuit power is the power due to temporary short circuit currents that occur when switching. It is very small and usually not taken into account. Leakage power is primarily due to an unwanted sub-threshold current in the transistor channel, when the transistor is turned off. As technology goes below 65 nm, leakage power becomes more important, as compared to dynamic power. .f stands The dynamic power in ORION is formulated as P = E ⋅ f , where energy E =α ⋅C ⋅ for the clock frequency, α the activity factor, C the load capacitance and the supply voltage. The key in these power computations is in finding a way to compute the load capacitance. Once it is found, the clock dynamic power model for clock, registers, buffers, allocators, arbiters and links can be deduced. As an example the link load capacitance is = + + where is the input capacitance of the following repeater, and are the ground and coupling capacitance of the wire. The load capacitance values for various components of the routers can be obtained from components datasheets. We use the total leakage current value to compute leakage power. (i, s)= W(i, s) ( (i, s) (i, s)) . and ORION defines this current as are the sub-threshold and the gate leakage current per unit of transistor width for a specific technology.(i, s) is the effective transistor width of component i at input state s. For each i and s, ' and were obtained through simulations using models at 65 nm technology. A layout model for logic gates is used to calculate router and link area. Router area is estimated by summing the areas of all its building blocks and taking into account the area between blocks. To be able to compute the area of a block, it is first decomposed into logic gates. The area for buffers is computed by considering the word line and bit line lengths of the FIFO (First In, First Out) buffer: Area= . where =F( +2( + ) ) and =B( +( + ) ) .B is the buffer size, in flits. F is the flit size, in bits. The memory cell width and height is given by and ( accounts for wire spacing). The number of read and respectively write ports are noted with Pr and Pw. Link area is computed using the following formula:!"#$ the wire width and % is the spacing between wires. = F( +% ) % where is We have integrated ORION2.0 libraries into TriBASim.The parameters for ORION are kept in the SIM_port.h configuration file. Most of the parameters have been kept to their defaults except for those specified by TriBASim at simulation time. For example our simulations are run for NoCs at 90 nm technology. The NoC clock frequency, flit and buffer size are set by TriBASim .The rest of the parameters are tightly related to our TriBA NoC router architecture. These are the number of input and output ports and the number of virtual channels. Fig[7] shows a UML diagram of how ORION is integrated within TriBASim. 29 International Journal of Mobile Network Communications & Telematics ( IJMNCT) Vol. 4, No.6,December 2014 Fig[7] ORION integration within triBASim Every time that a flit is routed and each time a flit goes through a link TriBASim makes a call to ORION. Dynamic and leakage power needed to route and transmit the flit is then computed. The measured power values are summed and stored in dynamicPower and leakagePower data members. We keep track of the number of flits whose power has been computed in the filtCount data member variable.This information is enough to compute the average power consumed by all routers and links in the simulated TriBA NoC network. To compute the power consumed by the entire network simulated by TriBASim we use a method from the TriBATopology class.The method totalTriBANoCPower() returns the total power consumed by our NoC.This method simply carries out a summation of the dynamic and leakage power.The area for all routers and channels in the network is calculated in a similar way.totalTriBANocArea() computes the area for the entire NoC.With the power consumed by the NoC at our fingertips we can compute the Energy consumed by our NoC simply by multiplying Power by the simulation time. 7. CASE STUDIES In this section we show the results of the simulations we run using TriBASim.The simulator keeps track of each flit and packet that is injected into the NoC. We rely on ORION for power and area computations. We show that TriBASim can be used to give the user a deeper insight into the mechanics of how packets and flits are transmitted into the TriBA NoC by logging the path followed by packets form source to destination. TriBA networks of different orders (3 nodes, 9nodes and 27 nodes) are compared in in terms of performance when submitted to various throughputs. We also study the performance of a TriBA NoC of 27 nodes when submitted to different traffic patterns with the increased clock cycle for data flits. Finally we investigate the variations in performance when the input buffer channel size is varied. Performance is evaluated in terms of the average latency of packets.[27]Defines the latency of a network as the time required for a packet to traverse the network, from the time the head of the packet arrives at the input port to the time the tail of the packet departs the output port. TriBASim keeps track of maximum and minimum packet latencies. The average latency of the packets is 30 International Journal of Mobile Network Communications & Telematics ( IJMNCT) Vol. 4, No.6,December 2014 expressed as a function of packet injection probability. The first 1000 cycles of the simulation are warm-up cycles [27] and we injected packets for 10000 cycles. We only collected packets for the remaining 9000 cycles in our analysis. The simulations were run on a Intel quad-core at 2.66 GHz, 4 GB DRAM system with Linux(XUbuntu 14.04) installed. Fig[8] Packet tracing Simulation within TriBASim In Fig[8] we traced the path followed by a packet from source to destination logging port information on each intermediary node .Critical network information can be easily obtained by activating convenience methods on node and triplet classes .In Fig[9] we studied how average latency in the network varies per link throughput per number of nodes Results show that lower level triBA networks saturate earlier than their higher level counterparts. Fig[9] Delay-latency-node count analysis within TriBASim In the next experiment, we used different higher clock frequencies to inject data flits into the network than we did for the head flits. This was done with input channel buffers of 9 flits in size and packets of 8 flits in length. Flits were a few bytes wide. We carried out this experiment on different traffic patterns. The results are shown in Fig[10]. 31 International Journal of Mobile Network Communications & Telematics ( IJMNCT) Vol. 4, No.6,December 2014 (a)Adjusted Bit-Complement traffic (b)Bit reverse traffic ( c ) Uniform random traffic Fig[10] Variations in average packet latency as we increase the packet injection frequency for different traffic patterns. One immediately notices that the average latency drops significantly when data flits are sent much faster than head flits (The network performs much better).The average latency is slightly higher for the bit complement traffic pattern than it is for other patterns. This is because with the bit complement traffic pattern, each generated packet is injected into the NoC. This is not true for other traffic patterns we used because on a particular node, it is possible to generate a packet with the source and destination set to that nodes address; therefore it is not injected in the network. We ran the same simulations on a 9 node TriBA NoC. These ran approximately 6 times faster than they did for a 27 node TriBA NoC. The subject of our last experiment was studying the effect of the allocated buffering resources on the average latency of the network; in other words performance. Uniform random traffic was used for 10000 cycles with 1000 cycles for warm-up. At every cycle, a flit may be sent into the network with a given probability of injection. Fig [11] shows the results. We used 9 flits wide packets, and the size of the input channels was varied uniformly, from 2 up to 8 flits. It can be seen that the more buffering resources we provide the better our NoC performs. Also one should notice that the effect of increasing buffering resources becomes more important with increased numbers of injected packets. 32 International Journal of Mobile Network Communications & Telematics ( IJMNCT) Vol. 4, No.6,December 2014 Fig[11] Average packet latency vs input buffer size. 8. FUTURE WORK TriBASim can already run the common chores that Network On Chip simulators are supposed to run .We hope to add support for multiple routing algorithms other than DDRA .The simulations we have run are based on random traffic models .We hope to delve into studying the characteristics of the traffics patters for our in-house SoCs and incorporate them in future versions. 9. CONCLUSIONS A new simulator for the Triplet Based NoC architecture has been suggested .We went through a broad overview of TriBA and displayed its basic characteristics and state of the art .Furthermore, we described the details for the design of our simulator and ended the paper with practical uses showing its usefulness to the triBA researcher and anyone interested in NoCs in general. REFERENCES [1] [2] [3] [4] [5] [6] [7] [8] [9] J I Wei2xing , QIAO Bao2jun , A New Non Von Neumann Architecture TriBA ,SHI Feng , L IU Bin , Transactions of Beijing Institute of Technology , Vol .26 No.10 Oct 2006 . TriBA Interconnection Topology Structure and Its Performance Analysis ,LIU Cai-xia, SHI Feng, QIAO Bao-jun, HAROON Ur Rashid, SONG Hong ,Journal of Beijing Institute of Technology ,Computer Engineering , Vol .36 No .15. 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Towles, Principles and Practices of Interconnection Networks, 1st ed. Morgan Kaufmann, 2004. 34 International Journal of Mobile Network Communications & Telematics ( IJMNCT) Vol. 4, No.6,December 2014 Authors: Daniel GAKWAYA A student at BEIJING INSTITUTE OF TECHNOLOGY currently pursuing his master’s degree,School of Computer Science ,Department of Advanced Embedded Computing . His research interests lie in Network Optimizations and Computer Graphics. Gao Yu Jin Associate Professor, BEIJING INSTITUTE OF TECHNOLOGY ,School of Computer Science , Department of Advanced Embedded Computing,His research interest include Embedded Multicore Processors. Jean Claude GOMBANIRO Master’s student at the School of Computer Science Of BEIJING INSTITUTE OF TECHNOLOGY , Department of Natural Languages Processing His research interests lie in Big Data Processing and Language recognitionAlgorithms . Jean Pierre NIYIGENA Master’s student at the School of Computer Science Of BEIJING INSTITUTE OF TECHNOLOGY , Department of Data Networks .His research interests lie in Geolocation Algorithms . 35