Systemc

Abstract
    We   present     work   in   the   domain   of   Virtual  
Platforms,   based   on   the   QEMU   emulator.   Virtual
Platforms allow software and drivers to be developed in  
parallel with the development of hardware, avoiding re­
design and long delay times  in SW development.  This  
work allows designers to plug SystemC models into the  
virtual platforms that QEMU offers (We focused on two  
of   the   available   platforms:   x86   PC   and   ARM's  
VersatilePB)     The   new   aspect   of   this   work   is   the  
technology   we   have   developed   to   connect   between  
QEMU   and   SystemC.   We   have   developed   a   virtual  
device   to   link   QEMU   and   SystemC,   and   a   bridge   to  
manage the OSCI SystemC­2.2.0 simulator. This bridge  
accomplish   the   task   of   synchronize   efficiency   the   two  
simulators, using a strategy of freeze­and­update on the  
SystemC   simulator   to   achieve   a   good   performance.  
Connection with the SystemC device is done using TLM­
2.0 sockets and makes use of DMI. Also we present the  
same emulator wrapped for a TLM­2.0 Initiator module.  
With this wrapper, this QEMU module can be used in a  
standard   SystemC   simulation   environment   as   an  
Initiator that accesses some (but not necessary all) of its  
system devices through a standard TLM­2.0 socket.

The current trend in embedded system design is towards an increasing percentage of the embedded SW development cost of the total embedded system design costs. There is a clear need of reducing SW generation cost while maintaining reliability and design quality. SystemC represents a step forward in ensuring these goals. In this chapter, the application of SystemC to embedded SW generation is discussed. The state of art of the existing techniques for SW generation is analyzed and their advantages and drawbacks presented. In addition, methods for systematic embedded software generation which reduce the software generation cost in a platform based HW/SW co-design methodology for embedded systems based on SystemC is presented. SystemC supports a single-source approach, that is, the use of the same code for system level specification and verification, and, after HW/SW partitioning, for HW/SW co-simulation and embedded SW generation.

Abstract—With semiconductor industry trend of “smaller the better”, from an idea to a final product, more innovation on product portfolio and yet remaining competitive and profitable are few criteria which are culminating into pressure and need for more and more innovation for CAD flow, process management and project execution cycle. Project schedules are very tight and to achieve first silicon success is key for projects. This necessitates quicker verification with better coverage matrix. Quicker Verification requires early development of the verification environment with wider test vectors without waiting for RTL to be available. DATA BUS UVC (Driver)

In this paper, we present our approach for automatic SystemC code generation from UML models at early stages of Systems On Chip (SOC) design. A particularity of our proposed approach is the fact that SystemC code generation process is performed through two levels of abstraction. In the first level, we use UML hierarchic sequence diagrams to generate a SystemC code that targets algorithmic space exploration and simulation. In the second level of abstraction, messages that occur in sequence diagrams are implemented using UML activity diagrams whose actions are expressed in the C++ Action Language (AL) included in the Rhapsody environment from which a full SystemC code is generated for both simulation and synthesis.

In this paper, we present our approach for automatic SystemC code generation from UML models at early stages of Systems On Chip (SOC) design. A particularity of our proposed approach is the fact that SystemC code generation process is performed through two levels of abstraction. In the first level, we use UML hierarchic sequence diagrams to generate a SystemC code that targets algorithmic space exploration and simulation. In the second level of abstraction, messages that occur in sequence diagrams are implemented using UML activity diagrams whose actions are expressed in the C++ Action Language (AL) included in the Rhapsody environment from which a full SystemC code is generated for both simulation and synthesis. General Terms Systems On Chip, System Modeling

En este artículo se presenta un proceso para la transformación de sistemas basados en hardware/software descritos mediante UML a código esqueleto SystemC. Se introduce la herramienta UML2SC, basada en librerías de Java, mediante la cual se puede realizar este proceso de transformación. La herramienta UML2SC, permite obtener código esqueleto SystemC a partir de modelos descritos en UML mediante los diagramas de clases y estructura compuesta. Los resultados de la utilización de esta herramienta se presentan mediante un ejemplo, el cual describe el modelo funcional de una CPU RISC de 16 bits.

System-Level Modeling using system-level languages like SystemC or SystemVerilog is gaining more and more popularity. They are supposed to provide the garantee of critical functional properties about the interaction between concurrent processes like determinism or liveness up to a basic unit, the delta-cycle. Additionnally to this functional correctness, system level models should also provide valuable information about important non-functional properties like time constraints. Since timing properties (execution times, delays, periods, etc.) are especially important in performance verification of multiprocessing real-time embedded systems [1], we propose a formal model based on SystemC waiting-state automata [2] that conforms to the SystemC scheduler up to delta-cycles (1) and that also conforms to the provided time constraints (2). 1.

Study of Network-on-Chip (NoC) systems requires simulators capable of handling their unique characteristics. Toward this objective, a set of simulation models are developed based on NoC first principles and the DEVS framework. The components necessary to build simulation models for NoC are developed using Parallel DEVS and implemented in NoC-DEVS which extends the generalpurpose DEVS-Suite simulator. An example mesh-based NoC model synthesized from processing elements, network interfaces, switches, and links is experimented with and analyzed. The same example is also studied in Noxim which is an extension of the SystemC simulator. The NoC-DEVS simulator is evaluated and compared against the Noxim simulator. The comparison focuses on their modeling capabilities and considers delay and throughput performance metrics as well as capabilities expected from advanced simulation tools. Related and future research directions are briefly discussed. 1

Abstract Among the many factors contributing to the industrial" productivity gap", the use of inappropriate abstraction levels for design entry, nonexistence of a standard high-level design methodology, modeling frameworks & tools, and insufficient methodologies and tools for hardware & software co-design are often blamed by industry experts. In our effort to address these specific issues, our research focuses on designing an appropriate framework that allows designers to express their specification of a complex hardware-software ...

TriBA(Triplet Based Architecture) is a Network on Chip processor(NoC) architecture which merges the core philosophy of Object Oriented Design with the hardware design of multicore processors[1].We present TriBASim in this paper, a NoC simulator specifically designed for TriBA.In TriBA ,nodes are connected in recursive triplets .TriBA network topology performance analysis have been carried out from different perspectives [2] and routing algorithms have been developed [3][4] but the architecture still lacks a simulator that the researcher can use to run simple and fast behavioural analysis on the architecture based on common parameters in the Network On Chip arena. TriBASim is introduced in this paper ,a simulator for TriBA ,based on systemc[6] .TriBASim will lessen the burden on researchers on TriBA ,by giving them something to just plug in desired parameters and have nodes and topology set up ready for analysis.

The current trend in embedded system design is towards an increasing percentage of the embedded SW development cost of the total embedded system design costs. There is a clear need of reducing SW generation cost while maintaining reliability and design quality. SystemC represents a step forward in ensuring these goals. In this chapter, the application of SystemC to embedded SW generation is discussed. The state of art of the existing techniques for SW generation is analyzed and their advantages and drawbacks presented. In addition, methods for systematic embedded software generation which reduce the software generation cost in a platform based HW/SW co-design methodology for embedded systems based on SystemC is presented. SystemC supports a single-source approach, that is, the use of the same code for system level specification and verification, and, after HW/SW partitioning, for HW/SW co-simulation and embedded SW generation.

Abstract Bluespec's rule-based model of computation (MoC) for hardware concurrency has gained attention for several reasons. From its basis in term rewriting systems, rules have the property of atomicity, which improves correctness by construction, particularly in large-scale concurrency with finegrained, dynamic resource sharing (typical in complex hardware). Rule-based interface methods extend atomicity across module boundaries, have a natural transactional reading, and precisely and formally characterize resource-sharing ...

The language SystemC [1] has proven itself to be an inevitable standard when virtual
prototyping is used during the development of embedded systems. Besides methodologies
as platform-based design SystemC was clearly designed in order to enable component-
based design.