Nesrine HARRATH

ABSTRACT The SystemC waiting-state automaton is a compositional formal model for verifying properties of SystemC at the transaction level within a delta-cycle: the smallest simulation unit time in SystemC. In this paper, we first propose how to extract automata for SystemC components where we distinguish between threads and methods in SystemC. Then, we propose an approach based on a combination of symbolic execution and computing fixed points via predicate abstraction to infer relations between predicates generated during symbolic execution.

System-Level Modeling using system-level languages like SystemC or SystemVerilog is gaining more and more popularity. They are supposed to provide the garantee of critical functional properties about the interaction between concurrent processes like determinism or liveness up to a basic unit, the delta-cycle. Additionnally to this functional correctness, system level models should also provide valuable information about important non-functional properties like time constraints. Since timing properties (execution times, delays, periods, etc.) are especially important in performance verification of multiprocessing real-time embedded systems [1], we propose a formal model based on SystemC waiting-state automata [2] that conforms to the SystemC scheduler up to delta-cycles (1) and that also conforms to the provided time constraints (2). 1.

Abstract--In this paper we present a model able to serve in validating either functional or non-functional properties of the hard real time systems. We firstly introduce the timed SystemC waiting state automata (TWSA) that will serve in the modeling of the hardware. TWSA guarantees both critical functional properties about the interactions between concurrent processes and non-functional properties especially the time constraints. Timing properties need to be carefully addressed as they are important in performance and safety verification of real time embedded systems. A method which starts from a SystemC code and ultimately provides a tight execution time upper bound of the code running on the modeled system is also presented.

Embedded systems are increasingly integrated into existing real-time applications. They are usually composed of deeply integrated but heterogeneous hardware and software components. These components are developed under strict constraints. Accordingly, the work of design engineers became more tricky and challenging. To meet the high quality standards in nowadays embedded systems and to satisfy the rising industrial demands, the automatization of the developing process of those systems is gaining more and more importance. A major challenge is to develop an automated approach that can be used for the integrated verification and validation of complex and heterogeneous HW/SW systems.In this thesis, we propose a new compositional approach to model and verify hardware and software written in SystemC language. This approach is based on the SystemC Waiting State Automata (WSA). The SystemC Waiting State Automata are used to model the abstract behavior of hardware or software systems describe...

Les systemes embarques sont de plus en plus integres dans les applications temps reel actuelles. Ils sont generalement constitues de composants materiels et logiciels profondement Integres mais heterogenes. Ces composants sont developpes sous des contraintes tres strictes. En consequence, le travail des ingenieurs de conception est devenu plus difficile. Pour repondre aux normes de haute qualite dans les systemes embarques de nos jours et pour satisfaire aux besoins quotidiens de l'industrie, l'automatisation du processus de developpement de ces systemes prend de plus en plus d'ampleur. Un defi majeur est de developper une approche automatisee qui peut etre utilisee pour la verification integree et la validation de systemes complexes et heterogenes.Dans le cadre de cette these, nous proposons une nouvelle approche compositionnelle pour la modelisation et la verification des systemes complexes decrits en langage SystemC. Cette approche est basee sur le modele des SystemC ...

Abstract--In this paper we present a model able to serve in validating either functional or non-functional properties of the hard real time systems. We firstly introduce the timed SystemC waiting state automata (TWSA) that will serve in the modeling of the hardware. TWSA ...

SystemC is becoming a de facto standard for the system level description of system–on–chip. However, most formal verification techniques used for verifying hardware components use a very low level design, usually a netlist or RTL, but time–to–market requirements ...

Abstract System-Level Modeling using system-level languages like SystemC or SystemVerilog is gaining more and more popularity. They are supposed to provide the garantee of critical functional properties about the interaction between concurrent ...