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The LM710 series are high-speed voltage comparators intended for use as an accuratee low-level digital level sensor or as a replacement for operational amplifiers in comparator applications where speed is of prime importancee The circuit has a differential input and a single-ended outputt with saturated output levels compatible with practically all types of integrated logicc The device is built on a single silicon chip which insures low offset and thermal driftt The use of a minimum number of stages along with minority-carrier lifetime control (gold doping) makes the circuit much faster than operational amplifiers in saturating comparator applicationss In factt the low stray and wiring capacitances that can be realized with monolithic construction make the device difficult to duplicate with discrete components operating at equivalent power levelss The LM710 series are useful as pulse height discriminatorss voltage comparators in high-speed AAD converters or goo no-go detectors in automatic test equipmentt They also have applications in digital systems as an adjustable-threshold line receiver or an interface between logic typess In addi-tionn the low cost of the units suggests them for applications replacing relatively simple discrete component circuitryy
International Journal of Innovative Technology and Exploring Engineering, 2019
A comparator has been proposed using the dynamic bias concept. The proposed comparator operates on low power with minimum delay. It describes the comparison of power and delay characteristics between the dynamic bias model, elzakker circuit and two stage dynamic comparator circuits. This is achieved by enhancing the total effective transconductance with in the circuit. All these circuits were simulated at 130nm technology with a supply voltage of 1.2V.
Highlights in Science, Engineering and Technology, 2022
Comparator is one of the fundamental building blocks in most analog to digital converters. Many high speed analog to digital converters such as flash analog to digital converter require high speed and low power comparators. A new double tail comparator is designed, where the circuit of a conventional double tail comparator is modified for low power and fast operation even in small supply voltages. Without complicating the design and by adding few transistors the positive feedback during the regeneration is strengthened which results in remarkably reduced delay time. Post layout simulation results in a 0.18µm technology confirm the analysis results. It is shown that in the switching transistors using dynamic comparator, both the power consumption and delay time are significantly reduced. Power consumption of conventional double tail comparator is 12µW in 0.8v and power is reduced to 9.5μW in double tail comparator using switching transistorswith the same supply voltage.
2013 21st Iranian Conference on Electrical Engineering (ICEE), 2013
Comparator is an important element in many Data converter circuits, Signal processing systems, such as telecommunication interfaces and in the sensory circuits. Also comparators are the basic building elements for designing modern analog and mixed signal systems. Many high speed analog to digital converters, such as Flash ADCs, require low power, high speed comparators with small chip area. In this paper, a novel new double tail comparator which consumes very less power and can operate at high speeds when compared to the existing double tail comparators is proposed and simulated. Because of its high speed and low power consumption it can be used in high speed analog to digital converters, such as Flash ADCs requiring low power, high speed comparators. The designed double tail comparator is simulated using Cadence virtuoso tool with 180nm technology. From the simulation results, it is observed that in the proposed double tail comparator both the power consumption and delay time are significantly reduced.
A new CMOS dynamic comparator using dual input single output differential amplifier as latch stage suitable for high speed analog - to - digital converters with High Speed, low power dissipation and immune to. Back - to - back inverter in the latch stage is replaced with dual - input single output differential amplifier. This topology completely removes the noise that is present in the input. The stru cture shows lower power dissipation and higher speed than the conventional comparators. The circuit is simulated with 1V DC supply voltage and 250 MHz clock frequency. The proposed topology is based on two cross coupled differential pairs positive feedback and switchable current sourceces, has a lower power dissipation, higher speed, less area, and it is shown to be very robust against transistor mismatch, noise immunity.
International Journal of Energy Technology and Management, 2017
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