Spectrum-based BIST in complex SOCs

Spectrum-Based BIST in Complex SOCs Ganapathy Kasturirangan Michael S. Hsiaoy Intel Corporation Bradley Dept. ECE, Virginia Tech Hillsboro, OR 97124 Blacksburg, VA 24061 ABSTRACT test lengths are obtained at the expense of area overhead required to store the seeds. It is also seen that the omplexity of omputation of the seeds [4℄ rapidly in reases with the number of primary inputs. Use of an embedded pro essor on an SOC to generate patterns to test the rest of the hip has been proposed [8, 11, 6℄. The embedded pro essor eases the need of additional hardware, su h as LFSRs, to test the other embedded ores. A spe trum-based BIST te hnique for SOC's with an embedded pro essor was proposed in [6℄, where dire t a essibility of all inputs of every ore is assumed to be available from the embedded pro essor. Ve tors are generated using ir uit-spe i spe tral information in the form of one or more Hadamard oeÆ ients, extra ted from ompa ted test sequen es. The disadvantage of this method is the limitation of dire t paths from the pro essor to every embedded ore. 1. In this work, no dire t or bypass paths from the primary inputs exist for internal ores; further, no internal s ans exist for any sequential ore. In su h a s enario, we rst ompute spe tral oeÆ ients for ea h embedded ore. Next, we analyze the relationship between the output hara teristi s of one ore and the input hara teristi s of the immediate su essor ore. Similar hara teristi s indi ate that the su essor ore may be tested dire tly from the pro essor without dire t a ess. The orresponding spe tral data enables the pro essor to su essfully test the su essor ore. Although spe tral te hniques have shown to out-perform onventional LFSR in BIST when the ore is dire tly tested by the TPG [6℄, it is un lear whether spe trum-testing is still superior when as aded ores are onsidered. The results for this spe trum-based BIST showed that signi antly more faults an be dete ted than by the onventional weighted random BIST te hnique. This new analysis will enable SOC integrater to determine a priori how testable an embedded ore is, if testability enhan ement is needed, and if spe trumbased testing would enhan e the fault overage. We present a spe tral built-in-self-test (BIST) for a systemon-a- hip (SOC) environment. Test ve tors are generated using the spe tral properties of the embedded ores. Beause some embedded ores may not have dire t onne tions to the embedded TPG, it would be ne essary to test them via other ores. As a result, testing su h ( as aded) ores requires onsiderations on the spe tral hara teristi s of the prede essor and su essor ores. Mat hing spe tral hara teristi s between the outputs of the prede essor ore and dominant inputs of the su essor ore allows the su essor ore to be more testable. Experimental results for the spe tral BIST showed that signi antly more faults an be dete ted using spe tral patterns than by onventional weighted random BIST te hnique. INTRODUCTION Te hnology advan es in terms of gate density and in reased lo king speeds are moving the trend towards \System-OnA-Chip" design. The in reased omplexities by putting a number of ores on one hip, thus limiting their a essibility, makes the testing of these ores very diÆ ult. Also testing equipment is falling short on keeping pa e with the growing speeds of ir uits, thus preventing at speed test and measurement. Built-In-Self-Test (BIST) has emerged as a promising solution to this problem. An e e tive test pattern generator for BIST should be a ir uit that has an area eÆ ient implementation and is apable to generating test sequen es that a hieve high fault overage. The main omponents of a onventional BIST system are a linear feedba k shift register (LFSR), a response ompa tor and a signature omparator [1℄. The LFSR generates pseudo-random test patterns, the response ompa tor ompa ts the responses into a signature and the signature omparator ompares the signature to a fault-free referen e value. BIST based on su h random patterns is found to have low hardware osts, but with large test sets [1℄. Moreover, the quality of the LFSR-generated test set depends on the ir uit-under-test. Weighted random patterns have been found to yield better results. Weighting the pseudorandom patterns is done using ounter-based s hemes [10, 9℄ or performing bit- xing [2℄. These te hniques have an area and delay overhead. To over ome these disadvantages, LFSRs with good seeds and feedba k polynomials were designed [7, 3℄. But here again, a eptable fault overages and  Formerly with Dept. of ECE, Rutgers University, Pis ataway, NJ 08854 y Supported in part by an NSF Career Award, under ontra t CCR-0196470 and a grant by NJ Commission on S ien e and Te hnology. 0-7695-1570-3/02 $17.00 2002 IEEE 111 The remainder of this paper is organized as follows: Se tion 2 des ribes the omputation of spe tral hara teristi s for as aded ores, Se tion 3 des ribes the BIST approa h, Se tion 4 explains the experimental results, and Se tion 5 on ludes this paper. 2. COMPUTING SPECTRUM IN CASCADED CORES 2.1 Frequency Decomposition of Bit Streams To obtain the spe tral hara teristi s of a given signal, a lean representation for the signal is desired. Compa tion is used to lter the noise from the test sequen e, leaving a Pro . IEEE VLSI Test Symposium, April 2002 leaner signal. In order to apture the spe tral hara teristi s of the ompa ted test set, the pro ess of spe tral de omposition of the signal using Hadamard matrix is performed [5℄. Based on the fa t that the rows and/or olumns of the Hadamard Matrix span the ve tor spa e, any bit stream an be represented as a linear ombination of the olumns of the Hadamard Matrix. Be ause Hadamard Matri es have only 1's and 1's, matrix multipli ation an essentially be omputed by additions and subtra tions, saving pro essing time. Also, the inverse transform of a Hadamard matrix is the same as the forward transform, making re onstru tion straight forward. Central Processing Unit PI’s Core 1 1 0 1 1 1 0 1 0 1 0 0 0 1 0 0 0 Aa Bb C 0 1 0 1 1 0 0 1 1 1 1 1 1 1 1 1 =) 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 For ea h input onsider m(= 2n ) bit stream. Multiply Hn with the bit stream of ea h input to obtain its oeÆ ient ve tor. In our example m = 23 = 8. Considering input C , we obtain the oeÆ ient ve tor V Coeff as: 6 6 6 6 6 6 4 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 32 76 76 76 76 76 76 54 1 1 1 1 1 1 1 1 3 2 7 6 7 6 7 6 7=6 7 6 7 6 5 4 4 4 4 4 0 0 0 0 Core 3 Be ause ea h ore is viewed as a bla k-box, testing is ondu ted by applying waveforms orresponding to the spe tral hara teristi s of the target ore that an maximize fault overage. To see if it is possible to e e tively test Core 2 via Core 1, we rst apply the pro edures des ribed in previous subse tions to ompute the output spe trum of Core 1 and input spe trum of the Core 2. If the spe tra are similar, testing Core 2 dire tly from the embedded CPU via Core 1 would be plausible. On the ontrary, if the spe tra vary widely, generating e e tive ve tors from the CPU to Core 2 that exhibit desired spe tral hara teristi s would be diÆult. Two spe tra are similar when the inner (dot) produ t of the two oeÆ ient ve tors is greater than some threshold. Step 2: 2 PI’s sequen e dire tly from the embedded CPU su h that high fault overages for ores 2 and 3 an still be a hieved. All ores an be either ombinational or sequential. Dd 1 1 1 1 1 1 1 1 Core 2 Figure 1: Cas aded Cores in a SOC Environment. Pro edure FreqDe omp Step 1: Start from ve tor v0 and pi k `n' ve tors. Repla e ea h logi `0' with a ` 1': 1 1 1 1 1 1 1 1 PI’s i (i+1) to PO’s n The pro ess of extra ting spe tral hara teristi s is illustrated with the following example of the test set, V , omposed of 4-input ve tors: f1110, 1001, 1100, 1101, 1111, 1000, 1100, 1001g. A B C D 1 PO’s to Ea h input of Core 2 needs not spe trally mat h the orresponding output of Core 1. This is be ause dete tion of faults in Core 2 may not depend on ertain inputs. We de ne sensitivity index of ea h primary input of a given ore to be the drop in fault overage when the orresponding primary input value is perturbed in the ompa ted test set. For example, in ir uit s400, we rst extra ted the input spe trum, then we ompute the sensitivity index for ea h primary input with the nal ompa ted test set obtained, the sensitivity results are shown in Table 1. In this table, 3 7 7 7 7 7 7 5 Set all oeÆ ients whose absolute value is less than the uto to 0 and others to 1. In our example, let us assume a uto of 4, so V Coeff would thus be ome  T 1 1 1 1 0 0 0 0 . This says that the rst 4 frequen y omponents of the Hadamard spa e are most dominant in bit-stream C . Step 3: Table 1: Changes in dete ted faults by perturbing input bits of s400. No. of bits perturbed Input 1 only Input 2 only Input 3 only We an ompute the output spe tral oeÆ ients of the target ore by rst logi simulating the nal ompa ted test set V , and analyze the spe trum of output ve tors. 0 10 50 100 Number of faults dete 384 375 378 373 384 366 369 359 384 310 100 57 500 ted 371 362 51 we perturbed ea h of the three primary inputs 10, 50, 100 and 500 times in the given ( ompa ted) test set. As shown in the table, perturbing inputs #1 or #2 does not signi antly de rease the fault overage. However, the fault overage is very sensitive to primary input 3. When we perturbed primary input #3 50 times, the fault overage drops from 384 to 100. Thus, the sensitivity index for the three inputs by perturbing 50 bit positions is omputed as 6/384=0.01, 15/384=0.04, and 284/384=0.74, respe tively. 2.2 Cascaded Cores In [6℄, dire t onne tion from the embedded CPU to every ore was assumed to be available. Even for an SOC with a few ores, this would result in a high area overhead. We do not have this restri tion in this paper. Figure 1 illustrates a s enario where testing ores 2 and 3 requires going through ore 1. We test ores 2 and 3 by generating a ve tor 112 From this experiment we an see that ontrolling input #3 of s400 is riti al in a hieving a high fault overage. In other words, whenever s400 is as aded after another ore Cp , in order to su essfully test s400 via the prede essor ore Cp , spe tral hara teristi s for input #3 of s400 and orresponding output of Cp will be essential. for bases 0 (1111 1111 1111 1111), bases 1 (1010 1010 1010 1010) and bases 2 (1100 1100 1100 1100), for outputs 1, 2 and 3 of s382 and the inputs of the stand-alone s400, respe tively. The dotted lines show the spe tral hara teristi s of the 3 outputs of s382, while the solid lines show the spe tral hara teristi s of ea h input of s400. 3. From Figures 2 and 4, we see that the spe tral hara teristi s of all three outputs of s382 do not mat h the hara teristi s of the three inputs of s400, espe ially in the sensitive input #3 of s400. In fa t, if we attempt to test s400 through s382 in this fashion, low overage (312 dete ted faults) is obtained. Suppose the two ores are onne ted in a di erent way: onne ting outputs 2, 3 and 4 of s382 to the three inputs of s400. The Hadamard oeÆ ients omputed for this on guration also reveals that bases 0 and 2 are more dominant. Figures 5 - 7 show the spe tral plots for the signals involved. In this ase, we see that the spe tral hara teristi s of inputs 1 and 3 of s400 mat h more losely to the spe tral hara teristi s of outputs 2 and 4 of s382, ex ept for a few sporadi noises. Sin e input #3 of s400 is the only sensitive input, the mismat h of the spe trum in the se ond input an be tolerated. We would expe t high overage to be obtained for s400 in this on guration. Indeed, for this new on guration, we dete ted 371 faults for s400. BIST FOR CASCADED CORES Given a as aded ore1- ore2 on guration, an attempt to generate ve tors dire tly from the embedded CPU, through ore1, to ore2 is made. We use a similar spe trum extra tion pro edure for ore2. However, in this ase, we must onsider the pre eding ore in the omputation. We explain this pro edure with the following example: Table 2: Modi ed ompa tion. v0 v1 v2 v3 v4 v5 v6 v7 v8 v9 v10 u0 u1 u2 u3 u4 u5 u6 u7 u8 u9 u10 f1 f2 f3 f5 f7 f6 f8 f4 The ve tor sequen e V = fv0 ; v1 ; ::::; v11 g shown in Table 2 is applied to the primary inputs of Core 1. Ve tor sequen e U = fu0 ; u1 ; ::::; u11 g is the output obtained at Core 1 orresponding to V . In turn, U is used to fault simulate Core 2. Faults dete ted by U in ore 2 by are shown underneath U in the table. For example, faults f5 and f6 are dete ted by ve tor u7 ( orresponding to ve tor v7 at the input of ore 1) at time unit t7 . If we simply ompa t U to obtain U , the ompa ted set U may not be attainable at the outputs of ore 1 dire tly from the CPU. Therefore, ompa tion must be performed with respe t to V , so that we an make sure that the ompa ted V is able to produ e the ne essary U that an still dete t all faults in ore 2. This is a hieved by embedding a logi simulation for ore 1 as part of the ompa tion routine. Now, the new set of spe tral oeÆ ients for ore 2 observed from the embedded CPU an be obtained readily. 4. To justify this further, we repla ed s382 with a di erent prede essor ore, s1423. We rst onne t outputs 1, 2 and 3 of s1423 to inputs of s400. Figures 8 - 10 show the orresponding spe tral hara teristi s. Sin e the spe tral hara teristi s do not mat h (espe ially for input#3 of s400), we do not expe t a high overage for s400 - only 70 faults were dete ted using this on guration. When we re on gure the onne tion by onne ting outputs 3, 4 and 5 of s1423 to s400 and re ompute the spe tral oeÆ ients, shown in Figures 11 - 13. These gures show that the spe tral properties of output #5 of s1423 are similar to that of input #3 of s400, and thus we expe t a high fault overage. Our ATPG is able to dete t 360 faults for this on guration, whi h is mu h higher than the previous 70 dete ted faults. EXPERIMENTAL RESULTS All experiments were ondu ted on an Ultra SPARC 10 with 256 MB of RAM. We onsider a sele tion of ISCAS 89 and ITC 99 ben hmark ir uits for onstru ting the SOC environment with as aded ores. Hadamard matrix of size 16 (H16 ) is used throughout. 4.2 BIST Results We as aded various ombinations of di erent ores taken from ISCAS89 and ITC99 ben hmark ir uits, and applied our spe tral BIST to test the se ond ore. No internal s an are onsidered in sequential ores. We ompared our results with one that uses weighted random (WR) approa h. In the WR approa h, the weights for the se ond ore obtained are adjusted so that they would be appli able when another ore pre edes it. The weights for ea h ore are obtained from the same ompa ted test sets. These weights are then used by the embedded CPU to generate ve tor sequen es. 4.1 Spectral Analysis of Cascaded Cores We rst omputed the spe tral oeÆ ients and sensitive inputs for ea h ore. For ea h as ading ombination, we ompared the orresponding oeÆ ients, for ea h of the 16 bases (16 be ause our experiments were ondu ted with the H16 matrix) of the ompa ted set of ve tors for various ore-1output to ore-2-input onne tions. For ea h input and/or output of a given ore, some frequen y omponents may be more dominant than others. For example, we observed the input spe trum of s400's primary inputs are most dominant in frequen ies represented by bases 0 and 2. Table 3 shows the results for both the weighted random and the spe tral te hnique. On e the spe tral oeÆ ients (or weights in weighted-random approa h) are obtained, 70,000 ve tors are generated from the CPU in both ases. For our experiments we sele ted s382, s400, s526 and b01rst as the 2nd ore, and the on gurations are set su h that the rst k output signals of the prede essor ore are onne ted to the k inputs of the su essor ore. The rst/pre eeding ores listed in olumn 1. Results for other on gurations are disussed in the next subse tion. Considering the on guration where s382 is the prede essor ore feeding s400 as the su essor ore, and the rst three outputs of s382 are onne ted to the three inputs of s400. Figures 2 - 4 show the orresponding Hadamard oeÆ ients 113 20 20 20 s400 input 2 s382−s400 output 2 of s382 s400 input 3 s382−s400 output 3 of s382 15 10 10 10 5 0 −5 5 0 −5 −10 −10 −15 −15 −20 0 50 100 150 200 −20 250 Hadamard coefficient value 15 Hadamard coefficient value Hadamard coefficient s400 input 1 s382−s400 output 1 of s382 15 5 0 −5 −10 −15 0 50 100 Vector number 150 200 −20 250 0 50 100 150 Vector number (a) PO 1 - PI 1 200 250 Vector number (b) PO 2 - PI 2 ( ) PO 3 - PI 3 Figure 2: s382(PO's 1-3) feeding s400, Basis 0. 4 4 s400 input 1 s382−s400 output 1 of s382 2 s400 input 2 s382−s400 output 2 of s382 s400 input 3 s382−s400 output 3 of s382 3 1.5 3 1 1 0 −1 2 Hadamard coefficient value Hadamard coefficient value Hadamard coefficient value 2 1 0 −2 0.5 0 −0.5 −1 −1 −3 −4 −1.5 0 50 100 150 200 −2 250 0 50 100 150 Vector number Vector number (a) PO 1 - PI 1 200 −2 250 0 50 100 150 200 250 Vector number (b) PO 2 - PI 2 ( ) PO 3 - PI 3 Figure 3: s382(PO's 1-3) feeding s400, Basis 1. 6 6 6 s400 input 2 s382−s400 output 2 of s382 s400 input 3 s382−s400 output 3 of s382 4 4 2 2 2 0 −2 −4 −6 Hadamard coefficient value 4 Hadamard coefficient value Hadamard coefficient value s400 input 1 s382−s400 output 1 of s382 0 −2 −4 0 50 100 150 200 −6 250 0 −2 −4 0 50 100 Vector number 150 200 −6 250 0 50 100 Vector number (a) PO 1 - PI 1 150 200 250 Vector number (b) PO 2 - PI 2 ( ) PO 3 - PI 3 Figure 4: s382(PO's 1-3) feeding s400, Basis 2. 20 20 20 s400 input 2 s382−s400 output 3 of s382 s400 input 3 s382−s400 output 4 of s382 15 10 10 10 5 0 −5 5 0 −5 −10 −10 −15 −15 −20 0 100 200 300 Vector number 400 500 −20 600 Hadamard coefficient value 15 Hadamard coefficient value Hadamard coefficient value s400 input 1 s382−s400 output 2 of s382 15 (a) PO 2 - PI 1 5 0 −5 −10 −15 0 100 200 300 Vector number 400 500 −20 600 0 100 (b) PO 3 - PI 2 200 300 Vector number 400 500 600 ( ) PO 4 - PI 3 Figure 5: s382(PO's 2-4) feeding s400, Basis 0. 4 6 s400 input 1 s382−s400 output 2 of s382 2 s400 input 2 s382−s400 output 3 of s382 3 s400 input 3 s382−s400 output 4 of s382 1.5 4 2 1 0 −1 Hadamard coefficient value Hadamard coefficient value Hadamard coefficient value 2 1 0 −2 0.5 0 −0.5 −4 −2 −1 −6 −3 −4 0 100 200 300 Vector number 400 500 −8 600 −1.5 0 (a) PO 2 - PI 1 100 200 300 Vector number 400 500 −2 600 0 100 (b) PO 3 - PI 2 200 300 Vector number 400 500 600 ( ) PO 4 - PI 3 Figure 6: s382(PO's 2-4) feeding s400, Basis 1. 6 6 6 s400 input 2 s382−s400 output 3 of s382 s400 input 3 s382−s400 output 4 of s382 4 2 2 2 0 −2 0 −2 −4 −4 −6 −6 0 100 200 300 Vector number 400 500 (a) PO 2 - PI 1 600 Hadamard coefficient value 4 Hadamard coefficient value Hadamard coefficient value s400 input 1 s382−s400 output 2 of s382 4 0 −2 −4 0 100 200 300 Vector number 400 500 (b) PO 3 - PI 2 600 −6 0 100 200 Figure 7: s382(PO's 2-4) feeding s400, Basis 2. 114 300 Vector number 400 500 ( ) PO 4 - PI 3 600 20 0 0 s400 input 2 s1423−s400 output 2 of s1423 s400 input 3 s1423−s400 output 3 of s1423 −2 10 −4 −4 5 0 −5 −6 −8 −10 −10 −12 −15 −14 −20 0 50 100 150 200 −16 250 Hadamard coefficient value −2 Hadamard coefficient value Hadamard coefficient value s400 input 1 s1423−s400 output 1 of s1423 15 −6 −8 −10 −12 −14 0 50 100 Vector number 150 200 −16 250 0 50 100 Vector number (a) PO 1 - PI 1 150 200 250 Vector number (b) PO 2 - PI 2 ( ) PO 3 - PI 3 Figure 8: s1423(PO's 1-3) feeding s400, Basis 0. 4 4 4 s400 input 1 s1423−s400 output 1 of s1423 s400 input 2 s1423−s400 output 2 of s1423 s400 input 3 s1423−s400 output 3 of s1423 3 3 3 2 1 0 −1 2 Hadamard coefficient value Hadamard coefficient value Hadamard coefficient value 2 1 0 −2 1 0 −1 −2 −1 −3 −4 −3 0 50 100 150 200 −2 250 0 50 100 150 Vector number 200 −4 250 0 50 100 Vector number (a) PO 1 - PI 1 150 200 250 Vector number (b) PO 2 - PI 2 ( ) PO 3 - PI 3 Figure 9: s1423(PO's 1-3) feeding s400, Basis 1. 6 6 4 s400 input 1 s1423−s400 output 1 of s1423 s400 input 3 s1423−s400 output 3 of s1423 s400 input 2 s1423−s400 output 2 of s1423 5 3.5 4 4 3 0 −2 Hadamard coefficient value Hadamard coefficient value Hadamard coefficient value 3 2 2.5 2 1.5 2 1 0 −1 1 −2 −4 0.5 −6 0 50 100 150 200 0 250 −3 0 50 100 150 Vector number 200 −4 250 0 50 100 (a) PO 1 - PI 1 150 200 250 Vector number Vector number (b) PO 2 - PI 2 ( ) PO 3 - PI 3 Figure 10: s1423(PO's 1-3) feeding s400, Basis 2. 20 20 0 s400 input 2 s1423−s400 output 4 of s1423 −2 10 10 −4 5 0 −5 5 0 −5 −10 −10 −15 −15 −20 0 50 100 150 200 250 300 Vector number 350 400 450 −20 500 Hadamard coefficient value 15 Hadamard coefficient value Hadamard Coefficient Value s400 input 1 s1423 − s400 output 3 of s1423 15 s400 input 3 s1423−s400 output 5 of s1423 −6 −8 −10 −12 −14 0 50 (a) PO 3 - PI 1 100 150 200 250 300 Vector number 350 400 450 −16 500 0 50 (b) PO 4 - PI 2 100 150 200 250 300 Vector number 350 400 450 500 ( ) PO 5 - PI 3 Figure 11: s1423(PO's 3-5) feeding s400, Basis 0. 4 s400 input 1 s1423−s400 output 3 of s1423 10 4 8 3 3 s400 input 3 s1423−s400 output 5 of s1423 6 s400 input 2 s1423−s400 output 4 of s1423 2 2 0 −1 Hadamard coefficient value Hadamard coefficient value Hadamard coefficient value 4 1 2 0 −2 1 0 −1 −4 −2 −2 −6 −3 −3 −8 −4 0 50 100 150 200 250 300 Vector number 350 400 450 −10 500 0 50 (a) PO 3 - PI 1 100 150 200 250 300 Vector number 350 400 450 −4 500 0 50 (b) PO 4 - PI 2 100 150 200 250 300 Vector number 350 400 450 500 ( ) PO 5 - PI 3 Figure 12: s1423(PO's 3-5) feeding s400, Basis 1. 6 8 6 s400 input 1 s1423−s400 output 3 of s1423 s400 input 2 s1423−s400 output 4 of s1423 s400 input 3 s1423−s400 output 5 of s1423 6 5 4 4 0 −2 Hadamard coefficient value 2 Hadamard coefficient value Hadamard coefficient value 4 2 0 −2 3 2 1 −4 0 −6 −1 −4 −6 0 50 100 150 200 250 300 Vector number 350 400 (a) PO 3 - PI 1 450 500 −8 0 50 100 150 200 250 300 Vector Number 350 400 (b) PO 4 - PI 2 450 500 −2 0 50 100 150 Figure 13: s1423(PO's 3-5) feeding s400, Basis 2. 115 200 250 300 Vector number 350 400 ( ) PO 5 - PI 3 450 500 1st Core s382 s1423 s1494 Table 4: Spe tral BIST results for di erent on gurations. 2nd Core s382 s400 s526 b01 new ombination OC NC OC NC OC NC OC NC 297 353 312 371 447 NA 61 NA outputs 2,3 and 4 used 64 340 70 360 405 NA 124 NA outputs 3,4 and 5 used 306 351 317 369 119 NA 21 71 outputs 11,12 and 13 used OC: Old ombination = outputs 1,2 and 3 are used NC: New ombination, as indi ated in rightmost olumn ) Table 3: Weighted-random vs. spe tral BIST. 1st Core s382 s400 s526 s713 s1423 s1494 b04 b08 b10 b11 b12 WR: an be a hieved by generating ve tors spe trally. Weightedrandom te hnique, on the other hand, fail to a hieve high fault overages even when the output spe trum of ore 1 and input spe trum of ore 2 mat h. This new analysis an also help SOC integrators determine a priori whether testability insertion is needed for a as aded ore. 2nd Core s382 s400 s526 b01 WR ST WR ST WR ST WR ST 23 297 20 312 0 447 0 61 0 362 354 381 39 439 5 48 0 351 0 369 39 381 5 48 357 361 376 381 44 401 22 49 47 64 49 70 285 405 117 124 276 306 290 317 65 119 21 21 69 308 70 359 260 434 95 116 210 291 219 302 109 362 4 76 357 363 375 383 91 362 53 53 288 296 310 313 392 426 40 87 0 298 0 315 0 393 5 41 Weighted Random ST: Spe tral Te hnique 6. REFERENCES [1℄ M. Abramovi i, M. A. Breuer, and A. D. Friedman. Digital System Testing and Testable Design. Computer S ien e Press, New York, NY, 1990. [2℄ S. B. Akers and W. Jansz. Test set embedding in a built-in-self-test environment. Pro . Intl Test Conf., pp. 257{263, 1989. [3℄ C. Fagot, O. .Gas uel, P. Girard, and C. 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IEEE Design Automation & Test in Europe Conf., pp. 204{208, Mar h 2001. g [6℄ A. S. Giani, S. Sheng, M. Hsiao, and V. D. Agrawal. Novel spe tral methods for built-in self-test in a system-on-a- hip environment. Pro . VLSI Test Symp., pp. 163{168, 2001. 4.3 Results for Other Configurations We ontinued our experiments with other output-input ombinations between ore 1 and ore 2. Depending on the sensitive inputs of the su essor ore, the fault overages may hange. For some ombinations, we observed notable improvements in the fault overage, reported in Table 4. For entries with NA, the old ombination was already the best. [7℄ S. Hellebrand, S. Tarni k, J. Rajski, and B. Courtois. Generation of ve tor patterns through reseeding of multiple polynomial linear feedba k shift registers. Pro . Intl Test Conf., pp. 120{129, 1992. [8℄ S. Hellebrand and H. J. Wunderli h. Mixed-mode BIST using embedded pro essors. Pro . Intl Test Conf., pp. 195{204, 1996. From Table 4, we see that the fault overages of s382 and s400 improved dramati ally in pairs (s1423, s382) and (s1423, s400), due to a better mat h of spe tral hara teristi s, while the fault overage for the ombination s1423,b01 is not reported, sin e the original on guration is already the best. f 5. g [9℄ D. Kagaris and S. Tragoudas. Generating deterministi unordered test patterns with ounter. Pro . VLSI Test Symp., pp. 374{379, 1996. CONCLUSIONS [10℄ F. Muradali, V. K. . Agarwal, and B. Nadeau-Dostie. A new pro edure for weighted random built-in-self-test. Pro . Intl Test Conf., pp. 660{669, 1990. We have presented a method to analyze and test embedded ores in an SOC environment, where dire t a ess paths do not exist from the embedded pro essor to some internal ores and no internal s an is available. We found that testing asaded ores depends on the output spe tral hara teristi s of ore 1 mat hing the spe tral hara teristi s of the sensitive inputs of ore 2. Experimental results showed that when the spe tral hara teristi s are similar, high fault overages [11℄ K. Rade ja, J. Rajski, and J. Tyszer. Arithmeti built-in-self-test for DSP ores. IEEE Trans. on 16(11):1358{1369, November 1997. 116 CAD,