Solid-State ElectronicsVol. 36, No. 10, pp. 1429-1432,1993 Printed in Great Britain.All rights reserved 0038-1101/93 $6.00+ 0.00 Copyright © 1993PergamonPress Ltd IMPACT IONIZATION RATE OF ELECTRONS FOR ACCURATE SIMULATION OF SUBSTRATE C U R R E N T IN SUBMICRON DEVICES SAMARSAHA, CHUNE-SINYEH and BHASKAgGADEPALLY National Semiconductor Corporation, 2900 Semiconductor Drive, Santa Clara, CA 95052-8090, U.S.A. (Received 12 January 1993; in revisedform 8 March 1993) Abstract--An expression for the impact ionization rate of electrons for accurate simulation of substrate current in submicron silicon devices and a methodology to optimize the empirical constants of the expression is reported. The optimized expression for the impact ionization rate of electrons fitting the measured substrate current in Lightly Doped Drain (LDD)-type n-channel silicon MOSFET devices of 0.8 micron CMOS technology is found to be: ~t, g 1.65 x l&exp[-(l.231 x 106/E)L23], where E is the electric field component along the current path. The simulated results obtained by this expression agree extremely well with the measured data for LDD type n-channel silicon MOSFETs of different channel lengths. 1. INTRODUCTION It is well-known that as feature sizes of MOSFET devices are scaled down to submicron range, the device performance is strongly affected by high field effects. In submicron devices, channel current in the high field region near the drain can cause low-level avalanche multiplication resulting in significant substrate current. These substrate Current generating devices could cause severe performance degradation of a VLSI circuit. Therefore, accurate prediction of substrate current is crucial in designing reliable MOSFET devices for VLSI applications. The Chynoweth[1] formula: ~t~= Ai e x p ( - BilE ) (1) is the most commonly implemented avalanche generation model for substrate current modeling in device simulators such as MEDICI[2]. Here E is the electric field component along the current path, and Ai and B~ are empirical fitting parameters. Over the years different researchers have reported different parameter couples (A, B~) for the Chynoweth expression to fit their experimental data[3]. The value of (A,., B~) reported by Van Overstraeten and De Man[4] is used in MEDICI for computation of substrate current in silicon devices and the default expression for impact ionization rate of electrons used is: u , = 7 . 0 3 x 105 e x p [ - (1.231 x 10e/E)] submicron devices the impact ionization takes place near the surface[5]. Therefore, the effect of surface impact ionization rate must be considered for an accurate prediction of substrate current in submicron devices. Secondly, the Chynoweth law is only valid for uniform electric field[9] where the carriers are assumed to attain a steady state equilibrium with the local electric field. In submicron MOSFET devices, the impact ionization process occurs in the presence of rapidly varying electric field within the device[6--9]. Due to this large spatial variation in electric field, carriers do not reach a steady state equilibrium with the local electric field. Therefore, the Chynoweth expression can lead to rather large errors in shortchannel MOSFET devices[9], and must be modified for accurate prediction of impact ionization and hence substrate current in submicron devices. In this paper, a modified Chynoweth expression for 10-3. 104" lO-S. ~ Simulated(OvenU-aetenet aL) i0. 7 .~ ~= 10 -8 i (cm-'). (2) 10 In advanced silicon devices, the simulated substrate current obtained by eqn (2) is usually one- to twoorders of magnitude higher than the measured value (Fig. 1)[5-8]. This discrepancy between the measured and the simulated values of substrate current is attributed to two main reasons. First of all, in ---o--- .9 GateOxide= 150A w = 4olun;L~= 0.64I ~ BackBias= O;DrainBias= 5 V . 0 Measured , 1 . . . 2 . . 3 , 4 . , . 5 Gate Voltage (V) Fig. I. Comparison of measured I,,b VS Yc,s characteristics with the simulated data obtained by default model in MEDICI for 40/~m/0.64/~m Lightly Doped Drain type n-channel MOSFET device. 1429 1430 SAMARSAHAet al. impact ionization of hot carriers with three empirical fitting parameters is presented. This expression accurately predicts substrate current in submicron devices with the existing local field implementation in MEDICI. A methodology to optimize the empirical parameters for n-channel devices is also described. Vs VG VD i N, 2. MODEL In recent years, several workers[7,8] have reported a modified Chynoweth expression: oti= Ai e x p [ - Bt/ear] (3) for accurate simulation of substrate current in submicron MOSFETs. Equation (3) is obtained by replacing the conventional local electric field, E, by an effective electric field denoted by Eel. This effective field accounts for the highly non-uniform electric field within the device along the current path. By using the existing local field approach in M E D I C I Saha et al.[7] have reported a power law relation between the local and the effective electric field for accurate simulation of substrate current in submicron n-channel MOSFET devices. Therefore, we can assume that the effective electric field is related to the conventional local electric field by the power law relation given by Een oc E", where r/is an empirical constant. Thus, the effective electric field can be written as: Eeer= ~cE", (4) where the constant of proportionality x and the constant r/account for t h e spatial variations in electric fields within submicron devices. From eqns (3) and (4) we can show that: ~tt = A i e x p [ - B~/xE"]. (5) Now, if we define B t / r = fiL eqn (5) can be expressed as: ~, = At e x p [ - (fit~E)"]. (6) Equation (6) with parameter set {Ai, fit, r/} is the modified Chynoweth law for accurate prediction of impact ionization rate and hence substrate current in submicron devices in terms of local field implementation in a device simulation program. Finally, the avalanche generation rate is determined by the expression [3]: G.+ = ~.lJ.IIq + ~plJpl/q, (7) where ~. and J. denote the impact ionization rate and the current density for electrons and ~p and Jp represents the corresponding pair for holes. Equation (7) is integrated over the simulation mesh into a device simulator to obtain the substrate current. 3. PROCEDURE The parameter set {A, fit, t/} for electrons was obtained by fitting the simulated substrate current with the measurement for L D D type n-channel MOSFET devices of 0.8 micron CMOS technology. Fig. 2. Two-dimensional cross~section of an ideal Lightly Doped Drain type n-channel MOSFET device. (Voltages applied to Drain, Gate, Source and Sabstrate are VD, Vo, Vs and V~, respectively). Figure 2 shows the cross-section of an ideal LDD type n-channel MOSFET device. In LDD structure, narrow, self-aligned n-regions are introduced between the channel and n + source-drain diffusions[10]. The device has four terminals: drain, gate, source and substrate, and the respective applied biases are VD, Vo, Vs and VB. The effective channel length (L,n) is defined as the spacing between the metallurgical junctions of the source and the drain plus the extra distance of surface conduction in the source-drain regions[11]. L,n was determined by using the method proposed by Chern et al.[12]. The calibrated SUPREM-3 was used to simulate the basic process technology[7]. One-dimensional impurity profiles were generated along the source-drain, the LDD and the channel regions of MOSFETs. These impurity profiles were used to generate twodimensional device structures for device simulations by using MEDICI. The device simulation program was calibrated to obtain a good agreement between the measured and the simulated electrical characteristics of all the devices. The calibrated MEDICI[7] was used to simulate electrical characteristics for n-channel MOSFET devices. All device simulations and measurements were performed by setting Vs = VB = 0. IDs vs Vos characteristics were obtained by keeping VD = 5 V and varying the gate bias Vo from 0 to 5 V. In order to generated substrate current vs gate voltage characteristics, Vo was ramped from 0 to 5.5 V for a fixed VD. The parameters Ai, fli and r/were optimized to fit the simulated substrate current with the measured data. The optimization procedure was performed on devices of different channel lengths. The constants r/ and fl~were optimized to obtain the accurate position of peak suhstrate current. After fixing the position of peak substrate current, the pre-exponential term A~, was optimized to obtain a 10% or lower match for Impact ionization rate of electrons 0.025' - - Simul=ed o Measured Left = 032 ~n / 0.020' C_rateOxide=150A ~ D,=Bi==sv 0.015" = ~ ~ / o : ' : = ,2" BaekBias=0 o/" W = 40 la'n 1.04pro a,".a" o o o 0.005' 0.000 0 1 2 3 4 5 0 Gate Voltage (V) Fig. 3. Simulated and measured los vs Vos characteristics of different Lightly Doped Drain type n-channel MOSFET devices. the magnitude of the simulated and the measured substrate current. 4. RESULTS AND DISCUSSION Figure 3 shows the measured and the simulated drain current vs gate voltage characteristics of LDD type n-channel silicon MOSFET devices of different channel lengths. It is evident from Fig. 3 that the simulated results agree very well with the measurement. Since substrate current is linearly dependent on channel current, it is extremely important to correlate the simulated and the measured channel current for accurate prediction of substrate current. In this study, it is found that the measured substrate current vs gate voltage characteristics for LDD type n-channel silicon MOSFETs of 0.8 micron CMOS technology can be represented by: ~.~ 1.65 x 106exp[-(1.231 x 106/E) z'23] (cm-]). (8) The optimized eqn (8) was used to simulate substrate current for LDD type n-channel silicon MOSFETs of effective channel lengths 0.32, 0.48, 0.64 and 1.04 microns. All the devices had a fixed channel width of 40 microns. The simulated substrate current vs gate voltage characteristics of the devices obtained by eqn (8) along with the measured data are shown in Fig. 4(a-d). It is seen from Fig. 4(a-d) that in the operating bias ranges, 0 < Vcs ~< 5.5 V and 4.5 V ~< lids ~< 5.5 V, the simulated and the measured data agree extremely well for all devices. 10 -3 10 -3 10 .4. 10 4 10 s 10-s 4.5V 10 4 1431 10el Simulated o Measured o Measured 10 "71 ,= 10:' Left=0.32pm 10-e 10 .9 • 1:o 0.0 | - 2.0 , • 3.0 10-9i I1 ! i 4.0 • L~ = 0.48 I~n 10-9 i 0.0 5.0 1.0 10 .7 V 5.0 < 10 4. - ¢ - ~ 10-s. [ === ~ lO-e. .= =1 m o~ 10-9 LaF = 0.64 p~n 10 -9 0.0 4.0 10"a I04. .= 3.0 (b) i0 -a. "~ 10-5 Im 10 e 2.0 Gate Voltage (V) Gate Voltage (V) (a) 10 "7' 10 -9 1.0 2.0 3.0 Gate Voltage (V) (c) 4.0 5.0 'i 10-9. 0.0 1.0 2.0 3.0 4.0 Gate Voltage (V) (d) 5.0 Fig. 4. Substrate current vs gate voltage characteristics of Lightly Doped Drain type n-channel MOSFET devices of different channel lengths. (W = 40/,4m and Gate Oxide Thickness = 150 A. The simulated data was obtained by optimized eqn (8). All data were obtained under Vs = Va = 0). 1432 SAMARSAI-IAet al. Equation (8) can be simplified to the most general form given by: 0q= 1.65 x 106 exp[ - ( l .66 x 106/Eel)], (cm -1) (9) where Ee~ = 0.054E 123, and r = 0.054. The expression (9) is similar to the expression for impact ionization rate of electrons reported by Ogawa[13] for electric field less than 250 kV/cm. The empirical constants in expression (9) are also comparable to the values reported by Lackner[9]. Therefore, eqn (8) can be applied to predict substrate current in advanced n-channel silicon MOSFET devices for electric fields less than 250 kV/cm. 5. CONCLUSION The expression for impact ionization rate of electrons obtained by optimizing the modified Chynoweth law of avalanche multiplication predicts much lower substrate current observed in advanced n-channel silicon MOSFETs. The simulated data agree very well with the substrate current characteristics measured on a broad range of LDD type n-channel silicon MOSFET devices with widely varying channel lengths and biasing conditions. The most important aspect of the present avalanche generation model is that the substrate current can be accurately simulated with the existing local field approximation in a device simulation program. Acknowledgements--Grateful thanks are due to Dr C. Bulucea for valuable comments and suggestions.Thanks are also due to Dr H. S. Chen, Fairchild Research Center for providing the wafers and Dr Philipp Lindorfer for providing process simulation data. The encouragements and support of the Otfice of Design Automation are also gratefully acknowledged. REFERENCES 1. A. G. Chynoweth, Phys. Rev. 109, 1537 (1958). 2. MEDICI User's Manual, Version 1. Technology Modeling Associates, Palo Alto (1992). 3. W. Maes, K. D. Meyer and R. Van Overstraeten, Solid-St. Electron. 33, 705 (1990). 4. R. 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