The demand for low power circuit design has increased tremendously due to explosive growth of battery operated portable devices like Microcontroller.Microcontroller uses register blocks that are inturn consists of flip flops. The... more
The demand for low power circuit design has increased
tremendously due to explosive growth of battery operated
portable devices like Microcontroller.Microcontroller uses
register blocks that are inturn consists of flip flops. The mandate
to reduce system power consumption and design energy-efficient
ICs has led to the increasing use of low-power IC design
techniques that prolong the battery life. In this paper, a novel
highly efficient power and delay optimized True Single Phase
clocked (TPSC) edge triggered flip-flop has been proposed. The
proposed circuit uses lesser number of transistors than the
conventional transmission gate D flip-flop that reduce the overall
power and delay.The proposed design is also free from both
glitch and charge sharing problems making it suitable for high
speed and low power applications. The circuits are simulated in
TANNER EDA simulation tool using PTM 180nm technology
files to compare the performance of proposed circuit with the
existing ones. The circuit performs well at different supply
voltages.
This paper presents a design of Low power 4 bits Counter at circuit and system level of abstraction using Cadence Virtuoso and Xilinx ISE 14.7 respectively. The laboratory work described includes the CMOS based transistor level design and... more
This paper presents a design of Low power 4 bits Counter at circuit and system level of abstraction using Cadence Virtuoso and Xilinx ISE 14.7 respectively. The laboratory work described includes the CMOS based transistor level design and VHDL based synthesis and implementation of the counter using back end and front end tools respectively. The functionality of the design has been simulated and tested using 0.18µm gdpk CMOS technology with 1.8V supply voltage using cadence virtuoso for back-end designing whereas, Xilinx ISE 14.7 is used for front-end simulation, synthesized using plan¬-ahead and is implemented on ArtixTM-7(family), with device xC7A100TTM. Power calculation has been done at 100 MHz clock frequency for the 1.8V supply voltage.
