Implementation of microprocessor core on a programmable device has been mostly sought by researchers due to its scalability and hardware reconfigurability. The proposed minimum version of 32-bit processor core is developed especially for... more
Implementation of microprocessor core on a programmable device has been mostly sought by researchers due to its scalability and hardware reconfigurability. The proposed minimum version of 32-bit processor core is developed especially for arithmetic operations of fixed point numbers, branch and logical functions. This paper presents the complete design of a microprocessor core in synthesizable Verilog. It defines an instruction set architecture suitable to be used for Internet of Things (IoT) application. This works as co-processor for IoT engine. The System on Chip (SoC) core has been synthesised and simulated using Synopsys Design Compiler and VCS. The SoC core is designed for 14 classic arithmetic and logical instructions suitable for IoT applications. However, the design can be expandable to 64 and 128 bits. This optimized processor core can be pipelined up to 5 stages and can be used for high speed applications. Architectural approach for low power and high performance are described and the area occupied by the entire core is 66562.3µm². The total power consumed by the design is 1.72 mW at 126MHz.
