MOSCAP

ZrO2/Ge is potential high-k dielectric candidate to replace silicon based devices. Controlling stress in zirconia film and stabilizing high dielectric constant phase is crucial for high-k application. A precise control of stress and phase selectivity in high-k thin films is demonstrated. Thin films of ZrO2 were grown by reactive sputter deposition. Wide range of
growth stress in thin films from -0.3 to -2.8 GPa can be tuned by growth rate control. Adatom incorporation into grain boundary was the dominant source of observed stress. Phase selectivity in zirconia was achieved by tuning growth parameters.

This paper presents a high PSRR full on-chip and area efficient low dropout voltage regulator (LDO), exploiting the nested miller compensation technique with active capacitor (NMCAC) to eliminate the external capacitor. A novel technique is used to boost the important characteristic for wireless applications regulators PSRR. The idea is applied to stabilize the Low dropout regulator. The proposed regulator LDO works with a supply voltage as low as 1.8 V and provides a load current of 50 mA with a dropout voltage of 200 mV. It is designed in 0.18 µm CMOS technology and the active area on chip measures 241×187 µm 2. Simulation results show that the PSR of LDO is-60 dB at a frequency of 60 KHz and-41.7 dB at a frequency of 1 MHz.

This paper presents the design of high-speed full adder circuits using a new CMOS mixed mode logic family. The objective of this work is to present a new full adder design circuits combined with current mode circuit in one unit to implement a full adder cell. This paper also discusses a high- speed hybrid majority function based 1-bit full adder that uses MOS capacitors (MOSCAP) in its structure with conventional static and dynamic CMOS logic circuit. The static Majority function (bridge) design style enjoys a high degree of regularity and symmetric higher density than the conventional CMOS design style as well as lower power consumption by using bridge transistors. This technique helps in reducing power consumption, propagation delay, and area of digital circuits while maintaining low complexity of mixedmode logic designs. Dynamic CMOS circuits enjoy area, delay and testability advantages over static CMOS circuits. Simulation results illustrate the superiority of the new designed adder circuits against the reported conventional CMOS, dynamic and majority function adder circuits, in terms of power, delay, power delay product (PDP) and energy delay product (EDP). The design is implemented on UMC 0.18µm process models in Cadence Virtuoso Schematic Composer at 1.8 V single ended supply voltage and simulations are carried out on Spectre S.