The objective of the work reported in this paper is to improve a 4-bit softcore processor previously designed in Verilog language, keeping its compact size. This processor was thought to be used as academic and didactic tool for teaching... more
The objective of the work reported in this paper is to improve a 4-bit softcore processor previously designed in Verilog language, keeping its compact size. This processor was thought to be used as academic and didactic tool for teaching as computers architecture subject as digital circuits subject in the technology faculty of the Universidad Distrital. The new features include arithmetic instruction with input carry, BCD operations enabling, rotating instructions, implementation of input and output register banks, increase of the number of general purpose registers of the data memory, and the reduction of the execution clock cycles per instruction. Additionally, the assembler software was enabled to support macro-instructions to make easy the comprehension of some composed functions. As result, a very compact softcore processor was obtained, by means of a Verilog description done in a single file. This implementation occupies only the 2% of the medium-size FPGA used for the application, reaching a maximum possible working clock frequency of 929 Mhz.
