research-article

Probabilistic shared cache management (PriSM)

Authors:

R GovindarajanAuthors Info & Claims

ACM SIGARCH Computer Architecture News, Volume 40, Issue 3

Pages 428 - 439

https://doi.org/10.1145/2366231.2337208

Published: 09 June 2012 Publication History

Abstract

Effective sharing of the last level cache has a significant influence on the overall performance of a multicore system. We observe that existing solutions control cache occupancy at a coarser granularity, do not scale well to large core counts and in some cases lack the flexibility to support a variety of performance goals.

In this paper, we propose Probabilistic Shared Cache Management (PriSM), a framework to manage the cache occupancy of different cores at cache block granularity by controlling their eviction probabilities. The proposed framework requires only simple hardware changes to implement, can scale to larger core count and is flexible enough to support a variety of performance goals. We demonstrate the flexibility of PriSM, by computing the eviction probabilities needed to achieve goals like hit-maximization, fairness and QOS.

PriSM-HitMax improves performance by 18.7% over LRU and 11.8% over previously proposed schemes in a sixteen core machine. PriSM-Fairness improves fairness over existing solutions by 23.3% along with a performance improvement of 19.0%. PriSM-QOS successfully achieves the desired QOS targets.

References

[1]

N. L. Binkert, R. G. Dreslinski, L. R. Hsu, K. T. Lim, A. G. Saidi, and S. K. Reinhardt. The M5 Simulator: Modeling Networked Systems. IEEE Micro, 26:52--60, 2006.

Digital Library

[2]

M. Chaudhuri. Pseudo-LIFO: the foundation of a new family of replacement policies for last-level caches. In MICRO 42, pages 401--412, New York, NY, USA, 2009. ACM.

Digital Library

[3]

S. Eyerman and L. Eeckhout. System-Level Performance Metrics for Multiprogram Workloads. Micro, IEEE, 28(3):42--53, may-june 2008.

Digital Library

[4]

S. Eyerman, L. Eeckhout, T. Karkhanis, and J. E. Smith. A performance counter architecture for computing accurate CPI components. In ASPLOS-XII, pages 175--184, New York, NY, USA, 2006. ACM.

Digital Library

[5]

L. R. Hsu, S. K. Reinhardt, R. Iyer, and S. Makineni. Communist, utilitarian, and capitalist cache policies on CMPs: caches as a shared resource. In PACT '06, pages 13--22, New York, NY, USA, 2006. ACM.

Digital Library

[6]

R. Iyer. CQoS: a framework for enabling QoS in shared caches of CMP platforms. In ICS '04, pages 257--266, New York, NY, USA, 2004. ACM.

Digital Library

[7]

A. Jaleel, W. Hasenplaugh, M. Qureshi, J. Sebot, S. Steely, Jr., and J. Emer. Adaptive insertion policies for managing shared caches. In PACT '08, pages 208--219, New York, NY, USA, 2008. ACM.

Digital Library

[8]

A. Jaleel, K. B. Theobald, S. C. Steely, Jr., and J. Emer. High performance cache replacement using re-reference interval prediction (RRIP). In ISCA '10, pages 60--71, New York, NY, USA, 2010. ACM.

Digital Library

[9]

S. Kim, D. Chandra, and Y. Solihin. Fair cache sharing and partitioning in a chip multiprocessor architecture. In PACT '04, pages 111--122, Washington, DC, USA, 2004. IEEE Computer Society.

Digital Library

[10]

J. Lin, Q. Lu, X. Ding, Z. Zhang, X. Zhang, and P. Sadayappan. Gaining insights into multicore cache partitioning: Bridging the gap between simulation and real systems. In HPCA, pages 367--378, 2008.

[11]

R. Manikantan, K. Rajan, and R. Govindarajan. NUcache: An efficient multicore cache organization based on Next-Use distance. In HPCA '11, pages 243--253, Los Alamitos, CA, USA, 2011. IEEE Computer Society.

Digital Library

[12]

R. Manikantan, K. Rajan, and R. Govindarajan. Probabilistic shared cache management(PriSM). Technical report, Lab for High Performance Computing, IISc, 2012.

[13]

M. K. Qureshi, A. Jaleel, Y. N. Patt, S. C. Steely, and J. Emer. Adaptive insertion policies for high performance caching. In ISCA '07, pages 381--391, New York, NY, USA, 2007. ACM.

Digital Library

[14]

M. K. Qureshi and Y. N. Patt. Utility-Based Cache Partitioning: A Low-Overhead, High-Performance, Runtime Mechanism to Partition Shared Caches. In MICRO 39, pages 423--432, Washington, DC, USA, 2006. IEEE Computer Society.

Digital Library

[15]

N. Rafique, W.-T. Lim, and M. Thottethodi. Architectural support for operating system-driven CMP cache management. In PACT '06, pages 2--12, New York, NY, USA, 2006. ACM.

Digital Library

[16]

D. Sanchez and C. Kozyrakis. The ZCache: Decoupling Ways and Associativity. In MICRO '43, pages 187--198, Washington, DC, USA, 2010. IEEE Computer Society.

Digital Library

[17]

D. Sanchez and C. Kozyrakis. Vantage: scalable and efficient fine-grain cache partitioning. In ISCA '11, pages 57--68, New York, NY, USA, 2011. ACM.

Digital Library

[18]

S. Srikantaiah, M. Kandemir, and Q. Wang. SHARP control: controlled shared cache management in chip multiprocessors. In MICRO 42, pages 517--528, New York, NY, USA, 2009. ACM.

Digital Library

[19]

K. Varadarajan, S. K. Nandy, V. Sharda, A. Bharadwaj, R. Iyer, S. Makineni, and D. Newell. Molecular Caches: A caching structure for dynamic creation of application-specific heterogeneous cache regions. In MICRO 39, pages 433--442, Washington, DC, USA, 2006. IEEE Computer Society.

Digital Library

[20]

Y. Xie and G. H. Loh. PIPP: promotion/insertion pseudo-partitioning of multi-core shared caches. In ISCA '09, pages 174--183, New York, NY, USA, 2009. ACM.

Digital Library

Cited By

Xiang YWang XHuang ZWang ZLuo YWang ZOliveira RFelber PHu Y(2018)DCAPSProceedings of the Thirteenth EuroSys Conference10.1145/3190508.3190511(1-15)Online publication date: 23-Apr-2018
https://dl.acm.org/doi/10.1145/3190508.3190511
Pons LSelfa VSahuquillo JPetit SPons J(2018)Improving System Turnaround Time with Intel CAT by Identifying LLC Critical ApplicationsEuro-Par 2018: Parallel Processing10.1007/978-3-319-96983-1_43(603-615)Online publication date: 1-Aug-2018
https://doi.org/10.1007/978-3-319-96983-1_43
Jain RPanda PSubramoney S(2017)Cooperative Multi-Agent Reinforcement Learning-Based Co-optimization of Cores, Caches, and On-chip NetworkACM Transactions on Architecture and Code Optimization10.1145/313217014:4(1-25)Online publication date: 14-Nov-2017
https://dl.acm.org/doi/10.1145/3132170
Show More Cited By

Index Terms

Probabilistic shared cache management (PriSM)
1. Hardware
  1. Integrated circuits
    1. Semiconductor memory
      1. Dynamic memory

Index terms have been assigned to the content through auto-classification.

Recommendations

Probabilistic shared cache management (PriSM)
ISCA '12: Proceedings of the 39th Annual International Symposium on Computer Architecture

Effective sharing of the last level cache has a significant influence on the overall performance of a multicore system. We observe that existing solutions control cache occupancy at a coarser granularity, do not scale well to large core counts and in ...
Performance-Energy Considerations for Shared Cache Management in a Heterogeneous Multicore Processor

Heterogeneous multicore processors that integrate CPU cores and data-parallel accelerators such as graphic processing unit (GPU) cores onto the same die raise several new issues for sharing various on-chip resources. The shared last-level cache (LLC) is ...
Managing shared last-level cache in a heterogeneous multicore processor
PACT '13: Proceedings of the 22nd international conference on Parallel architectures and compilation techniques

Heterogeneous multicore processors that integrate CPU cores and data-parallel accelerators such as GPU cores onto the same die raise several new issues for sharing various on-chip resources. The shared last-level cache (LLC) is one of the most important ...

Comments

Information & Contributors

Information

Published In

cover image ACM SIGARCH Computer Architecture News

ACM SIGARCH Computer Architecture News Volume 40, Issue 3

ISCA '12

June 2012

559 pages

ISSN:0163-5964

DOI:10.1145/2366231

Issue’s Table of Contents

ISCA '12: Proceedings of the 39th Annual International Symposium on Computer Architecture
June 2012
584 pages
ISBN:9781450316422
General Chair:
Shih-Lien Lu
Intel
,
Program Chair:
Josep Torrellas
University of Illinois

Copyright © 2012 ACM.

Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. Copyrights for components of this work owned by others than ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]

Publisher

Association for Computing Machinery

New York, NY, United States

Publication History

Published: 09 June 2012

Published in SIGARCH Volume 40, Issue 3

Check for updates

Qualifiers

Research-article

Contributors

Other Metrics

View Article Metrics

Bibliometrics & Citations

Bibliometrics

Article Metrics

30
Total Citations
View Citations
735
Total Downloads

Downloads (Last 12 months)14
Downloads (Last 6 weeks)3

Reflects downloads up to 09 Aug 2024

Other Metrics

View Author Metrics

Citations

Cited By

Xiang YWang XHuang ZWang ZLuo YWang ZOliveira RFelber PHu Y(2018)DCAPSProceedings of the Thirteenth EuroSys Conference10.1145/3190508.3190511(1-15)Online publication date: 23-Apr-2018
https://dl.acm.org/doi/10.1145/3190508.3190511
Pons LSelfa VSahuquillo JPetit SPons J(2018)Improving System Turnaround Time with Intel CAT by Identifying LLC Critical ApplicationsEuro-Par 2018: Parallel Processing10.1007/978-3-319-96983-1_43(603-615)Online publication date: 1-Aug-2018
https://doi.org/10.1007/978-3-319-96983-1_43
Jain RPanda PSubramoney S(2017)Cooperative Multi-Agent Reinforcement Learning-Based Co-optimization of Cores, Caches, and On-chip NetworkACM Transactions on Architecture and Code Optimization10.1145/313217014:4(1-25)Online publication date: 14-Nov-2017
https://dl.acm.org/doi/10.1145/3132170
Hu YSong MLi T(2017)Towards "Full Containerization" in Containerized Network Function VirtualizationACM SIGARCH Computer Architecture News10.1145/3093337.303771345:1(467-481)Online publication date: 4-Apr-2017
https://dl.acm.org/doi/10.1145/3093337.3037713
Hu YSong MLi T(2017)Towards "Full Containerization" in Containerized Network Function VirtualizationACM SIGPLAN Notices10.1145/3093336.303771352:4(467-481)Online publication date: 4-Apr-2017
https://dl.acm.org/doi/10.1145/3093336.3037713
Hu YSong MLi TChen YTemam OCarter J(2017)Towards "Full Containerization" in Containerized Network Function VirtualizationProceedings of the Twenty-Second International Conference on Architectural Support for Programming Languages and Operating Systems10.1145/3037697.3037713(467-481)Online publication date: 4-Apr-2017
https://dl.acm.org/doi/10.1145/3037697.3037713
Zang WGordon-Ross A(2016)CaPPSDesign Automation for Embedded Systems10.1007/s10617-015-9168-720:1(65-92)Online publication date: 1-Mar-2016
https://dl.acm.org/doi/10.1007/s10617-015-9168-7
Li YMelhem RJones A(2014)A Practical Data Classification Framework for Scalable and High Performance Chip-MultiprocessorsIEEE Transactions on Computers10.1109/TC.2013.16163:12(2905-2918)Online publication date: 1-Dec-2014
https://dl.acm.org/doi/10.1109/TC.2013.161
Singh SSurana NPrasad KJain PMekie JAwasthi M(2023)HyGain: High-performance, Energy-efficient Hybrid Gain Cell-based Cache HierarchyACM Transactions on Architecture and Code Optimization10.1145/357283920:2(1-20)Online publication date: 1-Mar-2023
https://dl.acm.org/doi/10.1145/3572839
Garcia-Garcia ASaez JCastro FPrieto-Matias M(2019)LFOCProceedings of the 48th International Conference on Parallel Processing10.1145/3337821.3337925(1-10)Online publication date: 5-Aug-2019
https://dl.acm.org/doi/10.1145/3337821.3337925
Show More Cited By

View Options

Get Access

Login options

Check if you have access through your login credentials or your institution to get full access on this article.

Full Access

Get this Publication

View options

PDF

View or Download as a PDF file.

eReader

View online with eReader.

Media

Figures

Other

Tables

View Issue’s Table of Contents