Article

HW/SW Codesign of the MPEG-2 Video Decoder

Authors:

Matjaz Verderber,

Andrej Zemva,

Andrej TrostAuthors Info & Claims

IPDPS '03: Proceedings of the 17th International Symposium on Parallel and Distributed Processing

Page 179.1

Published: 22 April 2003 Publication History

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Abstract

In this paper, we propose the optimized real-time MPEG-2 video decoder. The decoder has been implemented in one FPGA device as a HW/SW partitioned system. We made timing/power-consumption analysis and optimization of the MPEG-2 decoder. On the basis of the achieved results, we decided for hardware implementation of the IDCT and VLD algorithms. Remaining parts were realized in software with 32-bit RISC processor. MPEG-2 decoder (RISC processor, IDCT core, VLD core) has been described in high-level Verilog/VHDL hardware description language and implemented in Virtex 1600E FPGA. Finally, the decoder has been tested on the Flextronics prototyping board.

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Plavec FVranesic ZBrown S(2013)Exploiting Task- and Data-Level Parallelism in Streaming Applications Implemented in FPGAsACM Transactions on Reconfigurable Technology and Systems (TRETS)10.1145/25359326:4(1-37)Online publication date: 1-Dec-2013
https://dl.acm.org/doi/10.1145/2535932
Lee WPatel KPedram MNebel WStan MRaghunathan AHenkel JMarculescu D(2006)Dynamic thermal management for MPEG-2 decodingProceedings of the 2006 international symposium on Low power electronics and design10.1145/1165573.1165647(316-321)Online publication date: 4-Oct-2006
https://dl.acm.org/doi/10.1145/1165573.1165647

Index Terms

HW/SW Codesign of the MPEG-2 Video Decoder
1. Computer systems organization
  1. Architectures
    1. Parallel architectures
      1. Very long instruction word
    2. Serial architectures
      1. Complex instruction set computing
      2. Reduced instruction set computing
2. Hardware
  1. Electronic design automation
    1. Hardware description languages and compilation

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IPDPS '03: Proceedings of the 17th International Symposium on Parallel and Distributed Processing

April 2003

ISBN:0769519261

Publisher

IEEE Computer Society

United States

Publication History

Published: 22 April 2003

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Plavec FVranesic ZBrown S(2013)Exploiting Task- and Data-Level Parallelism in Streaming Applications Implemented in FPGAsACM Transactions on Reconfigurable Technology and Systems (TRETS)10.1145/25359326:4(1-37)Online publication date: 1-Dec-2013
https://dl.acm.org/doi/10.1145/2535932
Lee WPatel KPedram MNebel WStan MRaghunathan AHenkel JMarculescu D(2006)Dynamic thermal management for MPEG-2 decodingProceedings of the 2006 international symposium on Low power electronics and design10.1145/1165573.1165647(316-321)Online publication date: 4-Oct-2006
https://dl.acm.org/doi/10.1145/1165573.1165647

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HW/SW Partitioned Optimization and VLSI-FPGA Implementation of the MPEG-2 Video Decoder

FPGA-oriented HW/SW implementation of the MPEG-4 video decoder

HW/SW codesign techniques for dynamically reconfigurable architectures

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