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台灣新竹 ‧ 交通大學 ‧ 前瞻電力電子中心 808 實驗室 ( 電力電子系統與晶片實驗室 ) 

Implementation of Digital Controller 

數位控制的實現 

鄒應嶼 

教授 

國立交通大學 

電機與控制工程研究所 

2012 年 5 月 4 日 

Power Electronic Systems & Chips Lab., NCTU, Taiwan 

Advanced Power Electronics Center, NCTU, Taiwan

Real-time Control Systems: A Tutorial 

A. Gambier 

Automation Laboratory, B6 23-29, EG. Bauteil C 

University of Mannheim, 68131 Mannheim, Germany 

gambier@ti.uni-mannheim.de 

Abstract 

The literature about real-time systems presents digital 

control or computer controlled systems as one of its most 

important practical application field. However, it is very 

difficult to find in these textbooks real-time control aspects. 

It seems to be more natural that these applications should 

be treated as part of digital control courses. In spite of 

that, control system literature rarely includes extensively 

the real-time subject and it does normally not pay attention 

to real-time aspects beyond algorithms and choice of sampling 

times. The aim of this paper is to highlight important 

issues about real-time systems that should be taken into 

account at the moment to implement digital control. 

1 Introduction 

The implementation of digital control systems and real-time 

systems belong together and they should be connected 

more or less later in the control engineering curricula. 

However, it is difficult to find this connection in the 

standard textbooks, where the real-time implementation is 

almost always ignored. For example, a very good introduction 

into computer controlled systems can be found in [1], 

but no orientation to the real-time software is given there. 

Mechanisation of control algorithms are given e.g. in [9]. 

In [8], hardware and software for digital control systems 

are described shortly. On the other hand, in [3] the realtime 

system design is treated from the optic of control 

engineering without to consider implementation aspects. 

In general, real-time issues are gradually becoming “transparent” 

to the control engineering student. This transparency 

has been considerably increased in the last years with the 

advent of software tools like Matlab/Simulink ([24]) with 

its RTW (Real Time Workshop), the RTWT (Real Time 

Windows Target) and products from other companies like 

WinCon from Quanser ([25]) and ECP Executive from ECP 

Systems ([26]). They certainly do the implementation of 

real-time experiments easier and save much time, but on 

the other hand they put more distance regarding to the reallife 

problems, which can emerge during the real-time implementation 

of control systems. Hence, control concepts 

become today easier to be exemplified, but control engineering 

students can lose the real dimension about designing 

real-time control systems, particularly when they have to 

deal with time-critical applications. 

This paper attempts to give an introduction to the implementation 

of real-time control systems, where characteristics 

of real-time systems and digital control issues are taking together 

into account. 

The outline of the paper is as follow. Digital control aspects 

are introduced in Section 2. Definitions and characteristics 

of real-time systems are described in Section 3. Here, some 

common mistakes and misconceptions by developing realtime 

control software are also discussed. Section 4 treats the 

implementation of real-time controllers and Section 5 summarizes 

some important specifications for the implementation 

of real-time control systems as well as some well-known 

commercial products. Finally, conclusions are drawn in 

Section 6. 

2 Computer controlled systems 

The introduction of digital computers in the control loop 

has allowed developing more flexible control systems 

including higher-level functions and advanced algorithms. 

Furthermore, most current complex control systems could 

not be implemented without the application of digital hardware. 

However, the simple sequence sensing–control–actuation 

for the classical feedback control becomes more complex 

as well. Nowadays, this sequence can be supplemented 

as follow: sensing–data acquisition–control law 

calculation–actuation–data base update. Figure 1 shows 

an overview of such control systems. 

User 

Computer 

User 

Supervisory 

control 

u(k) 

D/A Hold 

y m (k) 

GUI 

Real-time Computer 

u(k) 

r(k) 

A/D 

Scaling 

unitsvoltage 

voltagedig. number 

Control Algorithm 

u(k) = f [y(k), r(k)] 

From other 

control level 

Scaling 

voltage units 

dig. numbervoltage 

u(t) 

Actuator 

y m (t) 

Real-time Clock 

Port 

y(k) 

Port 

Process 

Sensor 

u(k) 

digital 

number 

Figure 1. Overview of a computer controlled system 

y(t)

Thus, the control system now contains not only wired components 

but also algorithms, which must be programmed, 

i.e. software is now included in the control loop. This 

leads to new aspects to take into account by designing 

control systems: 

1.Errors due to A/D and D/A conversion as well as due 

to limited length word calculations. This subject is 

well treated in the literature (see for example [ 9]). 

2. Software developing is prone to errors. Thus, a new 

concept has to be introduced to consider this aspect, the 

verification, i.e. a mechanism to test if the software is 

doing exactly what it is expected. Here it is necessary 

to remark that in general a high percent of errors in 

digital control systems are caused by programming 

mistakes. Hence, digital control projects need not 

only control engineers but also engineers with skills in 

software engineering and computer programming. 

3. Standard textbooks on digital control systems normally 

assume that sampling is uniform, periodic and synchronous. 

This leads to a case of “zero-time-execution” for 

the control law. However, that is not realistic since the 

control algorithm also consumes some time producing a 

control or feedback delay (control or feedback latency), 

i.e. a delay between a sampling instant and the instant 

at which a control-signal value is applied to the actuator. 

If the controller design is based on a model and the 

delay is constant and known, it could be helpful to use a 

tool for the description of the inter-sample behaviour 

(e.g. modified z-transform) in order to obtain a discretetime 

model more approximated to the real case. 

4.The computational time of control algorithms can 

change from one sampling instant to other (e.g. hybrid 

controller with controller switching mechanism, event 

based controllers, adaptive controllers with on-line 

parameter update, etc.). This variation in the delay is 

called control jitter (according to the IEEE, jitter is “the 

time-related abrupt, spurious variation in the duration 

of any specified related interval”). Moreover, value 

calculation for the control signal is usually carried out 

using multitasking (Subsection 3.2) defining a set of 

control tasks with respective priorities. Thus, a task can 

be pre-empted by higher priority tasks. In general, it 

can be said that the control system is also affected by 

several kind of jitter depending on context: sampling 

jitter, control latency jitter, input jitter, output jitter, etc. 

Finally, real-time issues are often ignored in the implementation 

of digital control systems. This is in part a consequence 

of erroneous definitions and false interpretations. 

Popular misconceptions from the control engineering 

community about real-time systems are for example: 

The computer was connected to the plant by mean of 

A/D and D/A converters in order to obtain the realtime 

system. Analog plants should be connected to the 

computer through A/D and D/A converters. This link 

with the “real world” does not lead to a real-time 

system. On the other hand, it is possible to find realtime 

systems in complete digital contexts. 

Our plant is so slow that real time is actually no 

problem. A slow control system, which does not need 

a fast computer, can require critical time constraints. 

It is also possible that a control system does no need 

any hard real-time requirements but it is not necessarily 

a consequence of the slow plant. 

It is not meaningful to talk about guarantying real-time 

performance. It is true that occasionally time constraints 

can be relaxed without introducing additional problems 

in the control loop. This particularly applies to nice designed 

laboratory experiments. However, this actually 

depends on the application, and the time criticality 

should be proved for each individual case. On the other 

hand, real-time performance cannot be 100% guaranteed 

while hardware and software failures cannot be avoided 

at all. 

We do not care about real time in our digital control 

system and even though it works. This statement is 

similar to the previous one. The problem here is that 

you are not able to know when your system can fail. 

Real-time programming is assembly coding, priority 

interrupt programming and device driver writing. It 

is true that some code is still writing in assembler. 

However, high programming languages like C, Ada 

95, Modula 2 and Real-time Java are normally used 

to develop real-time software. Device driver programming 

is necessary for real-time as well as non-realtime 

systems but they should be provided by the operating 

system or by the device manufacturer. Interrupt 

programming should be in principle avoided as much 

as possible. This point is treated in Subsection 3.5. 

In the next Sections, an overview about real-time systems 

and control systems will be given in order to clarify real-time 

programming and its most important application. 

3 Real-time systems: a short introduction 

Real-time computing is a vast field and therefore, a complete 

discussion about that is outside the scope of this paper. 

Therefore, only the most relevant aspects will be treated here. 

3.1 Definitions and general aspects 

It is possible to find in the literature several definitions for 

real-time systems. Here, a definition that does not contradict 

the definition given in the IEEE POSIX Standard (Portable 

Operation System Interface for Computer Environments) 

will be assumed 

A real-time system is one in which the correctness of a 

result not only depends on the logical correctness of 

the calculation but also upon the time at which the 

result is made available. 

This definition emphasizes the notion that time is one of 

the most important entities of the system, and there are 

timing constraints associated with systems tasks. Such 

tasks have normally to control or react to events that take 

places in the outside world, which are happening in “real 

time”. Thus, a real-time task must be able to keep up with 

external events, with which it is concerned.

It should be noted here that real-time computing is not 

equivalent to fast computing. Fast computing aims at getting 

the results as quickly as possible, while real-time computing 

aims at getting the results at a prescribed point of time within 

defined time tolerances. Thus, a deadline (for this point of 

time) can be associated with the task that has to satisfy this 

timing constraint specifying either its start or completion time. 

If the task has to meet the deadline, because otherwise it 

will cause fatal errors or undesirable consequences, the 

task is called hard real-time task. On the contrary, if the 

meeting of the deadline is desirable but not mandatory, the 

task is said to be a soft real-time task. By extension, one 

speaks about hard/soft time-constraints as well as hard/soft 

deadlines. 

3.2 Real-time operating systems (RTOS) 

In order to implement multitasking real-time systems, two 

approaches can be used: The first one consists in programming 

by using concurrent real-time languages and the 

second one is to use a sequential language and a real-time 

operating system ([4]). There has been a long debate about 

advantages and drawback of both approaches, which will not 

be treated here. However, a very important point is that 

real-time systems and real-time operating systems are not 

equivalent concepts: A RTOS provides facilities, like 

multitasking (i.e. concurrency or potential parallelism), 

scheduling, intertask communication mechanism, etc., for 

implementing real-time systems. 

Old operating systems are characterised by the fact that each 

task is a simple program running in its own memory space. 

In the last years, there has been a tendency to provide facilities 

for creating several tasks within the same program to 

have faster task switch, unrestricted access to shared memory 

and to simplify the communication and synchronization. 

Such tasks are commonly called threads. The most 

important disadvantage of using threads consists in that the 

memory is not protected between threads of the same 

program. Figure 2 illustrates the difference between 

multitasking and multithread systems. 

M ultitasking 

M ultitasking 

One Thread 

M ultithread 

Task 1 Task n Task 1 

Task n 

Program 1 Program n Program 1 Program n 

Figure 2. Multitasking and multithreading concepts 

Together with parallelism, determinism is another important 

property of RTOS. A RTOS is predictable if the time 

necessary to acknowledge a request of an external event is 

know in advance. The end point of this predictability 

scale is called determinism, in sense that this time is 

exactly known in advance. This concept should not be 

confused with responsiveness, which is the time (after the 

acknowledgement) elapsed till the request is attended. 

Determinism and responsiveness make up the response time 

to external events. This is also called system latency. 

Modern RTOS include in general the following features: 

fast switch context, small size, preemptive scheduling based 

on priorities, multitasking and multithreading, intertask communication 

and synchronisation mechanisms (semaphores, 

signals, events, shared memory, etc.), real-time timers, etc. 

However, RTOS are similar to standard operating systems 

from a structural point of view, since functional components 

as interrupt handler, task manager, memory manager, I/O 

subsystem and intertask communication are proper of both 

kind of operating systems. 

3.3 Real-time scheduling 

The distinctive part of a RTOS is the task manager. It is 

composed by the Dispatcher and the Scheduler. The Dispatcher 

carries out the context switch, i.e. the parameter 

saving for the outgoing task and the parameter loading for 

the incoming task, and the CPU handing over to the task 

that is becoming active. 

The Scheduler has the function of selecting the task, which 

will obtain the processor as next. This choice is given by 

means of algorithms and this is the point where RTOS and 

non-RTOS are mostly distinguished. Real-time systems need 

special algorithms to schedule a set of tasks. This is a very 

active area of research in computer science and many 

algorithms have been proposed. In this paper, only the 

most important uniprocessor scheduling algorithms for realtime 

requirements will be presented. Fig. 3 presents an 

overview about some well-known scheduling algorithms 

(for details see e.g. [17], [12]). 

Scheduling algorithms can be grouped in two classes: static 

and dynamic algorithms. A static scheduling requires that 

the complete information about the scheduling problem 

(number of tasks, deadlines, priorities, periods, etc.) is 

known a priori. Thus, the scheduling problem is solved 

before the schedule is executed. Such scheduler is also 

called clairvoyant. If at run time the feasibility can be 

determined and changes in the configuration may be carried 

out, then the scheduling is said to be dynamic. 

Static schedules must always be planed off-line. Dynamic 

schedules can be planed either off-line if the complete 

scheduling problem is known a priori but with an on-line 

implementation, i.e. the configuration is changed at run 

time, or on-line if the future is unknown or ignored. Advantage 

of off-line scheduling is its determinism and the disadvantage 

its inflexibility. On the contrary, an on-line 

scheduling is very flexible but poor in determinism. Moreover, 

an on-line scheduling does not perform well if the 

system is overloaded. However, on-line scheduling is clearly 

the only option in a system whole future workload is 

unpredictable. 

The guarantee that all deadlines are met can be taken as 

measure of the effectiveness of a real-time scheduling algorithm. 

If any deadline is not met, the system is said to be 

overloaded. Liu and Layland ([13]) showed that the total 

processor utilization for a set of n tasks given by 

n C 

U i 

(1) 

min( D , ) 

i 1 i T 

i 

can be used as schedulability test. C is the execution time, 

D the deadline and T the task period. If the task is 

aperiodic or the deadline is smaller than the period, then 

the deadline is used in the equation. Figure 3 presents a 

classification for the most well-known dynamic scheduling 

algorithms for uniprocessor systems. In the following, the

most popular algorithms for scheduling tasks with real-time 

requirements will be shortly presented. 

Static Scheduling 

Scheduling Policies 

With Priorities 

Dynamic Priorities 

Dynamic Scheduling 

Without Priorities 

Preemptive Non-preemptive Preemptive 

Static Priorities 

Nonpreemptive 

Preemptive 

Nonpreemptive 

SJF FPS mit Deadline mit Deadline SRT HRRN RR FCFS 

Real-Time Scheduling 

FPS: Fixed-Priority 

RMS DMS EDF LLF MUF 

FCFS: First Come First served RMS: Rate Monotonic 

RR: Round Robin 

DMS: Deadline Monot. Scheduling 

Real-Time Scheduling 

FC-EDF 

EDF: Earliest Deadline 

SJF: Shortest Job First 

LLF: Least Laxity First 

SRT: Shortest Remaining Time MUF: Maximum Urgency 

HRRN: Highest Response Ratio Next FC-EDF: Feedback EDF 

Figure 3. Classification of uniprocessor scheduling 

algorithms 

Fixed-Priority Scheduling (FPS). In this approach, each 

task has a fixed static priority which is computed pre-run 

time. The runnable tasks are executed in the order determined 

by their priorities. If all tasks are periodic, a simple 

priority assignment can be done according to the statement: 

the shorter the period, the higher the priority. This approach 

is known as Rate Monotonic Scheduling (RMS) and it was 

proposed in [13]. The schedulability analysis for this algorithm 

presumes that all tasks are pre-emptive, periodic with 

deadlines equal to the period and independent (i.e. no task 

precedence between tasks exists). In this case the total 

utilization has an upper bound given by 

1/ n 

U n(2 1) 

This bound converges to 0.693 for n , to 0.88 when 

the periods are uniform and to 1,00 only when the periods 

are harmonics of the smallest period. Under the conditions 

given above, it can be showed that the algorithm is 

optimal among fixed priority policies (i.e. given a set of 

tasks, RMS always produces a feasible schedule for this set, 

if any other algorithm can do that). This approach is easy to 

be implemented and if there are schedulability problems, 

the first task to fail is the task with the longest period, i.e. 

if the system becomes overloaded, deadlines are missed predictably. 

The most important drawbacks are its low utilization 

(under 70%), the fixed priorities, which can lead to 

starvation and deadlocks, and the fact that all deadlines 

should be equal to the periods. 

In order to get out of the last problem, the Deadline Monotonic 

Scheduling (DMS) was proposed in [11]. They generalized 

the RMS allowing deadlines less than periods, 

where the fixed priority of a task is inversely proportional 

to its deadline. 

(2) 

Deadline-based Dynamic Scheduling. There are some dynamic 

scheduling algorithms which are based on assigning 

priorities according to their deadline. The simplest algorithm 

in this class is the Earliest Deadline First algorithm (EDF), 

where the task with the earliest (shortest) deadline has the 

highest priority. Thus, the resulting priorities are naturally 

dynamic. This algorithm can be used for both dynamic and 

static scheduling. However, absolute deadline are normally 

computed at run time and hence the algorithm is presented 

as dynamic. This algorithm was also proposed in [ 13] . 

They also showed that if all task are periodic and preemptive, 

then the algorithm is optimal and its utilization is U 1. 

A disadvantage of this algorithm is that the execution time is 

not taken into account in the priority assignment. 

Another algorithm that is also optimal for scheduling preemtive 

tasks on one-processor system is the Maximum Laxity 

First (MLF) algorithm ([6], also called Least Slack-time 

First, (LSF) or Least Laxity First (LLF) algorithm). At any 

time, the laxity (or slack) of a task with deadline is equal to 

Laxity deadline remaining execution time . (3) 

The MLF algorithm assigns priorities based on their laxities: 

the smaller the laxity, the higher the priority. This algorithm 

requires the knowledge of the current execution time, and 

then laxity is essentially a measure of the flexibility available 

for scheduling a task. Thus, MLF takes into consideration the 

execution time of a task, and this is it advantage in front of 

EDF. On the other hand, the execution time is normally not 

known until the task complete and therefore estimation is 

necessary. Because this estimation is used to schedule the 

set of task, the resulting schedule can be incorrect. This is 

its most serious disadvantage. 

The MLF algorithm also has a schedulable bound of 100% 

for all task sets. A problem with EDF as well as MLF is 

that there is no way to predict which tasks will fail in 

transient overboard situations. This has led to another algorithm 

called Maximum Urgency First (MUF) algorithm 

([19]), where an explicit description of urgency is assigned 

to each task. This urgency is defined as a combination of 

two fixed priorities, and a dynamic priority, which is 

inversely proportional to the task laxity. One of the fixed 

priorities, called task criticality has precedence over the 

dynamic priority. The other fixed priority, called user 

priority, has lower precedence than the dynamic priority. 

The criticality helps on-line algorithms to distinguish more 

important from less important tasks. Finally, it is necessary 

to remark that all mentioned dynamic algorithms do not 

remain optimal if pre-emption is not allowed or the system 

has multiple processors. 

If sporadic or aperiodic tasks must be scheduled, two algorithms 

can be used: the Deferrable Server Algorithm (DSA) 

and the Sporadic Server Algorithm (SSA). However, only 

SSA conforms to the RMS schedulability analysis. 

3.4 Intertask Communication and Synchronisation 

The intertask communication can be carried out as for 

non-RTOS by using mailbox, pipes and shared memory. 

Synchronization is very important in real-time systems for 

two reasons: (i) tasks may experience unpredictable delays 

due to blocking on shared resources to which they require 

exclusive access (e.g. A/D and D/A converters), and (ii) some 

tasks should be executed depending on results of other tasks. 

It can be shown that the addition of mutexes in real-time programs 

makes the general scheduling problem a non-predictable 

one ([14]). To solve this problem with an EDF algorithm 

kernelized monitor protocol can be used and priority 

ceiling protocol if the scheduling algorithm is RMS. 

3.5 Common programming mistakes 

By programming real-time system, many typical mistakes 

are often founded ([ 18] ). Some of them are:

Large or many if-then-else and/or case statements. 

These statements introduce in the code many different 

paths with varying length so that the code will also have 

different execution time. This becomes more significantly 

when the path is very long. Variable functions, 

state machines, lookup tables should be used instead the 

mentioned statements. 

Delays implemented as empty/dummy loops. This leads 

to inaccurately delays depending on the hardware. 

RTOS timing mechanisms should be used here for 

implementing exactly time delays. 

Indiscriminate use of Interrupts. Interrupts affect seriously 

the real-time predictability: They cannot be 

scheduled, and they have always very high priorities. 

Programs based on interrupt are very difficult to debug 

and to analyse. Moreover, they operate in kernel 

context. 

There is a very popular myth, which says that interrupts 

save CPU time and they guarantee the execution start of 

a task. This can be true in small and simple microprocessor 

based systems. However, it is not the case for 

complex real-time system, where non-preemptive periodic 

tasks can provide similar latency with better predictability 

and CPU utilization. 

Periodic polling threads should be used if it is possible. 

Interrupt services routines should be programmed in 

such a form that its only function is to signal an 

aperiodic server. 

Configuration information fixed using #define or similar 

statements. Programmers frequently use #define statements 

in their code to specify register addresses, limits 

for arrays, and configuration constants. Although this 

practice is common, it is undesirable because it prevents 

on-the-fly software patches for emergency situations, 

and it increases the difficulty of reusing the software in 

other applications. Changes in the configuration require 

that the entire application has to be recompiled. 

Implementation based on a big single loop. One big 

loop leads to the fact that the complete software executes 

to the same rate. In order to assign different and 

proper rates concurrent techniques for pre-emptive 

RTOS should be used. 

Use of message passing as primary intertask communication 

mechanism. Message passing reduces real-time 

schedulability bound and it produces significant overhead 

leading to many aperiodic servers instead of periodic 

tasks. Moreover, deadlocks can appear in closed 

loops systems. Shared memory and proper synchronization 

mechanisms to prevent deadlocks and priority 

inversion should be used. 

To think that problems can be fixed magically. Programming 

errors, which become seldom visible in the 

debugging phase, can appear exactly at the time when 

the application is running and it is not possible to 

correct the mistake. It is necessary to find all mistake 

causes before the software is released. 

Do not analyse memory during the design. The amount 

of memory in most real-time systems is limited. Frequently, 

programmers have no idea about how much 

memory a certain program or data structure uses. Moreover, 

they are normally wrong by an order of magnitude. 

A memory analysis is quite simple with most of 

today’s development environments. 

Design without execution-time measurement. It is very 

common to assume that the program is short enough 

and the available time is sufficient. However, measuring 

of execution time should be part of the standard testing 

in order to avoid surprises. Hence, the system should 

be designed so that the code is measurable all time. 

4 Computer implementation of control systems 

Building a real-time control system requires two stages in 

general: controller design and digital implementation. At 

controller design stage, normally a control performance 

index is defined (because optimal control is normally 

preferred to specify control performance requirements) and 

a controller is designed which optimise this index while 

maintaining stability and rejecting disturbances. SISOcontrollers 

in an imput/output approach, e.g. PID (Proportional 

Integral Derivative), GMV (Generalized Minimum 

Variance) GPC (Generalized Predictive Controller), pole 

placement, etc., can be represented by the general equation 

1 1 1 

Pq ( ) uk ( ) Tq ( ) rk ( ) Qq ( ) yk ( ) 

where P, T, and Q are polynomials, u is the control signal, 

r the reference signal and y the plant output. (Notice that 

for the PID controller T(q -1 ) = Q(q -1 )). State Space controller 

with observer are given in general by 

(1) 

u( k) K r( k) K x ˆ( k) 

(2) 

o 

r 

xˆ( k1) [ AK C] xˆ( k) [ BK D] u( k) K o y( 

k) 

where K o is the observer gain. The controller is executed 

cyclically according to the sampling time, whose value is 

assumed to be correctly chosen, i.e. satisfying not only the 

condition given by the Shannon’s sampling theorem but 

also achieving the desired performance (the control design is 

normally based on a time-discrete model which also depend 

on the sampling time). In order to satisfy the “zero-execution 

time” requirement, it is desired that the new value for the 

control signal be delivered as soon as possible. 

At implementation stage, multiple control tasks should be 

scheduled to run on microprocessors or microcontrollers. 

All tasks should be scheduled with limited available computing 

resources. The chosen sampling time should take into 

account the limited computation time provided by the hardware. 

Thus, the computation time delay (control latency) 

is always in conflict with the sampling time T o . Depending 

on the magnitude of relative to T o this conflict can be 

classified into either a delay (0 < < T o ) or loss (T o ) 

problem. Since the control latency is usually affected by 

control jitter, delay and loss can occur alternately in the 

same system at different times. The loss of the control 

signal u(k) is equivalent, to the case when the controller 

computer fails to update its output during any one sampling 

interval and u(k-1) is applied again. Because this could 

occur randomly at any time, the failure to deliver a control 

o 

x 

(3)

signal can be treated as a correlated random disturbance 

u(k) at the input of the plant. 

The interaction between control performance and task scheduling 

has been investigated in [16]. Research results led to 

the conclusion that separated design produces suboptimal 

performance. Hence, the digital control system design has to 

be revisited in order to introduce considerations about 

real-time computing. In [10] and [16], the task attribute 

assignment with respect to control performance was focused 

on task period selection for a single task model of the controller 

like the example shown in Figure 4 (Matlab syntaxes is 

used for simplicity). 

Set_Event_Variable() 

(wait function) 

set highest priority; 

y = read_ADC(Ch#1); 

ys = signal_conditioning_scaling(y); 

r = signal_generator(Parameters); 

e = [(w-ys) e(2:length(e)]; 

u = u + q’ * e; 

write_DAC(Ch#1, u); 

Scheduler 

Figure 4. Controller implemented with one real-time periodic 

task 

Here, in order for delivering the control signal u(k) as soon 

as possible one-step-ahead predictive controller can be used 

in the form 

uk ( 1) f[ rk ( 1), rk ( ), , rk ( n), uk ( ), , 

(4) 

uk ( m), yk ˆ( 1), yk ( ), , yk ( n)] 

where r(k+1) is assumed to be known and yk ˆ( 1) 

is 

calculated by a simple linear predictor given by 

yk ˆ( 1) yk ( ) yk ( ) yk ( 1) 

 

( k1) k k( k1) 

yk ˆ( 1) 2 yk ( ) yk ( 1) 

Hence, the control task started first delivering u(k) (which 

was calculated at time k-1), after this the remaining operations 

are carried out, i.e. read y(k) from A/D converter, 

calculating yk ˆ( 1) 

and then u(k+1). The disadvantage of 

this approach is that the control signal is calculated based on 

a prediction. This prediction can be however improved by 

using a model of the plant but in this case, more execution 

time is necessary. 

A second approach was proposed by [ 5]. This is based on 

the implementation of two periodic real-time tasks. The 

first one calculates the control signal directly after reading 

and conditioning y(k) and the second one updates the states 

after the control signal value was delivered. For the I/O 

representation, eq. (1) can be implemented by using a 

realization in the form of a ladder structure given by 

xr( k1) A 0xr( k) Br 

0 rk 

() 

 

 

xy( k1) y( k) 

 

0 A x 0 B 

 

yk () 

 

y 

 

(5) 

R 

(6) 

(7) 

uk ( ) 

C 

r( ) 

r 

( ) 

r 

C 

k d r k 

y 

x 0 

 

y( k) 

 

d 

y 

y( k) 

 

 

x 

 

0 

 

where the matrices A, B y , B r , C y , C r , d y and d u are obtained 

from some realization of 

1 

1 

T( z ) 

ur( z) r( z) 

and Qz ( ) 

u 

1 

y( z) yz ( ) 

1 

Pz ( ) 

Pz ( ) 

and contains the controller parameters. Figure 5 illustrates a 

possible implementation of this idea. 

Task 1 (with maximum priority) 

Scheduler 

Set_Event_Variable(1) 


y = read_ADC(Ch#x); 



ry = [r; ys]; 

u = [Cr –Cy]* xu + [dr 0;0 dy] * ry; 

write_DAC(Ch#x, u); 

Reset_Event_Variable(2); 

Sampling time T 

Task 1 

Shared Memory 

Deadline Task 1 

Task 2 

Task 2 



xu= Au * xu + Bu * ry; 

(8) 

Deadline 

Task 2 

Figure 5. I/O Controller implemented with two real-time 

tasks 

Space-state controllers naturally fit this task model (Figure 

6). All these approaches are based on optimal control design. 

In [15], the control performance is specified by rise time, 

maximum overshoot, settling time and steady state error. The 

task scheduling was carried out by a heuristic approach. 

Task 1 (with maximum priority) 

Scheduler 




u = Kr * r - Kx * x; 


eset_Event_Variable(2); 

Shared Memory 

u, r, x, y, Ab, Bb, Kr, Kx 

etc. 

Deadline 

Task 2 

Sampling time T 

Task 1 

Deadline Task 1 

Task 2 

Task 2 





x = Ab * x + Bb * [u’ y’]’; 

Figure 6. Real-time implementation of a state-space 

controller 

A supervisor can be implemented as an independent task. 

A possible scheme is shown in Figure 7. 

4.1 Some common mistakes in the implementation of 

real-time control systems 

In the laboratory, it can be frequently observed that control 

engineering students commit some of following mistakes: 

Overlook the anti-aliasing filter. Anti-aliasing filter is 

necessary to bind the highest signal frequency in order to 

determine correctly the sampling time. The filter can be 

dispensed with if the highest frequency of the signal is 

known and the sampler can be set accordingly. 

Implement the anti-aliasing filter in software (as digital 

filter) after the sampling. This is a typical error committed 

by students. Because the filter is used to avoid

Task 1 (with maximum Priority) 

Scheduler 


Sampling Time (control) 





ry = [r; ys]; 

u = [Cr –Cy]* xu + [dr 0;0 dy] * ry; 


Reset_Event_Variable(2); 

Scheduler Task 3 



Supervision(); 

Deadline 

Task 1 Task 1 

Task 2 

Shared Memory 

Deadline 

Task 2 

Sampling Time (supervision) 

Task 3 

Blocked by Task 1 Deadline 

Task 3 

Task 2 



xu = A * xu + Br * ry; 

Figure 7. Real-time implementation of a state-space 

controller 

aliasing at the sampling stage, the filter must be situated 

before the sampling and it has to be analogue. 

Overlook the signal scaling. Controllers are normally 

designed by using a model that is parameterized according 

to physical or normalized units. Thus, sampled signal 

have also to be converted to the corresponding units, 

before they can be used for the control signal calculation. 

Unnecessary implementation of continuous-time controllers. 

Students frequently design a continuous-time 

controller in Simulink and then they transfer the algorithm 

to real-time target system using the Real Time 

Workshop. The consequence is that the controller is 

implemented using a fixed-step solver for differential 

equations (normally fourth-order Runge-Kutta) with a 

sampling time equal to the integration step. Thus, the realtime 

task suffers an unnecessary overload. If it is possible, 

discrete-time controllers should be implemented. 

Here it is important to remark that sometimes discretetime 

control systems perform poorer than continuoustime 

ones and increasing the sampling rate does not 

always lead to a performance improvement. Moreover, 

some problems are caused by the properties of sampling 

zeros of pulse transfer functions at high sampling 

rates. In these cases, continuous-time control should be 

applied and the above advice could be incorrect. This 

clarifies the sense of the expression “if it is possible”. 

5 Real-time platform 

Nowadays it is very difficult to choose a software/hardware 

configuration for real-time experiments because there are 

many manufacturers that offer a variety of well designed 

systems. Thus, it is necessary to be careful at the moment 

to define the specifications for such systems. 

Today it is very common to use two computers in a host/ 

target configuration to implement real-time control systems. 

The host is a computer without real-time requirements, in 

which the develop environment, data visualization and 

control panel in the form of a Graphic User Interface (GUI) 

reside. The real-time system run on the target, which can be 

a second computer or an embedded systems based on a 

board with a DSP (Digital Signal Processor), a PowerPc or a 

Pentium family processor. 

This separation is not necessary for small systems, since 

hard real-time PC operating systems such QNX ([7]), 

LynxOS and RT-Linux have solved the problem of deterministic 

response of real-time tasks, which coexist together 

with non-real-time tasks on the same computer. However, if 

the project has some spread then the host/target architecture 

brings more flexibility, order and computational power. An 

additional advantage is that the real-time system will continue 

working still in the case that the host crashes, increasing 

the reliability of the system. Requirements for a realtime 

system could be: 

Preemptive Multitasking for hard real-time requirements. 

Multitasking and multithreading are necessary if 

e.g. there are many independent control loops. It is also 

necessary to implement supervisory control as well as 

adaptive control. 

Laboratory plants do not usually need hard real-time response 

to obtain an acceptable performance for a simple 

control loop. However, this property becomes essential if 

the project includes research in the area of hybrid 

dependable systems or the algorithms should be tested 

for time-critical applications. 

POSIX compliance. Posix (Portable Operating System 

Interface) is an IEEE standard for operating systems. 

Norms 1003.1b, 1003.1d, 1003.1j specify requirements 

and compatibilities for real-time systems. Posix compliant 

software is easy to be ported. 

Support for real-time scheduling. Several algorithms are 

available for this task, e.g. RMS, EDF, MLF and MUF. 

Small latency such that sampling times in the area of 1 

ms should be possible for several control loops. 

Integration with Labview. Labview is a graphical programming 

environment from National Instrument Inc. 

that combines development with a powerful programming 

language allowing 2-D and 3-D data presentation 

and visualization. 

The use of Matlab/Simulink/RTW should not be the 

exclusive tool to implement real-time software but an 

additional facility. Therefore, a real-time operating 

system with a develop environment to write software 

is also needed. 

The above stated requirements are very hart if the acquisition 

of ready-to-use products is wanted. For example, 

although EDF, MLF and MUF are well-known scheduling 

algorithms for real-time requisites, they are hardly to find in 

commercial real-time operating systems. MLF and MUF are 

not implemented at all and EDF can be found in JBed ([20]) 

and RT-Linux ([2]). However, JBed is not Posix compliant, 

the integration with Matlab/Simulink and LabView is not 

available and only few CPUs and interface cards are supported. 

RT-Linux (or RTAI) could be a good choice if 

software drivers are available for the corresponding acquisition 

boards and the developers have enough experience 

installing RT-Linux because this activity is very cumbersome. 

A limited interface with Matlab/Simulink/RTW and 

Labview is available. 

The first software specification (multitasking/multithreading) 

excludes products like RTWT ([24]), WinCom ([25]) and

eal-time systems based on DSP board, since they are very 

limited in this aspect. Most WindowsNT-based real-time systems 

are inadequate for system with hard deadlines and 

products like InTime (from RadiSys Co.) and Hyperkernel 

(from Nematron Co.) do not support Matlab/Simulink and 

Labview. The same is valid for LynxOS ([21]). 

6 Conclusions 

In this contribution, an introduction to real-time digital 

control from an educational point of view has been given. 

Some well-known misconceptions coming from the control 

system community were clarified and common mistakes 

in the programming and in the real-time control implementtation 

have been highlighted. The relevance of the realtime 

implementation of the control system, particularly in 

case of time-critical application, can also be taken from 

the paper. 

Finally, the problem to find an adequate commercial realtime 

operating system was pointed out by summarizing the 

experience collected in this field. 

References 

[1] Åström, K. and B. Wittenmark. Computer Controlled 

Systems. Prentice Hall International, 1997. 

[2] Barabanov, M., (1997). A Linux-based Real-Time 

Operating System. M.S. Thesis at New Mexico 

Institute of Mining and Technology. 

[3] Bennet, S. Real-time Computer Control an Introduction. 

Prentice Hall International, 1994. 

[4] Burns, A. and A. Wellings. Real-time Systems and Programming 

Languages. Addison Wesley, 2001. 

[5] Cervin, A. Improved Scheduling of Control Tasks, Proc. 

11th Euromicro conference on real-time systems, 

1999. 

[6] Dertouzos, M. L. and A. K. Mok. Multiprocessor 

on_line scheduling of hard_real_time tasks. IEEE 

Transactions on Software Engineering, Vol. 15, no. 

12, 1497-1506, 1989. 

[7] Hildebrand, D., (1992). An architectural overview of 

QNX. In USENIX Workshop on Micro-Kernels and 

Other Kernel Architectures, pp. 113-126, Seattle, 

WA, April 1992. USENIX. 

[8] Houpis, C. H. and G. B. Lamot. Digital Control 

Systems. McGraw-Hill, 1992. 

[9] Katz, P. Digital Control using Microprocessors. 

Prentice Hall International, 1981. 

[10] Kim, B. K. Task Scheduling with Feedback Latency 

for Real-Time Control Systems. Proc. IEEE 5th Int. 

Conf. on Real Time Computing Systems and 

Applications, 37-41, 1998. 

[11] Leung, J.-T. and J. Whitehead. On the complexity of 

fixed priority scheduling of periodic real-time tasks. 

Performance Evaluation, 2 (4), 237–250, December 

1982. 

[12] Liu, J. W. S. Real-time Systems. Prentice Hall, 2000. 

[13] Liu, C. L., and J. W. Layland. Scheduling Algorithms 

for Multiprogramming in a Hard Real Time Environment. 

Journal of the Association for Computing 

Machinery, Vol. 20, no. 1, pp. 44-61, 1973. 

[14] Mok, A. K. Fundamental Design Problems of Distributed 

Systems for the Hard Real Time Environment. 

PhD thesis. M.I.T., 1983. 

[15] Ryu M., S. Hong, M. Saksena. Streamlining Real- 

Time Controller Design: From Performance Specifications 

to End-to-end Timing Constraints. Proc. 

IEEE 3rd Real Time Technology and Application 

Symposium, p. 1-99, 1997. 

[16] Seto D., J. P. Lheoczk y, L. Sha, and K. G. Shin. On 

Task Schedulability in Real-Time Control Systems. 

Proc. 17th Real-Time Systems Symposium, 13-21, 

1996. 

[17] Stallings, W. Operating Systems. Prentice Hall, 2001. 

[18] Stewart D. B. 30 Pitfalls for Real-Time Software Developers. 

Embedded Systems Programming. Parts 1 

and 2, vol. 12, no. 11, 32-41; no. 12, 74-86, 1999. 

[19] Stewart D. B. and P. K. Khosla. Real-Time Scheduling 

of Dynamically Reconfigurable Systems. Proc. 

IEEE International Conference on Systems Engineering, 

Dayton Ohio, 139-142, 1991. 

[20] Tryggvesson J., T. Mattsson and H. Heeb, (1999). 

JBED: Java for Real-Time Systems. Dr. Dobb's 

Journal, 1999. 

[21] Wind River Systems, Inc., 1010 Atlantic Avenue, Alameda, 

CA 94501-1147, USA. VxWorks Programmer’s 

Guide, 1993. 

[22] Wittenmark B., J. Nilsson, M. Törngren. Timing Problems 

in Real-Time Control Systems. Proc. of American 

Control Conference, 1995. 

[23] RTLinux. The Realtime Linux, www.rtlinux.org. 

[24] The MathWorks, 3 Apple Hill Drive, Natick, MA 

01760- 2098, www.mathworks.com 

[25] Quanser Consulting, 102 George Street, Hamilton, 

Ontario, Canada L8P 1E2, www.quanser.com 

[26] ECP Educational Control Products. 5725 Ostin Avenue 

Woodland Hills, CA 91367 USA, www.ecpsys.com

chapter sixteen 

Implementation of Digital Control 

Using Digital Signal Processors 

The control based on programmable digital devices such as programmable 

logic devices (PLDs), microprocessors/controllers (henceforth, 

µ-controllers), and digital signal processors (DSPs) is used widely for 

numerous applications ranging from home appliances to industry products. 

DSPs are adopted for system controllers due to their fast operation 

speed through dedicated arithmetic units with multipliers and 

fast analog-to-digital converters and digital-to-analog converters. Their 

fast operation is thought to be suitable enough for replacing the existing 

analog controllers. Of course, there are still intrinsic limitations in a 

digital controller’s bandwidth, compared to the classical analog controllers. 

In many applications, however, system designers can select either 

appropriate µ-controllers or DSPs with enough performance. In addition, 

programmable controllers provide the flexibility of easily implementing 

unexpected conditions. 

In general, in order to properly utilize DSPs as well as µ-controllers, 

designers should take a series of steps toward gathering the physical 

information about the chosen processor, software development environment, 

and interface between the processor and external circuits. The next 

step is to move on to actual implementation of the system. This chapter is 

intended to explain and provide helpful guidelines for implementation 

of a system controller based on programmable digital processors specifically 

with DSPs. For the convenience of explaining and understanding, 

a controller for a non-inverting buck-boost DC/DC converter [1]–[16] is 

presented. Some parts of the source codes and physical waveforms are 

provided. 

16.1 Introduction to Implementation of 

Digital Control Based on DSPs 

As the first stride toward the implementation of controllers using DSPs, 

the basic concepts of DSP in a hardware and software point of view, specification 

of the desired system, description of control flow based on the 

functional requirements, selection of proper µ-controllers or DSPs, and 

detail datasheets and manuals are explained. 

© 2009 Taylor & Francis Group, LLC 

273

274 Integrated Power Electronic Converters and Digital Control 

16.1.1 Basic Concepts of DSPs from Hardware 

and Software Points of View 

DSP has two meanings based on hardware and software points of view. 

In terms of hardware, literally, a digital signal processor is a kind of 

µ-processor. 

DSPs manufactured by various semiconductor companies are presented 

in Table 16.1. The examples of DSP chips supplied by manufacturers 

are shown in Figure 16.1. The chips have leads to exchange digital or 

analog signals with external circuits. The chips are soldered on printed 

circuit boards (PCBs). Once DSP chips are powered, they begin to execute 


Table 16.1 DSP Hardware Manufacturers 

Manufacturer 

Advanced Devices, Inc. 

Advanced RISC Machines 

Analog Devices 

AverLogic Technologies, Inc. 

DSP Group 

Freescale Semiconductor, Inc. 

Hyperstone 

IDT 

Infineon Technologies 

Intersil 

Intrinsity, Inc. 

Logic Devices 

LSI 

MicroChip 

NXP 

STMicroelectronics 

Texas Instruments, Inc. 

VeriSilicon 

Vitesse Semiconductor Corporation 

Zilog 

Remarks 

16/32 bit/floating point 

(ARM) CPU core vendor 

16/32 bit DSP–SHARC 

32-bit embedded processors– 

uP/68000–uCRISC/DSP combo ICs 

RISC/DSP combo ICs 

Packet classification processors 

8/16 bit CMOS uP 

DSP devices 

dsPIC 16-bit RISC digital signal 

controllers 

TI320Cxx DSP processors-high speed 

CMOS signal processing/all-digital 

down/up-converters, digital filters, 

high-speed QAM modem chip sets 

DSP coprocessor, VoIP 

DSP-based T3/E3 transceiver 

16-bit multi-purpose DSP 

manufacturer 

Source: Davis, L. 2008. DSP processor vendors. http://www.interfacebus.com/Digital_ 

Signal_Processor_Manufacturers.html.

Chapter sixteen: Implementation of Digital Control 275 

(a) TMS320F243PGE 

(b) TMS320F2812PGFA 

Figure 16.1 DSP chip (manufactured by Texas Instruments) examples. 

the codes programmed by the designers in phase with the clock signals 

from crystal oscillators or resonators. 

From a software perspective, digital signal processing is said to be 

DSP, which means a series of procedures composed of algorithms and 

software codes. In other words, DSP is about how to obtain the system 

desired analog/digital output signals from the analog/digital input signals. 

The procedures of DSP can be summarized as 

© 2009 Taylor & Francis Group, LLC


1. Capturing analog/digital input signals (sample and hold) from hardware 

pins through external interface circuits 

2. Acquiring the digital data from the sampled signal through an analog-to-digital 

converter (ADC) 

3. Carrying out operations and calculations with the converted data 

and making digital results—either integer, fixed point, or floating 

point calculations 

4. Converting the digital results into the system desired analog signals 

through digital-to-analog converters (DACs) or digital output ports 

Figure 16.2 presents overall flows of program execution procedures 

after the DSP chip is powered. Figure 16.3 shows a diagram explaining 

digital signal processing including the DSP chip and the mounted DSP 

user program. 

16.1.2 Specifications of Desired System 

The non-inverting buck-boost DC/DC converter is used as an implementation 

example. The first step is to specify the functional requirements. 

Clarifying the specifications is the most important job for designers. 

Power on 

Boot code 

performed 

Initializing 

interrupt service 

vectors 

Initializing internal 

H/W architectures 

of the DSP chip 

Initializing the 

parameters of 

user program 

Interrupt Service Routines 

(ISRs) 

ISR1 

(Communication) 

ISR2 

(Timer/counter) 

ISR3 

(ADC) 

ISR4 

(External signals) 

ISRn 

(Other sources) 

User program 

running 

Data memory 

(Parameters/variables stored) 

Figure 16.2 General flow of source codes execution on DSP chips. 



Periodic (timer) interrupt request 

every control period (in ms, us, …) 

Digital inputs 

Analog inputs 

Sample and 

hold 

ADC 

n-bit internal data 

memory 

S/W 

filter 

Input pins 

n-bit data memory 

(variables) 

Operations and 

calculations 

according to user 

procedures 

DAC 

Analog outputs 

Digital outputs 

Control parameters 

(data memory) 

Output pins 

Figure 16.3 Overall flow of digital signal processing. 

Through specifications, designers can break the project into sub-projects 

and assign individual jobs to team members. This helps integrate and 

evaluate the individual jobs. 

16.1.2.1 Functional Requirements of Noninverting 

Buck-Boost Converter 

The electrical specifications of a non-inverting buck-boost converter are 

provided in Table 16.2. The overall system block diagram is presented in 

Figure 16.4, where the error amplifier and PWM generator are achieved 

by digital components such as DSP chip and user program and PLDs. 

Basically, the non-inverting buck-boost converter can have three operating 

modes: buck, boost, and buck-boost. The buck-boost mode is lossy 

compared to the other modes. 

16.1.2.2 Modeling and State Block Diagram of Converter 

The electrical specifications are the same as the parameters presented in 

Table 16.2 and Figure 16.4. The second step is to build the state block diagram 

of the converter by deriving the system model. Figure 16.5 presents 

the equivalent circuits of the operating modes in each switching period. 

The buck operation and boost operation modes do not appear at the same 

control period. To model the non-inverting buck-boost converter, state 

space averaging technique [18] is introduced as follows. 

For small signal modeling [18], 



Table 16.2 Electrical Specification of Non-inverting Buck-Boost Converter 

Input voltage 

V in = 4.2 V ~ 2.5 V 

Output voltage 

V o = 3.3 V 

Inductor 

L = 100 uH 

Output capacitor 

C = 330 uF 

Load 

R = 4.7 Ω 

Switching frequency 

f s = 100 kHz 

Minimum effective duty cycle D min_eff = 6.265% 

Maximum effective duty cycle D max_eff = 98.67% 

iL = IL + % i L , vo = Vo+ % v o , vin = Vin + % v in , 

% 

v in ⊕0 

d = D + d 

% 

= d ʺ1 , d = D + d 

% 

= d −1≥ 

0 

buck buck buck ctrl 

boost boost boost ctrl 

dbuckboost = Dbuckboost + d 

% buckboost 

(16.1) 

For buck operation, the transfer functions and DC gains are 

diL 

1 

= ( 

dt L d buck v in − v o ) 

(16.2) 

dvo 

1 

dt C i o 

= ( L − ) 

vR 

(16.3) 

1 

v% 

s LC V in 

o() 

d% 

buck() s 

= 2 1 

s + 

RC s 1 

+ 

LC 

(small signal model) 

(16.4) 

v% 

o() 

0 

= Vin 

(small signal DC-gain) 

d% 

buck() 

0 

(16.5) 



i in 

Buck 

switch 

L 

i L 

D 2 

i o 

+ 

Q 1 

Q 2 

v o 

v in 

+ 

– 

D 1 

Boost 

switch 

C 

Load 

R 

– 

V ref 

v o 

Error 

amplifier 

G 1 G 2 

v ctrl PWM 

generator 

(a) The Converter 

v ctrl 

0 

T s 

v buck_ctrl = v ctrl 

v H 

v mod 

v boost_ctrl = v ctrl -v mod 

v L 

G 1 

Buck Boost 

G 2 

0 

Time (s) 

(b) PWM Modulation Strategy (8) 

Figure 16.4 Non-inverting buck-boost converter. (a) Converter, (b) PWM modulation 

strategy [8]. 

1 

V s LC V in D buck 

o()= 

2 1 

s + 

RC s 1 

+ 

LC 

(large signalmodel), 

(16.6) 



L 

i in Q1 

D 2 

i L 

Buck 

i c 

switch 

+ 

Boost 

v in – D 1 switch 

Q 2 

C 

i o 

+ 

v o 

Load 

L 

i 

D in Q1 

2 

i L 

Buck 

i c 

switch 

+ 

Boost 

v in – D 1 switch Q 2 

C 

i o 

+ 

v o 

Load 

– 

(a) Buck Operation 

– 

L 

i in Q 1 

i 

Buck L 

D 2 

i c 

switch 

+ 

Boost 

v in – D 1 switch Q 2 

C 

i o 

+ 

v o 

Load 

L 

i in Q1 

D 2 

Buck i L 

i c 

switch 

+ Boost 

v in – D 1 

Q 

switch 2 

C 

i o 

+ 

v o 

Load 

– 

(b) Boost Operation 

– 

Figure 16.5 Equivalent circuits of operating modes. 

Vo() 

0 = VinDbuck 

(large signal DC-gain) (16.7) 

For the boost operation, the transfer functions and DC gains are 

diL 

1 

= [ 

dt L v in −( 1− 

d boost) v o] 

(16.8) 

dv 

dt 

o 

1 vo 

= [( 1 −dboost 

) iL 

− ] 

C 

R 

(16.9) 

' 

Dboost 

v s LC V ILs 

% 

o − 

o() 

= 

C 

d 

% 

' 2 

boost () s 

s 

RC s D 

+ + 

LC 

2 1 boost 

v% 

o() 

0 Vo 

Vo 

= = (smallsignalDC-gain) 

d% 

' 

boost () 0 D 1 − Dboost 

boost 

(16.10) 

(16.11) 



1 

V s LC V in( 1− 

D boost ) 

o() 

= 

1 

s 

RC s 1 

+ + ( 1 − Dboost 

) 

LC 

2 2 

(large signal model) 

(16.12) 

V 

o 

Vin 

() 0 = (large signal DC-gain) 

1 − D 

boost 

(16.13) 

The DC gain (steady-state characteristic) of the non-inverting buckboost 

converter based on equations (16.1) to (16.13) is plotted in Figure 16.6. 

In particular, the fact that the steady-state characteristic is continuous in 

the neighborhood of d ctrl = 1 helps designers construct a single controller 

for the converter with two different operating modes. Even in small signal 

DC gain in equations (16.5) and (16.11), continuity can be found when D boost 

= D ctrl – 1 = 0. 

Figure 16.7 shows the state block diagram constructed based on the 

state space averaged differential equations (16.2) to (16.9). The converter 

output voltage can be adjusted by two parameters d buck and d boost . The 

construction of the state block diagram provides intuitive information 

about input (feedback) and output signals from the controller. As seen in 

Figure 16.7, the controller uses v o and v o_ref as a feedback and the desired 

output voltage as input signals, respectively. These two signals are processed 

according to the user procedures as presented in Figure 16.3. The 

output signals d buck and d boost are given in the form of digital pulse stream, 

which has a fixed frequency and variable pulse width. 

V o 

1.0 

3 

2 

Boost region 

d boost = d ctrl – 1 > = 0 

V o = 2V in 

1 

V o = V in 

Buck region 

d buck = duty ctrl 

0 

0.0 0.2 0.4 0.6 0.8 1.2 1.4 1.6 

Duty d ctrl 

Figure 16.6 DC gain of large signal model. 



v in 

Converter 

d buck 

+ 

1/s 1/L 

i L (1–d boost ) 

+ 

v L –(1 – d boost ) 

+ 

+ 

i c 

1/s 

1/C 

v o 

–1/R 

d buck 

v o_ref 

System 

controller (DSP) 

d boost 

v o 

Figure 16.7 State block diagram of system. 

16.1.3 Control Flow Based on State Block Diagram 

The controller of the system ranges from the traditional PID to the modern 

techniques such as sliding mode control and adaptive control [19]. 

The state block diagram provides helpful information in selecting the 

preferred technique. As an example, a PI controller is introduced in this 

section. 

Figure 16.8 presents the control flow of a classical PI control with antiwindup 

and the analog implementation of PWM modulation based on 

Figure 16.4. In the PWM modulator, d boost must be less than one to prevent 

the inductor current i L from being extremely high in boost operation 

mode. In other words, v ctrl is always lower than 2v mod as seen in Figure 16.8. 

The conversion of the control flow into the discrete control follows the 

control flow diagram. The sampling periods of each control loop, system 

stability, and control gains can be selected using various discrete control 

techniques [20]. 

16.1.4 Selection of DSP and µ-Controller 

16.1.4.1 Guidelines for DSP Selection 

For proper hardware interface, data types (flags, n-bit integer data, fixedpoint 

data, and floating point data), the necessary hardware architecture, 

and input/output port should be defined with respect to the system 

requirements. The DSP chip or µ-controller manufacturers provide the 

information covering available data types, dedicated multiplier, and builtin 

internal architectures of their chips. Selection of appropriate DSP chip 

and µ-controller should consider the following criteria: 



PI-control 

PWM Modulator 

1/s K i 

v o_ref v err Kp 

+ 

+ 

v ctrl 

+ 

– 

v boost 

v buck 

d boost 

d buck 

v o 

v mod 

Figure 16.8 Control flow diagram. 

1. Build an input/output signal specification table. 

• How many inputs and outputs are necessary? 

• Are the signals analog or digital (ADC/DAC/digital IO ports)? 

• What are the feasible voltage and current ranges of each input 

and output port? 

2. What and how many operations/calculations does your controller 

need? 

• Integer/fixed point/floating point operations/calculations (8 bit, 

16 bit, 32 bit, and 64 bit) based on your control routines. 

3. How many “millions of instruction per second” (MIPS) are available 

from the DSP? 

• The faster (shorter) control period your system requires, the higher 

MIPS is necessary on the average. (It is recommended to track the 

number of instructions performed within that control period.) 

• Available MIPS generally tends to be increased by available 

clock speed (dependent on crystals and/or oscillators) of the DSP 

chips. 

4. How much and what types of memory are available (size and types 

of data and program memory; Figure 16.9)? 

5. What specific/special functions does your system require from the 

DSP chip? 

• Timer/counter, external interrupt request, analog-to-digital 

converter, digital-to-analog converter, up/down counter for 

two-phase incremental encoder signal, symmetric space vector 

PWM output for motor control, communication protocol (asynchronous/synchronous, 

CAN, I 2 C, TCP/IP, etc.), program downloading 

(via JTAG, RS-232, and so on). 

6. Other requirements (cost, physical dimension, soldering conditions, 

etc.)? 

16.1.4.2 Selection of DSP Chip 

We now consider estimation of operation/calculation load and data types. 

Based on the control flow diagram in Figure 16.8, the difference equations 

for DSP can be derived as 



Program Memory 

ROM 

(Fixed codes/data) 

Data Memory 

RAM 

(Variable codes/data) 

Flash ROM 

(EEPROM) 

Static RAM 

EPROM 

Pseudo static 

RAM 

PROM 

(OTP) 

Dynamic RAM 

(Refresh required) 

MASK ROM 

(For final mass 

production) 

Figure 16.9 General criteria of memory types. 

verr[ kTs] = vo_ 

ref [ kTs] − vo[ kTs 

] 

(16.14) 

k 

ctrl s p err s i• 

err s 

n= 

v [( k+ 1) T ] = K v [ kT ] + K v [ nT ] 

0 (16.15) 

vctrl[( k+ 1 ) Ts] ʺ Vctrl 

_max 

(16.16) 

v [( k+ 1) T ] = v [( k+ 1) T ] 0ʺ v [( k+ 

1) 

T s ]ʺ 1 

buck s ctrl s buck 

(16.17) 

vboost[( k+ 1) Ts] = vctrl[( k+ 1) Ts] −Vmod 

0 ʺ vboost[( k+ 1) T s ] < 1 

(16.18) 



vbuck[( k+ 

1) Ts 

] 

dbuck[( k+ 1) Ts 

] = 

V 

mod 

(16.19) 

vboost[( k+ 

1) Ts] 

dboost[( k+ 1) Ts] 

= 

V 

mod 

(16.20) 

where v o_ref [kT s ], v o [kT s ], K p , K i , and T s are the sampled output reference voltage, 

output voltage, proportional gain, integral gain, and sampling period, 

respectively. Equations (16.14) to (16.20) are performed in every sampling/ 

control period (set by timer interrupt request) by the DSP or µ-controller. 

Based on the electrical specification in Table 16.2, the switching frequency 

f s is 100 kHz, which means T s = 10 µs. In other words, the operations/calculations 

and comparisons for discrete control routine must be 

able to be completed within 10 µs. However, the execution time should 

not exceed the half sampling period, since the subroutines in the user 

program have to be executed during the idling time of control routines. 

As a result, the total execution time of a control routine must be shorter 

than 5 µs. If the type of data is 16-bit integer then the DSP should be able 

to perform 16 × 16 multiplication and 32/16 division by using either the 

dedicated architecture or software library. In the case that either the fixed 

or floating point data are required, the DSP should have capabilities in the 

fixed/floating point multiplication and divisions through the specialized 

arithmetic units or software library. 

Through the manufacturers’ specification tables, many different DSP 

chips can be chosen. For the example of non-inverting buck-boost converter, 

TMS320F2812 by Texas Instruments has been chosen. TMS320F2812 

has 150 MIPS, which would be enough for the discrete control of the motor 

drive, inverter, and converter. TMS320F2812 has a dedicated multiplier 

inside the chip and provides the library for floating point operation. Also, 

the furnished flash read-only memory (ROM) for program memory gives 

a chance for the user to revise the system program easily. 

16.1.5 Detailed Datasheets and Manuals 

In order to properly utilize the selected DSP or µ-controller, the designer 

needs to gather the detail electrical datasheet, various application notes, 

and manuals regarding the software development environment. First of 

all, a good understanding of the internal architecture and electrical specification 

of the DSP is very important for the system hardware designing 

and for the software development. 



In order to properly use a DSP chip, the designer needs several materials 

explaining 

• Internal hardware and electrical specification of DSP chips 

• Using the compiler/linker to generate user program code (assuming 

compiler/linker/unified software development environment 

is provided) 

• Downloading or writing code to the DSP chip (assuming downloading 

tools are provided) 

• Initializing and utilizing internal peripherals of DSP using software 

• Changing the booting mode when power is on 

• Using a starter-kit for beginners (easier way to approach the DSP 

chip) 

• Application notes associated with users’ applications 

The designer should be familiar with C/C++ languages or assembly languages 

compatible with the selected DSP chip. 

16.1.5.1 Internal Architecture and Electric Specifications 

The data manual includes overall and detail information on the DSP 

chip. Figure 16.10 shows the architecture of the selected DSP chip. 

For the TMS320F2812 chip, the manufacturer provides the literature 

SPRS174M, which is named TMS320F2810, TMS320F2811, TMS320F2812, 

TMS320C2810, TMS320C2811, TMS320C2812 Digital Signal Processors 

Data Manual. Using this material, the designer can find what internal 

hardware function is available and which more detailed manual is 

necessary. 

Table 16.3 presents several materials related to TSM320F2812 hardware. 

The shaded materials are recommended to read for the implementation 

of a digital controller of a non-inverting buck-boost converter. The 

designer can easily find this literature on the Texas Instruments Web 

site. 

16.1.5.2 Software Development Environment (Assembler, 

Compiler, Linker, and Downloader) 

With the hardware manuals of the selected DSP chip or µ-controller, the 

designer should have enough materials explaining the software development 

environment. As a rule, these materials consist of the assembler, 

compiler, linker, program downloader, and the unified development tool 

manuals. The unified development tool helps the user perform all the 

processes to generate from the source codes to the final execution codes. 

In the case of the Texas Instruments DSP products, the manufacturer 



Memory Bus 

MUX 

CPU Timers 

Timer 0 

Timer 1 

Timer 2 

Peripheral IRQ 

controller 

Internal Peripherals 

CPU Level 

IRQ 

Controller 

INT[12..1] 

INT13 

IN14 

NMI 

Real Time JTAG 

External 

Interface 

Control 

Address 

Data 

1. External IRQ 

controller 

XINT1/2/13, XNMI 

C28x CPU 

Core 

Internal 

Memory 

GPIO Pins 

GPIO MUX 

2. Communications 

SCIA/SCIB 

SPI 

MCBSP 

CAN 

3. Event managers 

(Timer/Counter) 

EVA/EVB 

1. Data 

memory 

SARAM 

M0: 1k × 16 

M1: 1k × 16 

L0: 4k × 16 

L1: 4k × 16 

H0: 8k × 16 

16 Channels 

4. ADC 

12-bit ADC 

2. Program 

memory 

X-tal/Oscillator 

System Control 

Oscillator and PLL 

Peripheral clocking 

Low power modes 

Watchdog 

/Reset 

CLKIN 

Flash ROM 

ROM 

OTP 

Boot ROM 

Figure 16.10 Overall internal architecture of TMS320F281x DSP. 

supplies the unified tools in its Code Composer Studio (CCS). Even 

though the designer develops the software for the DSP chip on the basis of 

the unified tools, it is still recommended for the designer to have enough 

knowledge of the assembler, compiler, linker, and program downloader 

manuals. Figure 16.11 presents the software development flow based on 

CCS. This flow is also similar to other unified development tools provided 

by different DSP chip manufacturers. Table 16.4 lists the materials to be 

consulted. 

16.1.5.3 Commercial DSP Starter Kit 

The commercial DSP starter kit is very useful in providing required information 

for beginners. The kit provides a DSP board on which various 

test pins/ports are available for the user to get basic experience in handling 

and understanding of the selected DSP’s functions. Most beginners 

would be advised to utilize the starter kit and implement several functional 

requirements. Designing and building custom DSP boards based 

on system requirements is very useful; however, the processes require 

experience. Various starter kits are available, depending on the provided 



Table 16.3 Materials Related to TMS320F1812 Hardware 

Title 

TMS320F2810, TMS320F2811, TMS320F2812, TMS320C2810, 

TMS320C2811, TMS320C2812 Digital Signal Processors Data 

Manual 

TMS320x28xx, 28xxx DSP Peripheral Reference guide (Rev. F) 

TMS320x281x System Control and Interrupts Reference Guide (Rev. E) 

TMS320x281x Multichannel Buffered Serial Port (McBSP) 

Reference Guide (Rev. C) 

TMS320x281x Event Manger (EV) Reference Guide (Rev. E) 

TMS320x281x, 28xxx Serial Peripheral Interface (SPI) Reference 

Guide (Rev. D) 

TMS320x28xx, 28xxx Enhanced Controller Area Network (eCAN) 

Reference Guide (Rev. E) 

TMS320x281x Analog-to-Digital Converter (ADC) Reference Guide 

(Rev. D) 

Literature 

No. 

SPRS174M 

SPRU566F 

SPRU078E 

SPRU061C 

SPRU065E 

SPRU059D 

SPRU074E 

SPRU060D 

F2810, F2811, and F2812 ADC Calibration SPRA989A 

TMS320x28xx, 28xxx Serial Communication Interface (SCI) SPRU051B 

Reference Guide (Rev. B) 

TMS320x28x DSP CPU and Instruction Set Reference Guide (Rev. D) SPRU430D 

TMS320x281x Boost ROM Reference Guide (Rev. C) 

SPRU095C 

TMS320x281x External Interface (XINTF) Reference Guide (Rev. C) SPRU067C 

Source: Texas Instruments. 2008. Technical documents: C2000TM high performance 32-bit 

controllers—tools user guide. http://focus.ti.com/dsp/docs/dspsupporttechdocs. 

tsp?sectionId=3&tabId=409&techDoc=6&familyId=1406&documentCategoryId=6 

&toolTypeId=0&viewType=0&toolTypeFlagId=2. 

functions, cost, and downloading tools. Texas Instruments provides the 

information of starter kits [23]. 

16.1.5.4 Application Notes 

Based on the selected DSP chip or µ-controller, the manufacturers 

provide a wide range of application notes to promote the sale of their 

products [24]. The application notes cover fields such as motor control, 

communication, image processing, inverter/converter control, temperature 

control, battery charger, automotive systems, display device control, 

and numerous other applications. Usually, a user is able to find the 

applicable notes on the chip manufacturer’s Web site. The exact application 

and technique might be different. Nevertheless, the application 

notes will provide the user with helpful information. 



Macro source 

code files 

C/C++ source 

code files 

Archiver 

Macro 

library 

C/C++ 

compiler 

Assembler 

source code files 

Assembler 

Main flow of 

software 

development 

Link 

command file 

Unified development tool on PC 

Archiver 

COFF object 

code files 

Library-build 

utility 

Library of object 

code files 

Linker 

Run-timer 

support library 

Hex-conv. util. 

(installed on PC) 

Post-link 

optimizer 

Debugging tools 


EEPROM 

programmer 

Executable 

COFF code 

files 

Downloading util. 


Programmed 

EEPROM 

Downloader 

(JTAG, SCI) 

C281 × board 

F281 × board 

Figure 16.11 Overall internal architecture of TMS320F281x DSP. 

16.2 Hardware Schematic Design of Noninverting 


and DSP Control Board 

In this section, actual circuit diagrams and their explanations are presented 

for the purpose of PCB implementation. It is assumed that the designer 

has proper knowledge of the selected DSP chip and software development 

environment. In addition, the designer has enough knowledge of control 



Table 16.4 Materials Associated with Software Development Environment [22] 

Title 

Code Composer Studio Development Tools v.3.1 Getting Started Guide 

(Rev. H) 

TMS320C28x Optimizing C/C++ Compiler User’s Guide (Rev. C) 

TMS320C28x Assembly Language Tools User’s Guide (Rev. C) 

TMS320F29xx SDFlash Serial RS232 Flash Programming Reference 

Guide 

IQmath Library (A Virtual Floating Point Engine) Module User’s 

Guide 

Literature 

No. 

SPRU509H 

SPRU514C 

SPRU513C 

object and control scheme. The circuit diagrams show the non-inverting 

buck-boost converter and the connectivity between the DSP chip and 

external circuits. The external circuits include the analog signal interface, 

digital signal interface, low-voltage power circuit, booting mode selecting 

circuit, RS-232 serial communication circuit, serial D/A converter, serial 

EEPROM, and JTAG interface circuit. 

16.2.1 Schematic for Non-inverting Buck-Boost Converter 

The beginning of design of a DSP chip or µ-controller is to draw schematics 

of the object to be controlled. Thus, the schematic is derived from 

Figures 16.4 and 16.5. The selection of components such as switches, diodes, 

resistors, inductors, and capacitors are based on the designer’s preferences 

and circuit parameters [18]. For real component selection, the designer 

needs various component parameters such as the range of operating voltage/current/power, 

heat radiation, frequency characteristics, switching 

time, parasitic RLC values, and costs. In the provided schematics, all of 

the parameters have been based on the author’s preferences. Figure 16.12 

presents the schematic of the non-inverting buck-boost converter where 

G 1 , G 2 , v in , v o , and v o_fbk are identified as the buck switch gate signal, boost 

switch gate signal, converter input voltage, output voltage, and output 

voltage feedback signal, respectively. The circuit is only for explanation 

purposes. 

16.2.2 Selected DSP Chip Connectivity 

Figure 16.13 shows TMS320F2812 DSP chip connectivity. The electrical 

specification of the chip datasheet or manual must be carefully reviewed 

so that proper signal exchanges are kept within the maximum electrical 

ratings. 



1 

2 

J3 

EH-2P 

+15V 

–15V 

+3.3V 

Vo_fbk 

GND 

U1 

6 

MC34071 

+ 

– 

3 

2 

C7 

0.1uF 

50V 

4 

5 

7 

1 

Q1 

IRF540 

Vin = 4.2~2.7V 

R1 

10k 

J1 

XH-2P 

1 

2 

C1 

0.1uF 

50V 

+ C2 

680uF 

25V 

G1 

J5 

1 

2 

3 

4 

5 

6 

D2 

1n5817 

EH-6P 

D3 

1n5817 

Figure 16.12 Non-inverting buck-boost converter. 

L1 

100uH 

D1 1N5817 

R2 

10k 

Q2 

IRF540 

1 

2 

J4 

EH-2P 

G2 

Voltage 

feedback 

R6 

1k 

(a) The Designed Schematic 

Vo=3.3V 

+ C3 

330u 

25V 

C5 

0.1uF 

50V 

C4 

0.1uF 

50V 

R3 

10k/1% 

R4 

10k/1% 

R5 

100 

C6 

0.1uF 

50V 

1 

2 

Load 

J2 

XH-2P 



(b) The Built Converter 

Figure 16.12 (continued) 

Figure 16.13 TMS320F2812 DSP chip connectivity. 



16.2.3 Analog and Digital Signal Interface 

Figure 16.14 provides the interface circuits between DSP and the external 

digital/analog signals. The external digital/analog signals are composed 

of gating PWM signals, gating logic control signals, output voltage feedback 

signal, and low voltage power lines. Through the filtering functions 

of these circuits, the DSP chip is protected from the line electromagnetic 

interference (Line EMI) and voltage/current surges. 

16.2.4 Low Voltage Power and DSP Chip Reset Circuit 

Figure 16.15 is the circuit to power the DSP control board and auxiliary 

power for the non-inverting buck-boost converter. The supplied voltages 

are +15 V, –15 V, +5 V, +3.3 V, and +1.8 V where +15 V, –15 V, and +5 V 

have another purpose: to interface with external circuitries such as the 

analog amplifier, current sensors, MOSFETs, transistors, and TTL/CMOS 

components. Figure 16.15a is the circuit for +15 V, –15 V, and +5 V supply. 

Figure 16.15b shows the +3.3 V and +1.8 V circuit to power the DSP chip. 

Along with designing hardware schematics, the designer needs to complete 

voltage maps depicting the power line connections in the hardware 

DSP Chip 

+3.3V and +1.8V 

Can be replaced by the 

open drain/collector 

FETs/transistors 

Digital signal 

pins 

Analog signal 

pins 

Make sure the 

current ratings 

Make sure the 

current ratings 

CMOS/TTL 

Buffer gates 

(+5.0V supplied) 

CMOS Buffer 

gates 

(~+15.0V supplied) 

3.3V Signal limiter 

3.0V Signal limiter 

+3.3V 

Circuitries 

+5.0V 

Circuitries 

~+15.0V 

Circuitries 

Other 

circuitries 

(a) An Electrical Signal Interface Diagram Between DSP Chip and External Circuitries 

Figure 16.14 Digital/analog signal interface. (a) An electrical signal interface diagram 

between DSP chip and external circuitries, (b) circuit schematic. 



+3.3V 

U2 

3 

5 

Y8 

7 

Y7 

9 

Y6 

12 

Y5 

14 

Y4 

16 

Y3 

18 

Y2 

Y1 

A8 

A7 

A6 

A5 

A4 

A3 

A2 

A1 

1OE 

2OE 

SN74HC244 

17 

15 

13 

11 

8 

6 

4 

2 

1 

19 

C56 

104 

50V 

GND 

GPIOA8-CAP1_QEP1 

GPIOA9-CAP2_QEP2 

GPIOA10-CAP3_QEPI1 

GPIOA11-TDIRA 

/C_CUT 

C_LMT_LCH 

C_OCP_LCH 

AC_CHK 

GPIOB6-T3PWM_T3CMP 

GND 10 

20 

VCC 

+5V +15V 

+15V 

J1 

PWM2 

OPMD_SEL5 

OPMD_SEL0 

OPMD_SEL2 

OPMD_SEL3 

C_LMT_LCH 

C_OCP_LCH 

R66 2k 

R67 2k 

L1 

L3 

L5 

L7 

L8 

L10 

L12 

BEAD 

BEAD 

BEAD 

BEAD 

BEAD 

BEAD 

BEAD 

1 2 

3 4 

5 6 

7 8 

9 10 

11 12 

13 14 

15 16 

17 18 

19 20 

GND 

L2 BEAD 

L4 BEAD 

L6 BEAD 

L9 BEAD 

L11 BEAD 

L13 BEAD 

2k 100 

PWM1 

OPMD_SEL4 

OPMD_SEL1 

C_RESET 

/C_CUT 

C_REF 

GND 

GND 

RA-20P 

TRIAC_HV 

TRIAC_BAT 

TRIAC_AC 

R68 10k 

Place 1N4448 of FairChild 

for Clamping Diodes between +3.3V and GND. 

+3.3V C57 

C_RESET 

104 

U1 

50V GND 

J2 

+15V 

17 

GPIOA0-PWM1 

1 +15V 

Y8 A8 

15 

GPIOA1-PWM2 

2 L14 BEAD 

Y7 A7 

13 

GPIOA2-PWM3 

3 L15 BEAD 

Y6 A6 

11 

Y5 A5 

GPIOA3-PWM4 

4 L16 BEAD 

8 

Y4 A4 

GPIOA4-PWM5 

5 

6 

Y3 A3 

GPIOA5-PWM6 

4 

Y2 A2 

GPIOA6-T1PWM_T1CMP 

EH-5P 

GND 

+3.3V 

VCC 

GPIOA12-TCLKINA 

GPIOA13-C1TRIP 


20 

GPIOA7-T2PWM_T2CMP 

2 

A1 

Y1 

OPMD_SEL0 

OPMD_SEL1 

OPMD_SEL2 

OPMD_SEL3 

OPMD_SEL4 

OPMD_SEL5 

PWM1 

PWM2 

3 

5 

7 

9 

12 

14 

16 

18 



GPIOB6-T3PWM_T3CMP 

1OE 

19 

2OE 

SN74HC244 

1 

GND 10 

GND 

Place 1N4448 of FairChild 

for Clamping Diodes 

between +3.3V and GND 

+3.3V 

–15V 

R3 10k 

AC_CHK 

ADCINA1 

ADCINA2 

ADCINA3 

ADCINA4 

ADCINA5 

ADCINA6 

ADCINA7 

R5 

R6 

R7 

R8 

R9 

R10 

R11 

R12 

1k 

1k 

1k 

1k 

1k 

1k 

1k 

1k 

L17 BEAD 

L18 BEAD 

L19 BEAD 

L20 BEAD 

+15V 

+15V 

–15V 

+3.3V 

_AC_CHK 

_AC_SYNC 

_Vbatt 

_Vhv bus 

GND 

J3 

1 

2 

3 

4 

5 

6 

7 

8 

EH-8P 

J4 

L21 BEAD 

L22 BEAD 

L23 BEAD 

L24 BEAD 

+15V 

–15V 

Iin 

Ibatt 

Ihv_bus 

Theat_sink 

GND 

1 

2 

3 

4 

5 

6 

7 

EH-7P 

(b) Circuit Schematic 

Figure 16.14 (continued)


J5 

VH-2P 

1 

2GND 

+15V 

C4 

1000uF 

25V 

1 

5 

U9 

LM2576T-ADJG 

V IN 

OUTPUT 

2 

D1 

MUR415G 

1 

R20 1K, 1% 

L29 

100uH 4.6A 

2100HT-101-H-RC 

C2 2 

330uF 

25V 

+ 

2 

3 

4 

FB 

C3 

104 

50V 

ON/OFF 

L25 

100uH 4.6A 

2100LL-101H-RC 

1 2 

+ 

R14 

3K 

R15 

68 

R13 

3k 

R16 

1K 

C6 

104 

50V 

LED1 

YEL 

R17 

470 

+15V 

+5V 

561-2601-100 

LED2 

RED 

TP2 

TP3 

C7 

104 

50V 

GND 

561-2101-100 

C16 

104 

50V 

C17 

330uF 

50V 

6 

4 

5 

U10 

VIN 

GND 

COMP 

MC34063ECN 

TCAP 

IPK 

IDC 

ISWC 

ISWE 

R21 11K, 1% 

R22 1, 1% 

R23 1, 1% 

R24 1, 1% 

R25 1, 1% 

R26 1, 1% 

3 

7 

8 

1 

2 

C15 

102 

50V 

C5 

1000uF 

25V 

D2 1N5819 

L28 

1.0uH 1A 

LQH32CN1R0M53L 

Murata 

–15V 

TP4 

C23 

104 

50V 

R19 

3.0k 

LED3 

YEL 

561-2601-100 

(a) +15V, –15V, and +5V Supply Circuit 

Figure 16.15 Low voltage supply circuits. (a) +15 V, –15 V, and +5 V supply circuits, (b) +3.3 V and +1.8 V supply circuits. 



LED4 

GRN 

+5V 

R28 

470 

+1.8V 

GND 

POWER FOR VDD(1.8V) and VDDIO(3.3V) 

+3.3V 

R27 

+3.3V 

U11 

10k 

R29 C24 + C25 

1 

28 

10K 

104 

2 

NC /RESET1 

27 

R31 30.1K 1% 

47uF 50V 

3 

NC 

NC 

26 

R30 16V 

4 

GND1 NC 

25 

+3.3V +1.8V 

U12 

1.5K 1% 5 

/EN1 FB1/SENSE 

24 

R32 

1 

5 

6 

IN1 

OUT1 

23 

16.9K 1% 

2 

CT VDD 

Q1 

C26 

7 

IN1 

OUT1 

22 

GND 

4 BSS138 

104 

8 

NC /RESET2 

21 

3 

RESETn 

1 

50V 

9 

NC 

NC 

20 

MRn 

10 

G ND2 NC 

19 

R39 

11 

/EN2 SENSE2 

18 

C27 + C29 C28 + 

TPS3838K33DBV 2.0K 1% 

12 

IN2 

OUT2 

17 

104 

13 

IN2 

OUT2 

16 

22uF 50V 22uF 

14 

NC 

NC 

15 

6.3V 

6.3V 

NC 

NC 

GND 

TPS767D301 

GND GND 

+3.3V 

C3 8 

104 

50V 

C39 

104 

50V 

C40 

104 

50V 

C41 

104 

50V 

C44 

104 

50V 

GND 

C46 

104 

50V 

C49 

104 

50V 

C50 

104 

50V 

GND 

R38 

0 

C31 

1uF 

16V 

+ 

GND 

FOR VDDIO1~VDDIO5 

(NEAR VDDIO1~VDDIO5) 18.2K: 1.899V 

16.9K: 1.848V 

15.0K: 1.773V 

13.7K: 1.722V 

/DSP_RESET 

3 

VDD3VFL 

2 

C51 

22uF 

6.3V 

+ 

C52 

22uF 

6.3V 

+ 

C3 7 

10 4 

50V 

FOR VDD2~VDD10 

(NEAR VDD2~VDD10) 

C42 

104 

50V 

C43 

104 

50V 

C45 

104 

50V 

C53 

22uF 

6.3V 

+ 

C47 

104 

50V 

C48 

104 

50V 

C30 

104 

50V 

C32 

104 

50V 

(b) +3.3V and +1.8V Supply Circuit 




schematic. On the basis of voltage maps, the circuit is divided into several 

parts and the interface is clarified. 

16.2.5 Boot Mode Selecting Circuit 

The boot mode selecting circuit is used to set the DSP’s operations right 

after power is on (Figure 16.16). The operations include µ-processor or 

µ-controller mode selection, PLL mode selection, and booting code operation. 

The µ-processor mode/µ-controller mode is used to determine the 

use of internal program memory. Through utilizing the boot code, the programmer 

selects the execution media of user boot code and user program. 

The execution media are SPI, SCI, parallel I/O port, H0 SARAM, flash 

ROM, and OTP ROM. The details are found in references [25] and [26]. 

SELECT CPU BOOT MODE 

1 

JP5 

2 

10K 

JP6 

2 

1 

R36 

10K 

JP9 

2 

R37 

10K 

JP10 

2 

3 

1 

3 

3 

3 

XMP/MC 

GPIOF12-MDXA 

GPIOF2-SPICLKA 

GPIOF3-SPISTEA 

GPIOF14-XF_XPLLDIS 

GPIOF4-SCITXDA 

+3.3V 

+3.3V 

+3.3V 

+3.3V 

+3.3V 

+3.3V 

XMP/MC 

1 

R33 

MDXA 

1 

R34 

10K 

JP7 

2 

SPICLKA 

1 

R35 

10K 

JP8 

2 

3 

SPISTEA 

3 

XF_XPLLDIS 

SCITXDA 

R40 

2.2K 

R41 

2.2K 

R42 

2.2K 

R43 

2.2K 

R44 

2.2K 

GND 

1. Set the jumpers and switch as right table 

2. When downloading via SCI-A, 

Make SCITXDA low using the switch 

3. When performing the downloaded code, 

Make SCITXDA high using the switch 

(a) Booting mode selecting circuit 

Figure 16.16 Boot mode selection. 



MODE SCITXDA MDXA SPISTEA SPICLKA 

Flash 1 X X X 

SPI 0 1 X X 

SCI 0 0 1 1 

HO 0 0 1 0 

OTP 0 0 0 1 

Parallel 0 0 0 0 

Disable 

Enable 

PLL Enable/Disable 

XF — XPLLDIS=0 

XF — XPLLDIS=1 

μ-Processor / μ-Controller 

μ-Processor 

XMP/MC=1 

μ-Controller 

XMP/MC=0 

(b) Booting mode selecting table 


16.2.6 RS-232 Serial Communication Circuit 

The asynchronous serial communication based on the RS-232 protocol 

is one of the helpful ways to transfer data between digital devices, 

although the communication speed is relatively slower than other up-todate 

communication protocols. However, asynchronous communication 

using RS-232 is still widely used in many applications because of the easy 

implementation. In this chapter, the RS-232 serial communication is used 

for monitoring the internal operations of user program, which is a very 

useful technique to debug the user program, even when taking advantage 

of the processor emulators. Figure 16.17 presents the schematic of RS-232 

communication for TSM320x281x DSP chips. 

16.2.7 Serial Interface with D/A Converter, 

EEPROM, and JTAG Port 

A digital-to-analog converter (DAC) is used to convert the digital operation 

results into analog signals, which is a final process of digital signal processing. 

In addition, DAC is useful in monitoring the internal calculation 

results in almost real time. The software developer is able to trace the calculation 

results from control routines by watching the oscilloscope. In order 

to store user parameters in the control system, EEPROMs are frequently 

used. When internal EEPROM is not available, the designer adds external 

EEPROMs to DSP chips or µ-controllers. Introducing DAC and EEPROM 



J6 

1 

2 

3 

EH-3P 

J7 

BEAD 

1 

BEAD 

2 

3 

4 

EH-4P 

C33 

0.1uF 

16V 

C35 

0.1uF 

16V 

BEAD 

BEAD 

GND 

+ 

+ 

C36 

0.1uF 

16V 

+ 

L30 

L31 

L32 

L33 

C54 

+0.1uF 

16V 

1 

2 

3 

4 

5 

6 

7 

8 

RXB 

TXB 

FOR RS232 

INTERFACE 

RXA 

TXA 

+3.3V C34 

0.1uF 

16V 

U13 

+ 

C1+ VCC 16 

V+ GND 15 

C1– T1OUT 14 

C2+ R1IN 13 

C2– R1OUT 12 

V– T1IN 11 

T2OUT T2IN 10 

R2IN R2OUT 9 

MAX3232E 

GND 

C58 

104 

50V 

GPIOG5-SCIRXDB 

GPIOG4-SCITXDB 

GPIOF4-SCITXDA 

GPIOF5-SCIRXDA 

GND 

Figure 16.17 RS-232 communication circuit. 

with serial interfaces reduces the number of wires in connecting DSP chips 

with external devices. Many DSP chip or µ-controller programmers use the 

JTAG port to download and emulate the user program on the basis of the 

boundary scan technology. For a software developer’s convenience, many 

DSP chip and µ-controller manufacturers provide a JTAG port on their 

products as well as a JTAG downloader and emulator. Figure 16.18 shows 

the schematic for serial interface of DAC, EEPROM, and JTAG. 

Figure 16.19 shows the self-designed digital controller PCB using the 

schematics from Figures 16.13 to 16.18. 

16.3 Software Implementation for Control System 

16.3.1 Defining Program Module Diagram 

According to Functionalities (or Tasks) 

The basic structure for implementing the functional requirements into 

user programs is as shown in Figure 16.2. The designer divides the whole 



C_REF 

C2 

10uF 

10V 

+ 

+5V R1 100 

C1 

104 

50V 

8 

7 

6 

5 

VOUTA 

AVSS 

VREFA 

LDAC 

U3 

VDD 

CS 

SCK 

SDI 

1 

2 

3 

4 

GPIOB1-PWM8 

GPIOB2-PWM9 

GPIOB3-PWM10 

MCP4921 

GPIOB0-PWM7 

(a) 

C55 

104 

50V 

1 

2 

3 

4 

U4 

A0 

A1 

A2 

GND 

VCC 

WP 

SCL 

SDA 

+3.3V 

8 

7 

6 

5 

R46 

100 

R64 

2k 

GPIOB4-PWM11 

GPIOB5-PWM12 

GND 

24FC512 

(b) 

GND 

Figure 16.18 Serial interface with DAC, EEPROM, and JTAG port. (a) Serial DAC, 

(b) serial EEPROM, (c) TAG Port.. 

software into several modules according to the functional requirements 

(or tasks). Figure 16.20 provides the software module diagram for the 

control of a non-inverting buck-boost converter. As mentioned earlier, 

the designer needs to be familiar with C/C++ programming language 

and the materials associated with software development environment in 

Table 16.4. It will also be useful to download and use the fundamental 

source codes such as the start-up code file, link command file, and header 

files for the DSP’s internal peripherals. 

16.3.2 Link Command File 

In Figure 16.11, the linker on software development flow links all the 

object code modules into one executable file based on the information 

given by the user. The linking information is described in the link command 

file, which defines the sizes and positions of program/data memory. 

For details, see Reference 22. Figure 16.21 presents a part of the link 

command file on the unified development tools. 



/XTRST 

XTMS 

/TRST 

TMS 

XTDI 

XTDO 

TDI 

TDO 

XTCK 

TCK 

XEMU0 

XEMU1 

EMU0 

EMU1 

+5V 

C60 

104 

+3.3V 

1 

JTAG 

GND 

XTMS 

XTDI 

XTDO 

XTCK 

XEMU0 

50V 

RA3 

7X103 

2 

3 

4 

5 

6 

7 

HEADER-14P 

1 2 

3 4 

5 6 

7 8 

9 10 

11 12 

13 14 

/XTRST 

R45 

10K 

XEMU1 

(c) 

P1 

GND 


16.3.3 Start-up Code 

The start-up code is an assembly language program that prepares for an 

execution of C/C++ language code. The linker links the start-up code into 

the executable code file and then the start-up code is executed first when 

the user program runs on the DSP chip. 

The start-up code performs several initializations for internal peripherals, 

data memory, and interrupt vectors/handlers, and then “jumps or 

calls” the initial function such as “main( )” on the run-time library or user 

program. The initial function is a program start point at the user-level C/ 

C++ program. In many cases, the start-up code is provided by the software 

tool suppliers. Programmers might or might not make minor changes on 

the start-up code for the applications. Once the start-up code is fixed, programmers 

only have to develop user application code at the C/C++ level. 

Figure 16.22 presents an example of the start-up code. 



(a) 

Figure 16.19 (a) Self-designed digital controller PCB, (b) completed controller 

combined with starter kit. 

16.3.4 Header Files and Module to Define 

Special Function Registers 

As seen in Figure 16.10, the internal architecture of a DSP chip or 

µ-controller has special function registers corresponding to the peripheral 

devices such as ADCs, timers/counters, digital I/O ports, communication 

ports, interrupt service request masks, etc. Special function registers 

(SFRs) specify or determine the detail operations of internal peripheral 

devices. Therefore, whenever setting up internal peripherals is necessary, 

programmers look up the hardware manual [21], [26] in order to have the 

specifications of SFRs to use. For a programmer’s convenience, the software 

development tool providers supply several header files and C/C++ 

code files, which define the SFRs. The programmers only include, compile, 



(b) 


and link these files with other modules. Whenever access to some SFRs is 

required, simply assigning values to the SFRs is enough to set up the corresponding 

peripheral devices. Figure 16.23 presents the files listed on the 

software development project where DSP281x_xxxxxxxxx.h and SFR.C 

files contain the definitions of SFRs. 

16.3.5 Construction of Control Flow Chart for Controller 

The preparatory files such as the link command file, start-up code file, 

and SFR-related files have been overviewed. In parallel with understanding 

of the preparatory files, the programmer needs to build the control 

flow chart based on the actual modules and function names. As shown 

in Figure 16.3, the digital signal processing with DSPs or µ-controllers is 



Interrupt Service 

Request (ISR)! 

Power On! 

SFR Access! 

Serial Monitor 

Functions! 

Interrupt Handlers 

INT.C 

All the system interrupt 

handlers are defined. 

Start-Up Code 

STARTUP.ASM 

SFR Definitions 

of TMS320F2812 

DSP281x_xxxxx.h 

SFR.C 

Implementing _printf(), 

_getch(), and _putch() 

functions through SCI-B 

PUFUNC.C 

External 

Devices 

Main Module 

MAIN.C 

1. Call system intializing functions. 

2. Converter control. 

3. Execute testing functions. 

Internal Data/Program Memory 

(Data access, function call) 

Communication 

Lines 

Asynchronous/Synchronous Serial 

Communication 

COM.C 

SCI-A: Com. port for upper devices with CRC. 

SCI-B: Com. port for serial monitor. 

Basic Input/Output System 

BIOS.C 

1. Initializing internal peripherals. 

2. Time delay functions. 

3. Digital/analog input sampling. 

4. Serial DAC and EEPROM handling. 

Link Command File 

LinkCmdFile.cmd 

Contain all the information 

of memory allocation and 

object modules’ linking. 

Figure 16.20 Modular diagram of source codes. 

based on the periodic execution of control routine by timer interrupt service 

request. Time interval (or sampling time) is established by assigning 

a proper counting value to the timer/counter-related SFRs and by 

enabling the operation of timer/counter and interrupt request handling. 

The materials [26]–[28] are helpful in setting the internal timers/counters 

of TMS320F2812. Figure 16.24 provides an example of the flow chart to 

construct the control routines of the user program. 

16.3.6 Composing Source Codes for Noninverting 


For the understanding of the flow chart in Figure 16.24, this section presents 

main routines of several files shown in Figures 16.20 and 16.23, which 

are BIOS.C, COM.C, INT.C MAIN.C, and PUFUNC.C. These routines are 

only examples of composing source codes which depend on the preference 

of the programmer. Also, Texas Instruments provides many programming 

examples with regard to the internal peripherals and applications 

that a programmer can consult. 



Figure 16.21 Link command file. 



Figure 16.22 Example of start-up code. 



Figure 16.23 Header files and source modules. 



Power On 

Every 10us interval 

(t=kT, T=T s ) 

STARTUP.ASM 

INT.C 

Intermediate 

routines from 

run-time library 

MAIN.C 

T1PINT_ISR( ) 

1. Renew gating logic state. 

2. Call ConvCtrl( ) 

Return 

main( ) 

1. Call peripheral intializing functions. 

2. Set and enable timers/counters for timer 

interrupt and PWM generation. 

3. Enable gating logic for buck and boost 

switches 

ConverterTest( ) 

Any key received 

from the user through 

serial monitor? 


parameter 

change? 

N 

Converter 

enabled? 

N 

Y 

Y 

Set the new 

parameters 

Enable 

converter 

Disable 

converter 

MAIN.C 

ConvCtrl( ) 

Verr[kT] = Vo_ref[kT] – Vo_fbk[kT], 

dVctrl[kT] = Kp*(Verr[kT]–Verr[(k–1)T]) + Ki*Verr[kT], 

dVctrl[kT] / = VCTRL_TC, 

dVctrl_rem[kT] + = dVctrl[kT] % VCTRL_TC, 

if(dVctrl_rem[kT]> = VCTRL_TC) { 

dVctrl[kT] + = 1, dVctrl_rem[kT] – = CVTRL_TC} 

else if(dVctrl_rem[kT] < = –VCTRL_TC){ 

dVctrl[kT] – = 1, dVctrl_rem[kT] + = CVTRL_TC} 

Vctrl[kT] + = dVctrl[kT] 

if(Vctrk[kT] > = Vmod) { 

pwm[kT] = Vctrl[kT] – Vmod and enable boost mode } 

else { 

pwm[kT] = Vctrl[kT] and enable buck mode } 

Load pwm[kT] to pwm timer. 

Return 

Figure 16.24 Control flow chart to construct control routines. 



 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 



 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 



 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 



 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 



 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 



 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 



 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 



 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 



 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 



 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 



16.3.7 Making and Running Executable Code File 

An example of making a code file executable on TMS320F2812 is shown 

in this section. The software development environment is based on Code 

Composer Studio version 3.10 (CCS v3.10), which is provided by Texas 

Instruments. In order to download the user program, F28xx On-Chip 

Flash Programmer plug-in module for CCS v3.10 is used. The steps for 

downloading and running the user program on the TMS320F2812 DSP 

chip are shown in Figure 16.25a to i. For the detail usages, Reference 29 

is helpful. 

16.3.8 Testing Operation of Non-inverting Buck-Boost Converter 

The electrical specifications to test the built non-inverting buck-boost converter 

and the digital controller with TM320F2812 DSP chip are given in 

Table 16.2. Figure 16.26a shows the expected output voltage waveform with 

regard to the input voltage variation. The waveforms in Figures 16.26b 

through d are the close-ups of the critical region. These waveforms help 

verify the stability and continuity of the DC gain of the large signal model 

in Figure 16.6. 

Figure 16.27 presents screenshots of a serial monitor to help the programmer 

watch the operations of the program on the DSP chip. By using 

the serial monitor through the RS-232 with a personal computer, the programmer 

is able to implement a console. 

16.4 Summary 

In this chapter, a series of preparatory steps and procedures for the implementation 

of a digital controller based on DSPs was overviewed. To better 

explain, the implementation of a non-inverting buck-boost converter was 

presented as an example with experimental results and suggestions to 

monitor the operation of a user program. Several schematics and source 

codes were provided as well. 



(a) Run CCS v3.10 

(b) Select Project –> New 

Figure 16.25 An example of making and running a user program code on 

TMS320F2812 DSP chip. (a) Run CCS v3.10. (b) Select project -> New. (c) Add link 

command file to project tree. (d) Add start-up code to project tree. (e) Add user C/ 

C++ source files to project tree. (f) Add run-time library to project tree. (g) Click 

“Rebuild All” button to generate an executable code file. (h) Click “F28xx On-Chip 

Flash Programmer” to download the generated code file. (i) Run the downloaded 

user program code. 



(c) Add Link Command File to Project Tree 

(d) Add Start-up Code to Project Tree 




(e) Add User C/C++ Source Files to Project Tree 

(f) Add Run-time Library to Project Tree 




(g) Click Rebuild All Button to Generate an Executable Code File 

(h) Click F28xx On-Chip Flash Programmer to Download the Generated Code File 




(i) Run the Downloaded User Program Code 




V in [V] 

V inH = 4.2V 

V o _ ref = 3.3V 

V in = V out + V drop 

Critical region 

without transients 

V inL = 2.5V 

V in > V out + V drop 

V in < V out + V drop 

Buck mode 

Boost mode 

t[s] 

(a) An Expected Output Voltage Depending on the Input Voltage Variation 

(b) Output Voltage During Smooth Transition from Buck to Boost 

Figure 16.26 The expected and actual output voltages in the critical region. (a) 

An expected output voltage depending on the input voltage variation. (b) Output 

voltage during smooth transition from buck to boost. (c) Output voltage during 

smooth transition from boost to buck. (d) A close-up of the gating signal during 

smooth transition. 



(c) Output Voltage During Smooth Transition from Boost to Buck 

(d) A Close-up of the Gating Signal During Smooth Transition 




Figure 16.27 Example of serial monitoring for user program for TMS320F2812 

chip. 

References 

1. Chakraborty, A., A. Khaligh, and A. Emadi. 2006. Combination of buck and 

boost modes to minimize transients in the output of a positive buck-boost 

converter. In 32nd Annual Conference on IEEE Industrial Electronics. November: 

2372–2377. 

2. Chakraborty, A., A. Khaligh, A. Emadi, and A. Pfaelzer. 2006. Digital combination 

of buck and boost converters to control a positive buck-boost converter. 

In 37th IEEE Power Electronics Specialists Conference. June: 1–6. 

3. Jingquan, C., D. Maksimovic, and R. Erickson. 2001. Buck-boost PWM converters 

having two independently controlled switches. In IEEE 32nd Annual 

Power Electronics Specialists Conference. 2 (June): 736–741. 

4. Haibo, Q., Z. Yicheng, Y. Yongtao, and W. Li. 2006. Analysis of buck-boost 

converters for fuel cell electric vehicles. In IEEE International Conference on 

Vehicular Electronics and Safety. December: 109–113. 



5. Midya, P., K. Haddad, and M. Miller. 2004. Buck or boost tracking power 

converter. IEEE Power Electronics Letters. 2(4):131–134. 

6. Andersen, G. K., and F. Blaabjerg. 2005. Current programmed control of a 

single-phase two-switch buck-boost power factor correction circuit. IEEE 

Transactions on Industrial Electronics. 53(1):263–271. 

7. Khaligh, A., A. M. Rahimi, and A. Emadi. 2008. Modified pulse-adjustment 

technique to control DC/DC converters driving variable constant-power 

loads. IEEE Transactions on Industrial Electronics. 55(3):1133–1146. 

8. Jingquan, C., D. Maksimovic, and R. W. Erickson. 2006. Analysis and design 

of a low-stress buck-boost converter in universal-input PFC applications. 

IEEE Transactions on Power Electronics. 21(2):320–329. 

9. Sahu, B., and G. A. Rincon-Mora. 2004. A low voltage, dynamic, noninverting, 

synchronous buck-boost converter for portable applications. IEEE 

Transactions on Power Electronics. 19(2):443–452. 

10. LTC3440: Micropower synchronous buck-boost DC/DC converter. www.linear.com. 

11. Weissbach, R. S., and K. M. Torres. 2001. A noninverting buck-boost converter 

with reduced components using a microcontroller. In Proceedings of the IEEE 

Southeast Conference. April: 79–84. 

12. Xiaoyong, R., T. Zhao, R. Xinbo, W. Jian, and H. Guichao. 2008. Four switch 

buck-boost converter for telecom DC-DC power supply applications. In 

Twenty-Third Annual IEEE Applied Power Electronics Conference and Exposition. 

February: 1527–1530. 

13. Bryan, D. A. W. 1988. Bi-directional buck-boost DC/DC converter. US Patent. 

4,736,151 (April). 

14. Dwelley, M. D., Barecelo, and W. Trevor. 2000. Control circuit and method for 

maintaining high efficiency in a buck-boost switching regulator. US Patent. 

6,166,527 (December). 

15. Paulkovich, R. J., and G. Ernest. 1981. Buck/boost regulator. US Patent 

4,245,286 (January). 

16. Hengchun, T. M., and J. Vijayan. 2000. Switching controller for a buck + boost 

converter and method of operation thereof. US Patent 6,037,755 (March). 

17. Davis, L. 2008. DSP processor vendors. http://www.interfacebus.com/ 

Digital_Signal_Processor_Manufacturers.html. 

18. Mohan, N., T. M. Undeland, and W. P. Robbins. 2003. Power Electronics: 

Converters, Applications, and Design. John Wiley & Sons. 

19. Slotine, J. J. E., and W. Li. 2004. Applied Nonlinear Control. Prentice Hall, Inc. 

20. Phillips, C. L., and H. T. Nagle. 1995. Digital Control System Analysis and 

Design, 3rd ed. Prentice Hall. 

21. Texas Instruments. 2008. Technical documents: C2000TM high performance 

32-bit controllers—products user guides. http://focus.ti.com/dsp/docs/ 

dspsupporttechdocs.tsp?sectionId=3&tabId=409&techDoc=6&familyId=140 

6&documentCategoryId=6&Input3=Go. 


32-bit controllers—tools user guide. http://focus.ti.com/dsp/docs/dspsupporttechdocs.tsp?sectionId=3&tabId=409&techDoc=6&familyId=1406&doc 

umentCategoryId=6&toolTypeId=0&viewType=0&toolTypeFlagId=2. 

23. Texas Instruments. 2008. TI eStore. http://www.ti-estore.com/Merchant2/ 

merchant.mvc?Screen=CTGY&Category_Code=dStartKit. 




32-bit controllers—application notes. http://focus.ti.com/dsp/docs/dspsupporttechdocs.tsp?sectionId=3&tabId=409&techDoc=1&familyId=110&d 

ocumentCategoryId=1. 

25. Texas Instruments. 2004. TMS320x281x Boot ROM Reference Guide 

(SPRU095B). 

26. Texas Instruments. 2005. TMS320F2810, TMS320F2811, TMS320F2812, 

TMS320C2810, TMS320C2811, TMS320C2812 Digital Signal Processors Data 

Manual (SPRS174M). 

27. Texas Instruments. 2006. TMS320x281x DSP Event manager (EV) Reference 

Guide (SPRU065D). 

28. Texas Instruments. 2005. TMS320x281x DSP System Control and Interrupts 

Reference Guide (SPRU078C). 

29. Texas Instruments. 2005. Code Composer Studio Development Tools v3.1: Getting 

Started Guide (SPRU509F). 


Digital Control Design and Implementation of a DSP Based 

High-Frequency DC-DC Switching Power Converter 

Shamim Choudhury 

Texas Instruments Inc. 

12203 Southwest Freeway, MS 728 

Stafford, Texas 77477, USA 

Email: sach@ti.com 

Abstract 

This paper presents a DSP based digital control design and implementation of a high frequency dc-dc 

switching power supply. Starting with a dc-dc buck converter and a given set of performance 

specifications, different control blocks and parameters, used as in the analog control design approach, 

are reviewed prior to the control design in digital domain. The control loop is then analyzed and the digital 

controllers are designed using different control design approaches. MATLAB based digital control design 

approaches presented here are finally validated with multiple test results from a prototype converter. 

1. Introduction 

Digital control of switching power supplies is becoming more and more common in industry today 

because of the availability of low cost, high performance DSP controller with enhanced and integrated 

power electronic peripherals such as analog-to-digital (A/D) converters and pulse width modulator (PWM). 

DSP based digital control allows for the implementation of more functional control schemes, standard 

control hardware design for multiple platforms and flexibility of quick design modifications to meet specific 

customer needs. Digital controllers are less susceptible to aging and environmental variations and have 

better noise immunity. Modern 32-bit DSP controllers with processor speed up to 150MHz and enhanced 

peripherals such as, 12-bit A/D converter with conversion speed up to 80nSec, 32x32-bit multiplier, 32-bit 

timers and real-time code debugging capability gives the power supply designers all the benefits of digital 

control and allows implementation of high bandwidth, high frequency power supplies without sacrificing 

performance [1-4]. The extra computing power of such processors also allows implementation of 

sophisticated nonlinear control algorithms, integrate multiple converter control into the same processor 

and optimize the total system cost. However, the power supply engineers, mostly familiar with analog 

control design, are faced with new challenges as they start to adopt these new digital control techniques 

in their designs. 

Since DSPs just started to gain some serious considerations in controlling power supplies, many pertinent 

factors in the design and implementation of a digital control loop need to be addressed. Re-identification 

of the control blocks and the associated control parameters is essential for the analog designers in order 

to enable them to implement the DSP based digital control techniques using the well-known analog 

control design approaches. This paper, therefore, describes a step-by-step DSP based digital control 

design and implementation of a high frequency dc-dc converter. Starting with a dc-dc buck converter and 

a given set of performance specification, it discusses different control design approaches and highlights 

the significant differences in designing control in the digital domain compared to the analog approach. 

Two approaches to the control design are illustrated namely, the design by emulation and the direct 

digital design. These are first shown in MATLAB and then verified by experimental results. In this process 

the effects of sampling delay and the computation delay are also analyzed in MATLAB and then verified 

experimentally. 

2. Digital Control Implementation for DC-DC Converter 

Figure 1 shows a simplified block diagram of a digitally controlled dc-dc converter interfaced to a 

TMS320F2812 DSP controller. This is a 32-bit, 150MHz DSP from Texas Instruments.

Vin 

Iin 

Q1 

L 

Vout 

Kd 

Gp 

Gate 

Drive 

C 

RL 

Signal 

Conditioning 

Vos 

d 

PWM1 

A/D 

TMS320F2812 

U 

Gc(z) 

E 

Vref 

Vo 

+ 

Figure 1. DSP based Digital Control of DC-DC Converter 

As indicated in Figure 1, a single signal measurement is needed to implement the voltage mode control 

of the dc-dc converter. The instantaneous output voltage Vout is sensed and conditioned by the voltage 

sense circuit and then input to the DSP via the ADC channel. The digitized sensed output voltage Vo is 

compared to the reference Vref. The voltage loop controller Gc is designed to make the output voltage 

Vout track the reference Vref and at the same time achieve the desired dynamic performance. The 

digitized output U of this controller provides the duty ratio command for the buck regulator switch Q1. This 

command output is used to calculate the appropriate values for the timer compare registers in the on-chip 

PWM module. The PWM module uses this value to generate the PWM output, PWM1 in this case, that 

finally drives the buck converter switch Q1. 

2.1. Digital Sampling Loop Implementation 

Figure 2 shows one example of a digital sampling scheme using the DSP on-chip peripherals. The 

sampling scheme affects the digital controller design and, therefore, needs appropriate attention. PWM 

output frequency is set up by configuring one of the on-chip Timers, T1 in this case. In this example, T1 

generates a dual edge modulated (symmetric), 250 kHz PWM output. These timers have associated 

compare registers which are used to write the calculated duty ratio values. These values then get 

compared with the timer counter value in order to generate the PWM output. The time at which a newly 

written compare value affects the actual PWM output duty ratio is controlled by associated PWM control 

registers. In this example, the PWM control registers are set up such that a new value written in the 

compare register, changes the actual PWM output duty ratio at the start of the subsequent timer (T1) 

period. Also, the ADC control registers are set up such that the AD conversion is triggered at the middle 

of the ON pulse of the PWM output. As soon as the conversion is complete, the ADC module is set up to 

T1 

Sampling period N N+1 

T S 

PWM period n n+1 

T S 

T d Update 

T d Update 

Duty 

Duty 

Tadc 

Tadc 

Sampling Scheme 1 

T d = 0.5T s 

Code 

Execution 

Context 

Save 

Start 

ADC 

Interrupt 

ISR 

Execute Context 

Controller Restore 

Start 

ADC 

Write 

Compare 

Spare 

Interrupt 

Background loop 

Write 

Compare 

t 

Figure 2 DC-DC Converter Digital Control Loop Sampling Scheme

generate an interrupt. The time delay between the start of AD conversion and this interrupt is shown in 

Figure 2, as Tadc. This time includes the AD conversion time and the processor interrupt latency. Inside 

the interrupt service routine (ISR), the user software reads the converted value from the ADC result 

register, implements the controller and then writes the new PWM duty ratio value to the appropriate PWM 

compare register. However, this new duty ratio value takes affect at the start of the subsequent PWM 

cycle. From Figure 2, it is clear that the time delay Td, between the ADC sampling instant and the PWM 

duty ratio update, is half the PWM period. In this case, the PWM period and the sampling period (Ts) are 

equal and so the computation delay is, Td = Ts/2. Also shown in Figure 2, the calculation of a new duty 

ratio value inside the ISR is completed well before a subsequent interrupt is generated. This means that, 

at this sampling frequency, the processor bandwidth (150 MHz) allows for sufficient spare time for 

extending the ISR by executing multiple controllers or other time critical tasks. Some of this spare time 

can also be used for non-time critical tasks by running them from a background loop. 

2.2. DC-DC Controller Design 

The system parameters used in this design are: 

Vin = 4~6V, Vout = 1.6V, Max output current Iout = 16A 

Maximum output voltage (used for ADC signal scaling) Vomax = 2V 

PWM frequency fpwm = 250kHz; Voltage loop sampling frequency fs = 250kHz 

Output filter components, L = 1.0uH, C = 1620uF, ESR = 4.0 mOhm 

Desired voltage loop bandwidth fcv = 20kHz 

Phase Margin = 45 deg, Settling time < 75uSec 

In order to design the digital controller, two approaches are discussed. These are, 1. Design by Emulation 

and 2. Direct Digital Design. 

2.2.1 Design by Emulation 

This is also known as Digital Redesign Approach. In this method, an analog controller is first designed in 

the continuous domain as if one were building continuous time control system, by ignoring the effects of 

sampling and hold associated with the AD converter and the digital PWM circuits. The analog controller is 

then converted to a discrete-time compensator by some approximate techniques. Figure 3 represents a 

simplified block diagram of the system in Figure 1. It shows all the different components of this closed 

loop control system in s-domain. 

Vo 

d Gp(s) 

Fm 

Kd 

U 

Gc(s) 

E 

Vref 

Vo 

+ 

U(n) 

Gc(z) 

E(n) 

Figure 3 DC-DC Converter Control Loop Block Diagram in s-domain 

The small signal power stage model of the buck converter in s-domain is indicated as Gp(s). For the given 

system parameters, this is derived as, 

G P 

( s) 

= (3.2410 

5 

s + 5.0) /(1.68510 

+ 1.64810 

s + 1.0) 

If the maximum output voltage is Vomax, then the voltage feedback factor is, Kd = 1/Vomax, provided that 

the digital output voltage Vo is represented in Q31 fixed-point format for this 32-bit DSP controller [6]. The 

PWM modulator gain is Fm = 1. This is so because the user software together with the on-chip PWM 

9 

s 

2 

5

hardware can be configured such that as the controller output U (in Q31) varies between 0 ~ 7FFFFFFFh, 

the PWM output duty ratio d varies between 0 ~ 1, [6]. 

Now for this plant Gp(s), a suitable analog controller Gc(s) is designed in MATLAB using the available 

control design tool. This is shown in Figure 4 where the system bandwidth (BW) is 25 kHz and the phase 

margin (PM) is 71 deg. 

Continuous System Bode Plot 

(Matlab) 

BW = 25kHz, PM = 71 deg 

Figure 4 DC-DC Converter Control Loop Bode Plot Gp(s)*Gc1(s)*Kd*Fm (MATLAB) 

The corresponding controller Gc1(s) is derived as, 

This analog controller Gc1(s) can be discretized by any of the commonly used discretization methods. 

Specifying a method such as ‘Pole-Zero Match’ in MATLAB yields the following digital controller Gc1(z): 

G C 1 

G C 

2 

5 

9 

1( 

s) 

= (14.3s 

+ 6.51410 

s + 7.210 

) / s( 

s + 1.25610 

1 

U 12.34 22.53z 

+ 10.28z 

( z) 

= = 

1 

2 

E 1 1.605z 

+ 0.6051z 

2 

U ( n) 

= 1.605U 

( n 1) 

0.6051U 

( n 2) + 12.34E( 

n) 

22.53E( 

n 1) 

+ 10.28E( 

n 2) 

Where, the sampling time is Ts = 1/fs = 4uSec. This controller was implemented using DSP instruction set 

and the dynamic performance of the closed loop converter was tested. This is shown in Figure 5: 

5 

) 

Gp(z)*Gc1(z)*Fm*Kd 

Figure 5 DC-DC Converter Load Transient Response (loop gain = Gp*Gc1*Fm*Kd)

For a step load change of 15A, the output voltage settles within 30uSec (1% band). The converter has a 

satisfactory time response. However, the damping of the transient response does not reflect a phase 

margin of 71 deg as shown in MATLAB Bode plot (Figure 4). This difference in the designed and actual 

phase margin is because of the fact that we completely ignored the effect of sampling and hold and the 

computation delay. In digital control design the effect of these delays can be taken into account prior to 

the control design that results in a more predictable and accurate dynamic performance. This is illustrated 

next. 

2.2.2 Direct Digital Design 

Figure 1 is now redrawn as in Figure 6 to show all the different components of this closed loop control 

system including the effect of sampling and hold. 

The sampling process by the on-chip ADC is represented by an ideal sampler with time period Ts. ADC 

can be represented this way as compared to the model given in [7], since the ADC gain is taken into 

account in the block labeled Kd and ADC conversion time is included in the computation delay block 

labeled Hc. The on-chip PWM module acts as a hold device. Representing this as a zero-order-hold 

(ZOH), the ADC and the PWM module together form a sampling and hold device. The s-domain transfer 

function of such a device can be expressed as [1- exp(-s*Ts)]/s. The computation delay block Hc, models 

the time delay between the ADC sampling instant and the subsequent duty ratio update. If this time delay 

is denoted by Td then the transfer function for Hc is, Hc = exp(-s*Td). Now, the continuous time power 

stage model is first discretized with ZOH and the sampler. 

d 

Gp(s) 

Vout 

ZOH 

Kd 

Hc 

T s 

Vo(n) 

Gp(z) 

U(n) 

Gc(z) 

E(n) 

+ 

+ 

Vref 

Figure 6 DC-DC Converter Digital Control Loop Block Diagram 

Once this is available, the discrete-time compensator. i.e., a digital controller Gc(z) is designed directly in 

the z-domain using methods similar to the continuous-time frequency response methods. This has the 

advantage that the poles and zeros of the digital controllers are located directly, resulting in a better load 

transient response, as well as better phase margin and bandwidth for the closed loop operation of the 

power converter. The discrete-time transfer function Gp(z) of the converter plant, including the ZOH, 

the sampler, the voltage sensing gain and the computation delay model Hc is [8], 

1 sTs 

GP 

( z) 

= Z{ 

s 

(1 e ). HC. 

GP 

( s). 

Kd} 

2 

G P 1 

( z) 

= 0.0494( z 0.5283) /( z 1.952z 

+ 0.962) 

where, Z denotes the z-transform of the function inside the parenthesis {}. Using MATLAB, this can be 

computed as, 

Where Kd = 1/Vomax = _, Ts = 1/fs = 4uSec and the computation delay Td, for now, is taken as Td = 0, 

i.e., Hc = 1.

Discrete System Bode Plot 

Gp1(z)*Gc2(z) 

(Td=0) 

BW = 27.9kHz, PM = 61.6 deg, GM = 9dB 

Figure 7 DC-DC Converter Digital Control Loop Bode Plot Gp1*Gc2 (MATLAB) 

For this plant G P1 , a suitable digital controller is designed in MATLAB. The system bandwidth is set at 

27.9 kHz with a phase margin of 61.6 deg. The Bode plot is shown in Figure 7. The corresponding 

controller G C2 is derived from MATLAB as, 

G C 2 

1 

U 14.87 26.91z 

+ 12.16z 

( z) 

= = 

1 

2 

E 1 1.473z 

+ 0.473z 

2 

U ( n) 

= 1.473U 

( n 1) 

0.4731U 

( n 2) + 14.87E( 

n) 

26.91E( 

n 1) 

+ 12.16E( 

n 2) 

Case 1 : Computation Delay Td = 0.5Ts 

For the controller just designed we assumed Td = 0, which is not the case if we implement this controller 

using the sampling scheme shown in Figure 2. So, we recalculate Gp(z) for T= 0.5Ts to include the effect 

of the sampling scheme shown in Figure 2. The modified plant model is, 

G P 

2 

2 

2 

( z) 

= (0.022z 

+ 0.017z 

0.158) / z( 

z 1.952z 

+ 0.962) 

The corresponding Bode plot for this plant Gp2(z) with the controller Gc2(z) is shown in Figure 8. 

Gp2(z)*Gc2(z) 

BW = 26.9kHz, PM = 41 deg, GM = 7.46dB 


From the two plots of Gp1*Gc2 and Gp2*Gc2, it is clear that the same controller Gc2 results in a reduced 

phase margin of 20.6 deg (= 61.6-41.0) for the latter system. This reduction in phase margin can be 

accounted for by the computation time delay of Td = 0.5Ts associated with Gp2. This time delay 

translates to a phase lag of, 

H 

= T 

= ( 360 f )(0.5Ts) 

20 deg 

C d 

where, Ts = 4uS, and f 27kHz is the frequency of interest at which the phase lag is calculated.

The actual system Bode plot for the digitally controlled dc-dc converter represented by the plant model 

Gp2(z) and controlled by the controller Gc2(z) is shown in Figure 9. Notice that the frequency domain 

performance parameters (bandwidth, phase margin and gain margin) agree quite well between the actual 

and the designed values. The time domain dynamic performance of the converter is shown in Figure 10. 

For a step load change of 15A, the output voltage settles within 28uSec (1% band). These test results on 

the frequency and time domain characteristics of the digitally controlled converter show the validity of the 

MATLAB based design approach as illustrated by Figures 7 and 8 above. 

Gp2(z)*Gc2(z) 

BW = 22.45 kHz, PM = 40 deg, GM = 10.7dB 

Figure 9 DC-DC Converter Control Loop Bode Plot Gp2*Gc2 (Test result from prototype h/w) 

Figure 10 DC-DC Converter Load Transient Response (Loop gain = Gp2*Gc2) 

Case 2 : Computation Delay Td = 2.0Ts 

The sampling scheme shown Figure 2 can be modified to investigate the effect of a more severe 

computation delay of Td = 2.0Ts. This is easily done in software by changing the interrupt scheme and 

the way the actual PWM duty ratio is updated following a new AD conversion of the output voltage. Once 

this is done in software, the new plant model Gp3, for Td = 2Ts, is computed using MATLAB as, 

G P 

2 

2 2 

3 

( z) 

= (0.022z 

+ 0.017z 

0.159) / z ( z 1.954z 

+ 0.963) 

The corresponding Bode plot for this plant Gp3(z) with the controller Gc2(z) is shown in Figure 11.

Gp3(z)*Gc2(z) 

BW = 27.9kHz, PM = -19.0 deg, GM = -2.22dB, 

Unstable Loop. 


From the plot of Figure 11 it is clear that this system is completely unstable when controlled by the 

controller Gc2. From the plots of Gp1*Gc2 and Gp3*Gc2 we note that the controller Gc2 results in a 

reduced phase margin of 80.6 deg [= 61.6-(-19.0)] for the latter system. This reduction in phase margin is 

again accounted for by the computation time delay of Td = 2.0Ts associated with Gp3. This time delay 

translates to a phase lag of, 

where, Ts = 4uS, and f 27kHz is the frequency of interest at which the phase lag is calculated. 

In order to find a stable controller for Gp3, we note that this plant has 4-poles and 2 zeros and, therefore, 

the 2-pole 2-zero controller Gc2 cannot stabilize the system. So, using MATLAB a new 3-pole 3-zero 

controller Gc3 is designed as, 

G C 3 

H 

C 

= T 

d 

= ( 360 f )(2.0Ts) 

80 deg 

1 

2 

3 

( 14.4 31.1 20.1 3.376 

) = U z + z z 

z = 

1 

2 

E 1 1.235z 

+ 0.2362z 

0.00115z 

3 

U ( n) 

= 1.235U 

( n 1) 

0.2362U 

( n 2) + 0.00115U 

( n 3) 

+ 14.4E( 

n) 

31.1E( 

n 1) 

+ 20.1E( 

n 2) 3.376E( 

n 3) 

The corresponding Bode plot for this plant Gp3(z) with the new controller Gc3(z) is shown in Figure 12. 

3 Pole 3 Zero Type Controller 

Gp3(z)*Gc3(z) 

BW = 16.1kHz, PM = 46.4 deg, GM = 3.77dB 

Figure 12 DC-DC Converter Digital Control Loop Bode Plot Gp3*Gc3 (MATLAB)

The actual system Bode plot for the dc-dc converter represented by this plant model Gp3(z) and 

controlled by the redesigned controller Gc3(z) is shown in Figure 13. It is again clear that the frequency 

domain characteristics match very closely between the actual and the designed values. Figure 14 shows 

the converter output voltage transient response with this controller. For a step load change of 15A, the 

output voltage settles within 50uSec (1% band). These test results on the frequency and time domain 

characteristics of the converter again show the validity of the MATLAB based design approach as 

depicted in Figures 11 and 12 above. 

Gp3(z)*Gc3(z) 

BW = 15.28kHz, PM = 41.76 deg, GM = 3.4dB 

Figure 13. DC-DC Converter Control Loop Bode Plot Gp3*Gc3 (Test result from prototype h/w) 

Figure 14. DC-DC Converter Load Transient Response (Loop gain = Gp3*Gc3) 

Conclusion 

DSP based digital control design methods for high frequency dc-dc buck converter is investigated using 

MATLAB based control design tools. Starting with a buck converter interfaced to a DSP controller, 

different control blocks and associated parameters are identified prior to the digital controller design. Two 

approaches to the digital controller design are presented. The first method, namely design by emulation, 

allows the power supply designers to do the control design in the familiar s-domain and then convert it to 

a discrete/digital controller. The second approach known as direct digital design, illustrates digital 

controller design directly in z-domain. It was found that the later approach results in a better dynamic 

performance for the closed loop operation of the converter. All of these MATLAB based designed 

controllers were finally validated by experimental results.

References 

[1] S. Bibian, H. Jin, “Digital control with improved performance for boost power factor correction circuits” 

APEC, March 2001 pp:137 - 143 

[2]Jinghai Zhou, etc., “Novel sampling algorithm for DSP controlled 2 kW PFC converter”, Power 

Electronics, IEEE Transactions, March 2001, pp: 217 – 222 

[3] P. Zumel, etc., “Concurrent and simple digital controller of an AC/DC converter with power factor 

correction”, APEC 2002, pp: 469 – 475 

[4] Wanfeng Zhang, etc., “DSP implementation of predictive control strategy for power factor correction”, 

APEC, Feb. 2004, pp: 67 - 73 

[5] Y. Duan, H. Jin, “Digital controller design for switch mode power converters”, APEC ’99, Volume: 

2, pp: 967 – 973. 

[6] S. Choudhury, “Average Current Mode Controlled Power Factor Correction Converter using 

TMS320LF2407A”, Texas Instruments Application Report SPRA902, 2003 

[7] Prodic, A.; Maksimovic, D.; Erickson, R.W., “Design and implementation of a digital PWM controller for 

a high-frequency switching DC-DC power converter”, Industrial Electronics Society, 2001. IECON 2001, 

Volume: 2, 29 Nov.-2 Dec. 2001, pp: 893 - 898 

[8] S. Choudhury, “DSP Implementation of an average current mode controlled Power Factor Correction 

Converter”, International Power Elect Technology Conference Proceeding, Nov 4-6, 2003.

00PSC-75 

Design and Implementation of a Digital Controller For DC-to- 

DC Power Converters 

Copyright © 2000 Society of Automotive Engineers, Inc. 

John Sustersic, John R. (Jack) Zeller, Zhiqiang Gao, 

The Advanced Engineering Research Laboratory, Cleveland State University 

Robert Button 

NASA Glenn Research Center 

ABSTRACT 

A digital signal processor (DSP) solution is proposed to 

control an H-bridge DC-DC isolated output power 

converter. The multiple mode digital controller is 

evaluated with an existing Westinghouse 1-kW power 

stage. The digital controller was developed using the 

dSPACE [1] rapid prototype development system and 

MATLAB/Simulink. It is evaluated using a real-time 

digital control development platform that included the 

actual Westinghouse converter power stage. Preliminary 

digital controller performance is presented that warrants 

continued investigation and development of this 

application of digital control and supports the use of the 

DSP as a viable component in Power Management and 

Distribution (PMAD) applications. 

INTRODUCTION 

The burgeoning interest in digitally controlled DC-DC 

power conversion is represented by the growing volume 

of literature on the subject [2-12]. The interest is strong in 

the aerospace industry, especially at NASA, for several 

reasons. First, efficient DC-DC power conversion is 

critically important in all space platforms, especially 

manned spacecraft. Second, all space borne systems 

require extensive telemetry data from all elements of the 

system. These requirements increase the cost and the 

complexity of all elements of the space system and 

further increase the expenditures of time and money 

required for sophisticated systems integration. Third, the 

high costs associated with the deployment of space 

systems constantly point research toward new 

technologies that promise to reduce the size and weight 

of system components while increasing overall system 

reliability and lowering integration costs. As outlined in 

the following work, digitally controlled DC-DC power 

conversion promises advantages in all of these areas. 

OBJECTIVE 

The principle goal of this effort is to demonstrate the 

following device-level improvements in an open-ended, 

digital configuration that will easily allow for the 

development and implementation of a number of systemlevel 

objectives. 

DEVICE LEVEL IMPROVEMENTS - 

1. Real-time optimization and adaptive compensation of 

the converter for varying load and/or line conditions. 

2. Digital control to provide active compensation for 

mismatched FETs and/or aging components in the 

converter bridge. 

3. Software implementation of under voltage protection, 

thereby eliminating inefficient hardware protection 

methods. 

4. Greatly improved portability to other converters. 

5. Possibility of implementing optimized active filter 

technology. 

SYSTEM LEVEL IMPROVEMENTS - A digital control 

system architecture will include features to improve faulttolerance 

and improve overall system performance. 

Such an architecture might involve a single DSP device 

controlling several DC-DC converters, with several such 

systems operating concurrently. Each DSP would be 

responsible for its assigned converters in addition to the 

monitoring of other devices. This architecture would 

allow for the following system capabilities or 

improvements: 

1. Optimization of parallel converters under widely 

varying load conditions. 

2. Controller redundancy to maintain converter 

operation in case of a DSP failure. 

3. Independent verification of each converter’s 

operation by secondary controllers. 

4. Improved scalability. 

5. Active load balancing. 

6. Improved telemetric capabilities.

7. In situ frequency-domain analysis (FFT) of converter 

operations. 

8. Early identification of potential device failures. 

9. Improvement in overall system reliability and stability. 

10. Active impedance control. 

DIGITAL CONTROLLER DEVELOPMENT 

The approach selected to develop this digital control 

architecture includes several key steps. First, a simple 

mathematical model of the system was developed as the 

initial basis of the controller design. Second, the digital 

control development platform was interfaced to the 

power converter. Third, the preliminary controller 

resulting from the simulation analysis was further 

developed using the digital control development platform 

and dSPACE’s extensions to Simulink, the Real-Time 

Workshop (RTW). Finally, the control algorithm 

developed in this environment was programmed in native 

C code to avoid limitations of the Simulink/RTW 

environment and thereby improve overall controller 

performance. 

MODELING AND SIMULATION 

The modeling of DC-DC converters has resulted in 

several linearized [15-18] and quasi-linearized [19] 

solutions. These solutions generally consider only buckboost 

class converters that require only a single Pulse 

Width Modulation (PWM) input. However, the converter 

system to be studied in this research is significantly more 

complicated. Its model will include a series of linear and 

non-linear blocks. The non-linear blocks can be quite 

complicated, especially the H-bridge block and the stepdown 

isolation transformer block. However, since an 

objective of this investigation is a real-time digital control 

development platform that uses the actual converter, it is 

not necessary to precisely model the plant. Instead, a 

simple model was used to roughly test the proposed 

control system. 

CONTROLLER DESIGN 

Figure 1 – Controller Block Diagram 

A two-loop PI controller (Figure 1) was developed for the 

initial testing of the digital controller. Control of the 

converter is maintained through two phase-locked PWM 

signals. 

Figure 2 – Bi-Phase PWM Signal Definition, 2*t c = T, 

PWM Phase 1 duty cycle = t a /t c , PWM Phase 2 duty 

cycle = t b /t c . All units in seconds. 

The converter requires alternating assertions of these 

PWM signals to drive an AC current through the 

transformer primary. Each PWM signal switches a highside 

FET and the opposing low-side FET in the H-bridge. 

Asserting a particular PWM signal activates that set of 

FETs, allowing current to flow in one direction through 

the transformer. Asserting the opposite PWM signal 

allows current to flow in the opposite direction. The duty 

cycle of each PWM signal is directly proportional to the 

time current is flowing through the transformer during 

each half-cycle. Ideally, both PWM signals would be 

balanced. However, the transconductance of the FETs 

may vary by a factor of two nominally, and this imbalance 

may result in a DC current component through the 

transformer primary. Since this current may saturate the 

transformer core and limit it’s ability to transmit power, 

the duty cycles of the driving PWM signals must be 

adjusted to compensate. Figure 2 illustrates an 

exaggerated case of current imbalance to completely 

define these two control signals. The top waveform of 

figure 2 is a uniform square wave of period T and 50% 

duty cycle. The middle waveform is one PWM channel 

and the lower waveform is the second channel. Time t c 

exactly equals 0.5T. The duty cycle of channel one is 

define as t a /t c . The duty cycle of channel two is defined 

as t b /t c . Both of these quantities are strictly limited to the 

range 0≤t 

≤ 1. However, the FETs exhibit a finite turnoff 

time, and it is possible that duty cycles near 1 may 

result in a shoot-through condition where FETs on one 

side of the H-bridge may momentarily be conducting 

simultaneously. These effects may damage or destroy 

converter components and must be avoided. Therefore, 

conventional designs implement a dead-band between 

the PWM phases. The dead-band used in this 

application is 5%. Therefore, the actual range of PWM 

duty cycles in this application is 0≤t 

≤ 0.95. 

Implementing the current mode control begins with 

calculating the current mode error. This is done by 

sensing the current through the transformer and 

integrating it to determine the average (DC) transformer 

primary current. A PI current loop controller is then used. 

The controller output is limited to restrict its control 

authority, and then differentially combined with the 

voltage loop controller output to determine the two PWM 

duty cycles. 

The outer voltage loop is again a PI controller with feed 

forward of the converter input voltage. In this application,

the error signal drives a PI controller with a proportional 

gain near zero and an integral gain between 50 and 500. 

The output of the traditional PI control is then normalized 

by dividing it by the converter input voltage. This result is 

hard-limited to the range of +/- 1, then linearly scaled into 

the range between zero and one. This is the PWM duty 

cycle output of the voltage loop controller, and is then 

combined with the output of the current mode controller 

to form the two bi-phase PWM signals. 

Additionally, all integration operations in the control 

implementation provide mechanisms that limit the 

integration and prevent integrator run-up. All limits in the 

controller are implemented by checking the limited 

variable against a programmed maximum (or minimum) 

value and assigning the maximum (or minimum, 

respectively) value if the variable exceeds the limit. 

Finally, the controller implementation uses limited 

Boolean logic to shut down the converter under adverse 

input line conditions. 

DIGITAL DC-DC CONVERTER ARCHITECTURE AND 

dSPACE SYSTEM TESTBED (FIGURES 3 &4) 

The H-bridge DC-DC galvanically isolated power 

converter uses four FET switches to modulate filtered 

input power through a transformer. 

Gate Drivers 

CPLD PWM 

Generation 

Figure 3 - Basic H-Bridge and Conceptual Diagram 

To adapt this system to digital control, it is necessary to 

digitize both the output voltage and to sense and digitize 

the transformer current. These voltages are galvanically 

isolated from the digitization circuitry to avoid ground 

loops. Additionally, the transformer primary current must 

be sensed to allow current-mode control. As outlined in 

the previous section, it is actually the DC value of the 

primary current that is used in the control algorithm. In 

addition to the three aforementioned feed back variables, 

the input and output currents are also sensed. These 

currents will be used for further control development and 

for real-time input and output power measurements. 

HP 6050A 

DC Electronic 

Load 

1 kW 40 Amp 

DSP 

DC-DC 

Power 

Converter 

Current 

sensor 

and 

integrator 

ADC 

120 VDC 

Isolation 

amplifier 

ADC 

DCS150-20 

Figure 4 – Real-Time Digital Control Development 

Platform Block Diagram 

This research utilizes a dSPACE DSP rapid-prototype 

development system based on the TMS320C40 DSP by 

Texas Instruments that provides 60 Mflops performance. 

The dSPACE system includes the DS1003 Modular DSP 

board, the DS2001 High Resolution ADC board, the 

DS2102 high-Resolution DAC board, and the DS4002 

Timing and Digital I/O board. This configuration provides 

the following capabilities: 

• Five ADC channels with 16-bit resolution and a 

sampling time of 6.2 microseconds. 

• Six DAC channels with 16-bit resolution and a 

settling time of 2.0 microseconds. 

• Single and/or three-phase PWM generation and 

measurement. 

• Eight programmable digital I/O lines with 200ns 

resolution. 

• Thirty-two additional digital I/O lines. 

A Sorenson [13] Model DCS150-20 provides the nominal 

120 VDC, 10 amps required by the Westinghouse 

converter. The testbed employs a Hewlett-Packard [14] 

Model 6050A DC Electronic load with the appropriate 

load modules. GPIB interfaced oscilloscopes with 

isolated probes and other GPIB instrumentation round 

out the testbed. 

In interfacing the converter to the digital control 

development platform, a minimum of signal processing 

circuitry was used to scale and condition the measured 

variables for digitization and use in the controller. The 

circuitry was developed using Analog Devices AD210 

Isolation Amplifiers. Two pole Butterworth filters are used 

on the voltage feedback channels to eliminate aliasing. 

The Hall effect devices that measure the current signals 

provide the necessary electrical isolation. For the current 

loop feedback path, an F. W. Bell CLN-100 Hall effect 

current-mode sensor is employed, providing a bandwidth 

of 160 KHz. An analog integrator is used to determine 

the DC offset current in the transformer primary. For the 

input and output current measurements, F. W. Bell 

model BB-100 Hall-Effect current sensors are employed. 

DIGITAL PWM GENERATION 

In preparing the converter and the dSPACE system for 

the hardware-in-the-loop simulation, it was discovered 

that there was no direct way to maintain the phase lock 

between the two PWM channels that are required in the 

H-bridge. Using the dSPACE DSP hardware to

accomplish this would involve writing a low-level driver to 

guarantee that the two PWM signals were never 

simultaneously asserted. 

DSP 

Data 

Four 

8-bit 

Register 

s 

50 MHz Clock 


Logic and 

PWM state 

machine 

CPLD 

Figure 5 – PWM Generation 

Output 

Drivers 

Phase 

1 

Phase 

2 

It was decided that a better solution would involve 

developing an Hardware Definition Language (HDL) 

program with which to program a complex 

programmable logic device (CPLD) that would interface 

to a digital output from dSPACE’s DSP and generate the 

appropriate PWM signals. This novel CPLD architectural 

approach was designed to offer software-selectable 

switching frequencies and a PWM resolution of eight bits 

per PWM channel. Furthermore, the device was 

designed with the flexibility to allow for future 

improvements. Figure 5 shows the functional block 

diagram of the PWM generation circuitry. The PWM 

generation is controlled via four 8-bit registers as 

indicated in figure 5. Two registers hold the PWM duty 

cycle for each of the two phase-locked channels. The 

third register holds the divisor for the modulo-n clock 

generator circuit. The fourth register is reserved for 

future expansion and may be used in part to increase the 

PWM resolution. Using the 50 MHz clock in this 

implementation, the maximum attainable PWM 

frequency of the phase-locked PWM outputs is 100 kHz. 

Additionally, the phase is generated with quartz-crystal 

accuracy. The granularity of this implementation is better 

than 20 nanoseconds. 

The additional expense of utilizing a CPLD in this 

application is easy to justify. Most importantly, the 

architecture of the CPLD-based PWM generator ensures 

that the PWM signals continue in the event of a DSP 

software failure. Under this condition, the PWM duty 

cycles will not change significantly and the converter will 

continue to provide a voltage output near the specified 

value. This allows the DSP time to restart and regain 

regulation of the converter without necessarily disrupting 

power conversion. Furthermore, the CPLD approach 

provides hardware-guaranteed phase lock between the 

two PWM signals; a software-based generation 

algorithm could be corrupted by an operating system 

failure in a multi-processing controller. Finally, the CPLD 

based PWM generator relieves the DSP of potentially 

significant processor bandwidth demands, freeing the 

DSP for advanced control computations, and other 

system-level distributed PMAD functions such as 

communication. 

circuit board prototyping capabilities. The final device 

offers quartz-crystal accuracy in PWM signal generation 

with a resolution of less than 20 nanoseconds. 

PRELIMINARY RESULTS 

The Simulink/RTW–based control algorithm proved 

useful as a proof-of-concept study and was effective in 

controlling the system under low power (

Figure 6a – Steady-state controller response, V set = 28 

volts I load = 10 amps, K i = 100. 

Figure 7a – Load Transient Response, V set = 28 volts I load 

= 2 to 10 amps, K i = 100. 

milliseconds for the increasing load. The slower 

controller requires approximately 125 milliseconds to 

recover from both transient cases. Again, the average 

output voltage of both controllers is the same. 

Figure 6b – Steady-state controller response, V set = 28 

volts I load = 10 amps, K i = 25. 

LOAD TRANSIENT RESPONSE 

Load transient response was determined using the 

HP6050A electronic load and its periodic transient 

generator. As shown in figures 7(a) and 7(b), the digital 

controller exhibits good response to load transients. Both 

controllers have similar output voltage fall-off on 

increasing load transients and similar voltage over-shoot 

on decreasing load transients. However, the faster timeconstant 

of the higher bandwidth controller is clearly 

evident by comparing the recovery time of the two 

controllers. The faster controller requires only 25 

milliseconds to recover from the decreasing load and 50 

Figure 7b – Load Transient Response, V set = 28 volts I load 

= 2 to 10 amps, K i = 25. 

LINE TRANSIENT RESPONSE 

Line transient response was determined using the 

Sorenson DC power supply’s period transient generator. 

This produced line transients from 100 volts to 125 volts. 

The results are shown in figures 8(a) and (b). As in the 

load transient cases studied, the effect of the different 

controller bandwidth is clearly evident. However, the 

magnitudes of the output voltage transients are different 

for the two controllers. The higher bandwidth controller 

shows output transients of one volt in magnitude in 

response to the 25% input transients. The lower 

bandwidth controller exhibits output transients of 

approximately 3 volts in response to the same input 

transients.

Figure 8a – Line Transient Response, V set = 28 volts I load 

= 10 amps, V in = 100 volts to 125 volts, K i = 100. 

Figure 9 – Line Transient Response With and Without 

Feed Forward Control, V set = 28 volts I load = 10 amps, V in 

= 100 volts to 125 volts, K i = 100. 

CONCLUDING REMARKS 

This paper documents the elements of a research 

program to develop a DSP-based digital controller for a 

high power DC-to-DC converter. The controller 

developed features a novel architecture in which a CPLD 

device is used for PWM generation. Separating this 

converter function from the control DSP eases the DSP’s 

computational load and provides a level of system fault 

tolerance. Evaluations of the initial selected control 

strategies show fast transient recovery for load and line 

disturbances and the potential for stable, tight steadystate 

output voltage regulation. 

Figure 8b – Line Transient Response, V set = 28 volts I load 

= 10 amps, V in = 100 volts to 125 volts, Ki = 25. 

Recall that the digital controller developed for this 

application uses feed forward control on the input voltage 

to improve line transient response. To test the 

effectiveness of this control approach, the line transient 

test was repeated for the high bandwidth controller with 

the feed forward control removed. 

Figure 9 illustrates the effectiveness of the feed forward 

control. The bottom trace indicates the identical result 

displayed in figure 8(a). The top trace is the performance 

of the controller without the feed forward control 

component using identical test parameters. Both traces 

are displayed using identical time and voltage scales. 

These data clearly indicate that the feed forward control 

implementation used in this controller improves the 

magnitude of the input line voltage induced output 

voltage transient by approximately 50% and reduces the 

duration of the disturbance by 25% to 50%. 

The results obtained thus far have identified several key 

issues that require further investigation. First, the current 

mode controller’s structure and command authority must 

be thoroughly studied and refined. Second, the current 

controller’s sensitivity to integral gain seems to indicate 

that either better noise filtering is needed in the data 

acquisition or a lead-lag compensator may be required to 

increase the system’s phase margin. Third, there are 

indications that the 8-bit resolution per PWM channel 

may be near the minimum required in this application. 

Fourth, the effect of varying the switching frequency on 

converter input and output impedance should be 

analyzed to determine if the switching frequency might 

serve as a viable and useful control handle for the 

regulating system. Finally, nonlinear control techniques 

should be evaluated to determine the best controller for 

this application. 

The digital controller and test bed developed in this 

research is ideally suited to resolve these issues and to 

help define the hardware and software requirements for 

the next generation of digital power conversion 

controllers. This next generation of digital control, 

employing powerful DSPs and fast network 

communication, may indeed form the basis of modular, 

distributed power management and distribution systems.

ACKNOWLEGMENTS 

The work discussed in this paper is sponsored by the 

NASA Glenn Research Center under grant #NCC3-699 

and by Cleveland State University. The work is 

conducted in CSU’s Fenn College of Engineering 

Advanced Engineering Research Laboratory (AERL). 

The authors would like to thank other members of the 

AERL team including Charles Alexander, Marcelo 

Gonzales, and Tom Stimac for their help in the 

experimentation. 

REFERENCES 

1. dSPACE Inc. 22260 Haggerty Road - Suite 120 

Northville, MI 48167 Tel.: (248) 344-0096 Fax: (248) 

344-2060. 

2. P.F. Kocybik and K.N. Bateson, “Digital Control of a 

ZVS Full-Bridge DC-DC Converter”, 0-7803-2482- 

X/95 IEEE 

3. R.R. Boudreaux, R.M. Nelms, and John Y. Hung, 

“Simulation and Modeling of a DC-DC Converter 

Controller by an 8-bit Microcontroller”, 0-7803-3704- 

2/97 IEEE 

4. W.C. So, C.K. Tse and Y.S. Lee, “A Fuzzy Controller 

for DC-DC Converters”, 0-7803-1859-5/94 IEEE 

5. Keyue Ma Smedley and Slobodan Cuk, “One-Cycle 

Control of Switching Converters”, 0-7803-0090-4/91 

IEEE 

6. Richard Redl, “Small-Signal High-Frequency 

Analysis of the Free-Running Current-Mode- 

Controlled Converter”, 0-7803-0090-4/91 IEEE 

7. Richard W. Wall and Herbert L. Hess, “Design and 

Microcontroller Implementation of a Three Phase 

SCR Power Converter.” 

8. T. Gupta, R.R. Boudreaux, R.M. Nelms, and John Y. 

Hung, “Implementation of a Fuzzy Controller for DC- 

DC Converters Using and Inexpensive 8-bit 

Microcontroller”, IEEE Transactions on Industrial 

Electronics, Jan 1997. 

9. R. Vinsant, J. DiFiore, and R. Clarke, “Digital Control 

Converts Power Supply into Intelligent Power System 

Peripheral,” Ninth International High Frequency 

Power Conversion Conference, April 1994, pp. 2-6. 

10. C.P. Henze and N. Mohan, “A Digitally Controlled 

AC-DC Power Conditioner That Draws Sinusoidal 

Current,” IEEE Power Electronics Specialists 

Conference, June 1986, pp. 531-540. 

11. R.R. Boudreaux, R.M. Nelms, and John Y. Hung, 

“Digital Control of DC-DC Converters: Microcontroller 

Implementation Issues,” Combined Proceedings of 

HFP Power Conversion & Advanced Power 

Electronics Technology, Powersystems World’96. 

September 1996, pp. 168-180. 

12. C.L. Phillips and H.T. Nagle, Digital Control Analysis 

and Design, Prentice-Hall, New Jersey, 1995. 

13. Sorensen, A division of Elgar 9250 Brown Deer 

Road San Diego, CA 92121 

14. Hewlett-Packard, Palo Alto, CA. 

15. R.D. Middlebrook and S. Cuk, “A General Unified 

Approach to Modeling Switching Power Stages,” 

IEEE Power Electronics Specialists Conference 

Rec., 1976, pp. 18-34. 

16. ---,”A General Unified Approach to Modeling 

Switching Power Stages in Discontinuous 

Conduction Mode,” IEEE Power Electronics 

Specialists Conference Rec., 1977, pp. 36-57. 

17. A.J. Fossard, M. Clique, J.G. Ferrante, and A. Capel, 

“A General Linear Continuous Model for Design of 

Power Conditioning Units at Fixed and Free-Running 

Frequencies,” IEEE Power Electronics Specialists 

Conference Rec., 1977, pp. 113-124. 

18. F.C. Lee, Y. Yu, and J.E. Triner, “Modeling of 

Switching Regulator Power Stages with and without 

Zero-Inductor-Current Time,” IEEE Power 

Electronics Specialists Conference Rec., 1976, pp. 

62-72. 

19. Chi K. Tse and Keith M. Adams, “Quasi-Linear 

Modeling and Control of DC-DC Converters,” IEEE 

Transactions on Power Electronics, vol. 7, No. 2, 

April 1992. 

20. International Rectifier, 233 Kansas St., El Segundo, 

CA 90245 USA Tel: 310-726-8000 FAX: 310-322- 

3332. 

DEFINITIONS, ACRONYMS, ABBREVIATIONS 

ADC: Analog to Digital Converter 

CPLD: Complex Programmable Logic Device 

DAC: Digital to Analog Converter 

DSP: Digital Signal Processor 

FLOP: Floating Point Operation per Second 

GPIB: General Purpose Instrumentation Bus 

PMAD: Power Management and Distribution 

PWM: Pulse Width Modulation 

RTW: Real Time Workshop – dSPACE’s extension to 

the Simulink Environment

A Practical Introduction to 

Digital Power Supply Control 

Laszlo Balogh 

ABSTRACT 

The quest for increased integration, more features, and added flexibility – all under constant cost 

pressure – continually motivates the exploration of new avenues in power management. An area gaining 

significant industry attention today is the application of digital technology to power supply control. This 

topic attempts to clarify some of the mysteries of digital control for the practicing analog power supply 

designer. The benefits, limitations, and performance of the digital control concept will be reviewed. 

Special attention will be focused on the similarities and differences between analog and digital 

implementations of basic control functions. Finally, several examples will highlight the contributions of 

digital control to switched-mode power supplies. 

I. INTRODUCTION 

Power management is one of the most 

interdisciplinary areas of modern electronics, 

merging hard core analog circuit design with 

expertise from mechanical and RF engineering, 

safety and EMI, knowledge of materials, 

semiconductors and magnetic components. 

Understandably, power supply design is regarded 

as a pure analog field. But from the very early 

days, by the introduction of relays and later the 

first rectifiers, power management is slowly 

incorporating more and more ideas from the 

digital world. Ones and zeros are translated to 

“on and off’s” but at the end a diode can be 

viewed as a “digital component”. The 

introduction of switched mode power conversion 

required even more digital knowledge seeping 

into the repertoire of the practicing power supply 

designers. The know-how of the first discrete 

implementations of the PWM logic using 

comparators, gates and latches have faded away 

long time ago. Integrated pulse width modulator 

ICs have turned those simple digital circuits to 

history and have introduced even more digital 

content to power management. 

Today’s highly integrated power management 

ICs are packed with digital gates. The digital 

circuits allow the integration of some highly 

sophisticated features. Some examples are 

EEPROM based trimming after packaging to 

eliminate package stress related initial offsets, 

digital delay techniques to adjust proper timing of 

gate drive signals, microcontrollers and state 

machines for battery charging and management, 

and the list could go on. 

If power conversion already incorporates 

such a large amount of digital circuitry, it is a 

legitimate question to ask: what has changed? 

What is this buzz about “digital power”? 

II. GOING DIGITAL 

Despite the tremendous amount of digital 

circuitry used in power management integrated 

circuits, it remained mainly hidden from the 

users. Most externally accessible functions are 

implemented by fundamentally analog circuit 

blocks today. Thus PWM controllers and other 

power management integrated circuits have 

successfully upheld their analog feel to them, 

making analog measurements and accepting 

analog controls. Their interfaces to the outside 

world are the various comparators and amplifiers 

monitoring the operating conditions and 

providing a choice of protection options for the 

designer of the power supply. This elemental 

principle prevails in existing controllers as 

demonstrated in Fig. 1. 

6-1

IN 

Power 

Stage 

Filter 

OUT 

IN 

Power 

Stage 

Filter 

OUT 

LOGIC 

ADC 

(PWM) 

VOLTAGE 

& 

CURRENT 

REGULATION 

DIGITAL 

PROCESSOR 

ADC 

ADC 

VOLTAGE 

& 

CURRENT 

REGULATION 

CONTROLLER 

ADC 

ADC 

CONTROLLER 

SENSORY INPUTS 

& 

COMMAND FUNCTIONS 

Fig. 1. Top level analog PWM controller 

architecture. 

Another important aspect to notice in Fig. 1 is 

the fact that the analog inputs are converted to 

digital signals as soon as practical. The point 

where the conversion is taking place in today’s 

controllers varies depending on the signal type. 

When an under voltage lock out function is 

considered, the conversion is done by the 

simplest of all analog-to-digital converters, an 

UVLO comparator. Its input is strictly analog, 

while the output is already a digital signal, it is 

either high (“1”) or low (“0”), with no 

intermediate value. But this digital output is also 

buried inside the integrated circuit and it is very 

rarely accessible by the designer. Output voltage 

and current regulation employs closed loop 

negative feedback, traditionally done by error 

amplifiers and the conversion to the digital 

“domain” is performed by a PWM comparator, 

again well concealed inside the IC. 

A. What Really is “Digital Power”? 

“Digital power” is an inaccurate description 

of a new direction in the controller design of the 

power supply to replace the analog circuits by 

digital implementations. Accordingly, “digital 

power” really stands for digital control of the 

power supply. Digital power supply control 

attempts to move the barrier between the analog 

and digital sections of the power supply right to 

the pins of the control IC. 

SENSORY INPUTS 

& 

COMMAND FUNCTIONS 

Fig. 2. Top level representation of a “digital” 

power supply. 

This fundamental change in the control 

philosophy is summarized in Fig. 2. When 

comparing Fig. 1 and 2, it is important to 

emphasize that the deployment of digital control 

had no effect on the operating principle and the 

design of the power stage. The specification of 

the power supply still determines the choice of 

topology, the selection of power components and 

the required control functions. That leaves a fair 

amount of design tasks still in the analog realm 

for the power supply expert. 

B. What is Changing? 

The striking difference between “analog” and 

“digital” control is the quality and the amount of 

information available for the controller to make 

decisions regarding the operation of the power 

stage. For example, the output of a comparator 

carries limited information about the monitored 

parameter, i.e. only whether it is above or below 

a threshold. When the border between analog and 

digital is moved from the output of a comparator 

to the input by converting the actual information 

to digital form, the controller suddenly knows the 

concrete value of the parameter. Now, in addition 

to comparing it to a threshold, changes in the 

parameter’s value can be detected, stored and 

later reported back to a supervisory system. If 

necessary, parameter values can be combined 

6-2

with other information in complex algorithms to 

perform even more sophisticated functions. 

Of course, this large amount of information 

can not be processed by traditional logic gates. 

Digital controllers take advantage of large scale 

integration offered by state of the art 

semiconductor technology. Typically, a 

microcontroller (µC) or a digital signal processor 

(DSP) is at the heart of a suitable digital 

controller for power supply applications. 

Another important controller property which 

changes significantly is the flexibility to 

implement various control algorithms. 

Traditional, “analog” controllers may employ 

sophisticated decision trees driven by the digital 

outputs of the various peripheral circuits. But the 

reactions to the changes in the operating 

conditions are pre-programmed and rigidly 

executed by the internal logic. For instance, the 

usual reaction to exceeding a current limit 

threshold is to shut down the converter and start 

over, hard coded into the logic of analog 

controllers. The power supply designer has no 

option and in most cases it requires a significant 

amount of external circuitry to circumvent some 

of the built-in features of the controllers. By the 

introduction of a digital engine such as a µC or 

DSP, the decision, how to react to certain 

conditions becomes user programmable. In the 

current limit example the designer might opt to 

let the power supply operate in current limit for a 

number of switching cycles before resorting to 

shutdown. This would allow riding through short 

overload conditions during transient operation. In 

other cases where this behavior is not necessary 

or outright dangerous, the controller could be 

programmed to shut down immediately. 

Another area to address in digital control is to 

ensure stable operation of the power supply. The 

output voltage is still regulated by a closed 

negative feedback loop, but it will be the result of 

complex calculations performed by the µC or 

DSP. While stability criterias for a power supply 

with analog control is well established and 

understood by the designers, these control laws 

are not directly applicable to the digital 

controllers. The digital implementations require 

new expertise, being familiar with and being able 

to apply the stability requirements in the 

Z-domain. The Z-domain transfer function of a 

sampled data system can be used to predict the 

small signal behavior of the converter. Additional 

new problems surface as well, like bandwidth 

limitations, resolution issues in time and voltage 

measurements and limit cycle oscillation, just to 

mention a few which will be discussed later. 

One more key aspect of digital 

implementations is to recognize that 

microcontrollers and DSPs are powered by very 

low voltages due to their semiconductor 

technologies. As a result they are not capable of 

directly interfacing with the power components, 

unlike their analog counterparts. Thus, they 

require their own low voltage supply and a 

suitable high current gate driver with a 

compatible input threshold and adequate output 

voltage range. These requirements establish a 

clear partitioning between the analog and digital 

sections of the power supply. A closer look of the 

fundamental architecture of a digitally controlled 

converter is shown in Fig. 3. 

ANALOG 

DIGITAL 

COM 

LOW V 

BIAS 

uC or DSP 

BIAS 

V IN 

POWER STAGE 

Fig. 3. Analog – digital boundary in a power 

supply. 

The low voltage bias shown in Fig. 3 must be 

able to power the digital controller independently 

without operation of the power stage to allow 

initialization during start-up and to preserve 

intelligence during standby (disable) and short 

circuit operation when traditional bootstrap bias 

might not be available as a viable power source. 

6-3

Furthermore, the output of the digital 

controller must be converted to a suitable signal 

to drive the power switches in the converter and 

all voltages must be scaled to the input voltage 

range of the analog inputs, usually determined by 

the reference voltage of the analog-to-digital 

converter on-board the digital controller. 

C. Advantages of Digital Control 

Flexibility is definitely the most noteworthy 

benefit of digital controllers. It is especially 

remarkable considering the consolidation of all 

necessary functions into one highly integrated, 

sophisticated controller. As mentioned before, by 

the introduction of a digital controller, the 

hardwired, hardly customizable control flow of 

analog controllers is exchanged for an open 

structure, where the designer has the ultimate 

freedom to decide the right course of action to a 

given stimuli. This new opportunity can be rather 

overwhelming for practicing power supply 

designers, because most of these decisions were 

made for them by the semiconductor 

manufacturers of analog controllers. In addition, 

this freedom comes with another new 

complication, the digital controller must be told 

what to do. Software must be written to program 

the execution of all the functions assigned to the 

µC or DSP. The software carries the knowledge 

and intellectual property which was previously 

realized in the controller hardware. 

There are three major areas in the design 

where flexibility can provide significant benefits. 

The first one is adjustability. Every parameter 

which is measured or programmed can also be 

adjusted by the digital controller. These include 

voltage and current thresholds, operating 

frequency, thermal shut down, startup time, and 

so on. 

The next level of flexibility is offered by the 

user defined what-if decision making process 

inside the digital controller. This tool can be 

exploited for enhanced functionality like green 

mode or low power stand-by operation, load 

share or hot swap control, just to mention a few. 

The foundation of these features is the option to 

invoke different control algorithms as the 

operating conditions of the power supply are 

changing. In addition, fault containment 

strategies can be refined and adapted as required 

by diverse applications. For example, once the 

output current of the converter is measured by the 

digital controller this information can be used to 

program fold back, constant power, constant 

current, delayed shutdown or any other mode of 

over current protection. Moreover, any 

combination of these output characteristics can 

be implemented without ever changing any 

components in the power supply. 

The use of modern digital controllers also 

adds communication as a potential feature to the 

power supply. When this communication 

capability is utilized, the flexibility of the digital 

approach is greatly enhanced through the on-thefly 

programmability. The adjustability of the 

converter’s output voltage is a great advantage as 

demonstrated in processor applications using 

VID code. In a communication enabled power 

supply, not just the output voltage, but current 

limit, operating frequency and other vital 

operating parameters become programmable by a 

host system during operation. Beyond 

programming, communication permits remote 

data logging of the operating conditions of the 

power supply. By examining the data such as 

efficiency, output ripple, temperature rise, certain 

shifts in the measured parameters may be the 

leading indicators of pending failures. These 

trends can be used for failure prediction, downtime 

avoidance and intelligent fault management. 

In a centrally managed power supply, start-up, 

shut-down and sequencing can also be supervised 

remotely by a higher level supervisory system. 

All these options and the corresponding 

computing power on-board can open the door for 

customization of future power supplies and entire 

power systems through software. This approach 

promotes platform development and a faster 

Time to Market window. Despite the potential 

standardization of the hardware, digital control 

allows unique product differentiation through 

software. The implementation methods of the 

various power supply features remain well 

protected due to the software code security 

feature of modern microcontrollers and DSPs 

which ensures that the program can not be read 

by unauthorized users. 

6-4

In complex systems such as the 

telecommunication power infrastructure or high 

end computing environments, digital control also 

offers reduced component count even with the 

increased functionality. Fewer components mean 

lower manufacturing cost and higher reliability. 

It is important to note though that all this 

flexibility and adjustability is restricted by the 

capabilities of the power stage. For example, 

widely varying output voltages might require 

different turn ratios in the transformer and filter 

inductors must be selected with the maximum 

output current in mind. Lowering the operating 

frequency still increases output ripple although it 

might improve light load efficiency. All these 

effects of the adjustable parameters must be 

carefully considered otherwise the performance 

of the power supply can be significantly 

penalized. But it is possible to use the same 

digital controller with several versions of the 

power stage, taking advantage of its ultimate 

flexibility. 

D. Present Status of Digital Control in Power 

Management 

The “digital revolution” is in its early phase 

in power supply applications. Its present state 

resembles the motion control and UPS field just 

some 20 years ago. The first digital controllers 

operated at moderate switching frequency and 

debuted in those applications in the early ‘80’s. 

The digital control acceptance rate was 

relatively slow, despite the fact that the 

technology was readily available and capable of 

performing the job. Microcontrollers and DSPs 

had sufficient computing power to handle speed 

control, sine wave generation and other similar 

low speed control function. In addition they 

offered the possibility of communication between 

a host supervisor and the equipment. As the 

performance has improved and the price of the 

digital controllers has dropped during the years, 

the technology became standard in most motor 

control and large UPS systems. 

Digital control in power management is 

gaining considerable attention in recent years in 

academia and in the industry as well. Numerous 

publications in major conferences discuss the 

theoretical and practical aspects of digital control 

implementations. Significant interest of the 

subject had been expressed at APEC 2003 where 

the first Rap Session on digital power took place 

with participation from end users, power supply 

manufacturers and IC companies. The first 

Market Report was published by iSupply on 

digital power in early 2003. 

A closer look at the reported results confirms 

that in power supplies, digital technology might 

not yet be ready for prime time. Some of the 

problem stems from the ever present price 

pressure the industry is operating under. Like any 

new technology, digital controllers cost more 

until reasonable sales volume is reached. 

Reaching a sufficient level of production is 

delayed by the required time to learn and 

introduce new design disciplines and to address 

manufacturing needs associated with digital 

controllers. Also hindering the effort is the lack 

of appropriate analog support components to go 

along with the microcontroller or DSP. 

On the theoretical front, the majority of 

present implementations “translate” S-domain 

transfer functions to Z-domain. This approach 

permits utilization of the well understood 

linearized small signal model of the power 

supply. Once the poles and zeros are calculated to 

ensure the stability of the system, the Z- 

coefficients of the digital transfer function can be 

found easily. The weakness of this method is that 

by starting from a linearized model, the benefits 

of a higher performance non-linear control theory 

can not be fully utilized. As a result, the 

performance of power supplies using either 

digital or analog controllers are very similar 

today. 

To set realistic expectations of today’s digital 

implementations in power supplies, Table 2 

attempts to highlight the pros and cons of the 

analog and digital approaches. 

6-5

TABLE 1. COMPARISON OF ANALOG AND DIGITAL CONTROLLER 

PERFORMANCE (+ BETTER; - WORSE) 

Control Properties Analog Digital 

Switching frequency (CPU limitations) + - 

Precision (tolerances, aging, temperature effects, drift, offset, etc.) - + 

Resolution (numerical problems, quantization, rounding, etc.) + - 

Bandwidth (sampling loop, ADC – DAC speed) + - 

Instantaneous over current protection + - 

Compatibility with power components + - 

Power requirements + - 

Communication, data management - + 

Understanding theory + - 

Advanced control algorithm (non-linear control, improved transient) - + 

Multiple loops - + 

Cost of controller + - 

Cost of a platform (flexibility, time to market) - + 

Component count (comparable functionality, integration) - + 

Reliability + ? 

Achieving high switching frequency is 

definitely easier using analog controllers. 

Obtaining high enough clock frequency to 

implement direct digital pulse width modulation 

with reasonable resolution is the fundamental 

problem. Today’s digital controllers with suitable 

clock speed for high switching frequency 

operation are not cost effective and consume a 

significant amount of bias power. Another area 

where speed is critical is the performance of the 

digital controller’s analog-to-digital converter. 

The ADC’s conversion time and the number of 

instructions needed to acknowledge the result 

have an effect on the digital controller’s 

performance. Where sensing and reacting to 

certain conditions should happen simultaneously 

– peak current limiting for example – analog 

circuits still has a significant advantage over pure 

digital implementations. Furthermore, the 

repetition rate of converting important parameters 

like output voltage, impacts the bandwidth of the 

control algorithm. An additional important 

characteristic of the analog-to-digital converter is 

its resolution which can introduce rounding or 

quantization errors. These numerical issues are 

inherent in digital control and represent a new 

challenge for the power supply designer. On a 

positive note, digital components can offer better 

accuracy, great resilience against temperature 

drift and aging effects. Digital controllers are a 

better fit to implement advanced control 

algorithms and to manage multiple control loops 

if necessary. 

In the most important comparison – cost – 

digital power supply control can be competitive. 

If all the functions provided by a digital 

implementation are necessary to meet 

specification, digital controllers will come out on 

top. In this case, component count and cost will 

be significantly lower than the cost of analog 

control circuits and the required additional 

support ICs to accomplish comparable features. 

When the only task is to regulate an output 

voltage, digital controllers might have a hard 

time competing on price. In this instance, a 

bigger picture should be considered to evaluate 

the real advantages of a digital implementation. If 

the design is expected to be re-used in several 

power supplies, the flexibility and possibility of 

quick modifications in software is a very valuable 

attribute of the digital implementation although it 

could be difficult to identify its cost benefit. 

Finally, reliability is a key question. Analog 

controllers have a proven track record in power 

supply applications. They work reliably in harsh, 

noisy environment. Digital controllers have 

6-6

proven to be very reliable as well, but not 

necessarily inside a power supply. It is unclear 

whether microcontrollers and DSPs will operate 

reliably under the same circumstances. 

III. DIGITAL BASICS 

To fully understand the potential benefits of 

digital control, some basic operating principles 

and terminology must be clarified. The two 

fundamental building blocks to understand are 

the time base and how the analog signals are 

converted to digital form. These two circuits 

interface with the surrounding analog world and 

are critical to the digital controller’s performance. 

A. Generating the Time Base 

One of the first steps in the design procedure 

is to establish the operating frequency of the 

controller. It is usually defined by an on-board 

oscillator, often programmed by R-C timing 

components. A frequently used implementation 

of a simple analog oscillator is shown in Fig. 4. 

V+ 

V PEAK 

V VALLEY 

Fig. 4. Analog oscillator. 

f CLK 

RESET 

n 

COUNTER 

n 

PERIOD 

REGISTER 

R 

S 

COMPARE 

Fig. 5. Simplified digital oscillator (f CLK >> f SW ). 

Q 

Q 

f SW 

f SW 

Since the R and C values can be set to any 

desired value, this oscillator can run at any 

frequency within its wide operating range. In an 

analog implementation the controller’s clock 

frequency and the converter’s operating 

frequency (f SW ) are the same. 

On the other hand, the clock frequency (f CLK ) 

of a microcontroller or a DSP is much higher 

than the actual operating frequency of the 

converter. The digital controller uses f CLK as the 

time base for the central processor unit and its 

peripherals only. All other timing functions, 

including the switching period, must be generated 

using the internal resources of the digital 

controller. 

Fig. 5 demonstrates the principle of deriving 

the switching frequency. Once the clock 

frequency of the digital controller and the 

switching frequency of the converter are fixed, 

the switching period can be established. The 

number of clock cycles in the switching period 

can be calculated by dividing the switching 

period by the clock period. This number is stored 

in the “period register”. Every clock signal 

increments the counter by one and eventually the 

counter value will be equal to the period. At that 

time the digital comparator produces an output 

pulse which will reset the counter to zero. The 

frequency of the comparator output pulse is also 

the desired operating frequency of the converter. 

As f CLK increases with respect to f SW , more 

clock cycles become available within a switching 

period to perform the complex arithmetic 

calculations, data conversions and housekeeping 

functions. This indicates that the higher clock 

frequency has a desirable effect on the 

performance of the digital controller. 

Another important reason to push the clock 

frequency higher becomes clear when the 

relationship between the number of clock cycles 

in a switching period and the PWM resolution of 

the digital controller is investigated. An analog 

controller can command any pulse width as the 

decision is made using analog signals providing 

infinite resolution. In a digital controller the 

PWM pulse width is represented by an integer 

number of clock cycles calculated by the 

arithmetic unit, therefore the pulse width has a 

finite number of discrete values. 

6-7

TABLE 2. EFFECTIVE NUMBER OF BITS, NUMBER OF CLOCK CYCLES PER PERIOD AND DUTY CYCLE 

RESOLUTION IN %, USING TYPICAL COMBINATIONS OF SWITCHING AND CLOCK FREQUENCIES 

f SW 

f CLK - Clock Frequency (MHz) 

(kHz) 1 2 4 8 20 40 100 150 

5.3 6.3 7.3 8.3 9.6 10.6 12.0 12.6 Bit resolution (eff.) 

25 40 80 160 320 800 1600 4000 6000 Clock cycles/period 

2.50 1.25 0.625 0.313 0.125 0.063 0.025 0.017 D resolution (%) 



5 2.50 1.25 0.625 0.250 0.125 0.050 0.033 D resolution (%) 



10 5 2.50 1.25 0.50 0.25 0.10 0.067 D resolution (%) 



25 12.5 6.25 3.125 1.250 0.625 0.250 0.167 D resolution (%) 



50 25 12 6.25 2.50 1.25 0.50 0.333 D resolution (%) 



100 50 25 12.5 5.0 2.5 1.0 0.667 D resolution (%) 

The pulse width of the digital controller can 

only be multiples of the clock period. The 

important characteristics of the digital PWM 

engine can be defined as a function of the 

switching frequency and the clock frequency as 

shown in Table 2. 

For every combination there are three 

numbers in the table. The first number is called 

the effective number of bits and it signifies how 

many bits are required in the counter to be able to 

set up the desired switching frequency with a 

given clock frequency. The second number 

indicates how many clock cycles are available in 

a switching period. And the third number, which 

can be defined as: 

fCLK 

DRES(%) 

= ⋅100 

fSW 

gives the duty cycle resolution in percentage 

which is the most important parameter 

determining the performance of the digital 

controller. Due to the distinct values of the duty 

ratio of the digital controller, the output voltage 

of the converter can not be adjusted continuously. 

Depending on the difference between two 

neighboring duty cycle values, the output voltage 

resolution is also affected. A further variable to 

define how coarse the output voltage adjustment 

will be is the steady state operating duty ratio at 

nominal input, output conditions (D NOM ). 

V O,NOM 

, Normalized Output Voltage Change [%] 

10 

8 

6 

4 

2 

0 

0 

Duty Cycle Resolution (D RES 

): 

0.001 

0.005 

0.01 

0.02 

0.2 0.4 0.6 0.8 

Steady State Operating Duty Cycle (D NOM 

) 

Fig. 6. The effect of duty cycle resolution on the 

output voltage resolution as a function of 

nominal operating duty ratio. 

1 

6-8

In Fig. 6, the curves represent the percentage 

of output voltage change in response to changing 

the converter’s duty ratio between two 

neighboring discrete values. It is important to 

remember that the time difference between two 

neighboring duty ratio values is constant and it 

equals 1/f CLK . As Fig. 6 emphasizes, the same 

duty cycle step will result different output voltage 

changes depending on the nominal operating duty 

cycle of the converter. In other words, increasing 

the conduction time of the power supply’s main 

switch by one clock period (1/f CLK ) at narrow 

operating duty ratio will raise the converter’s 

output voltage more than the same change 

applied at wider nominal duty cycles. Therefore, 

in converters typically operating with narrow 

duty cycles – for example a 12V to 3.3V nonisolated 

buck converter – it is desirable to have a 

higher speed (f CLK ) digital controller even at 

moderate switching frequencies. 

To further underline the impact of the duty 

cycle resolution, consider the above mentioned 

buck converter as an application example. The 

converter operates at 250kHz switching 

frequency using an 8 MHz digital PWM engine. 

The input is 12V and the output voltage is 3.3V. 

The required operating duty ratio would be: 

VOUT 

3. 

3 

DREQ = = = 0. 

275 

VIN 

12 

The corresponding PWM pulse width is: 

DREQ 

0. 

275 

tON = = = 1. 

1µ 

s 

f 

SW 

250kHz 

This requires; 

nON = tON 

⋅ fCLK 

= 1. 1µ 

s ⋅8MHz 

= 8. 

8 

number of clock cycles. Since the digital 

controller can not put out fractional number of 

clock cycles, the on-time will be the closest 

integer number of cycles, nine. This duty cycle 

will yield an output voltage of: 

f 

SW 

250kHz 

VO ( n= 

9) 

= VIN 

⋅n 

⋅ = 12V ⋅9 

⋅ = 3. 

375V 

f 

8MHz 

CLK 

While this value might satisfy the 

requirements of the design (+2.2%), it is 

important to determine what the output voltage 

would be at neighboring duty ratios: 

fSW 

250kHz 

VO ( n= 

8) 

= VIN 

⋅n 

⋅ = 12V ⋅8 

⋅ = 3. 

00V 

fCLK 

8MHz 

fSW 

250kHz 

VO ( n= 

10) 

= VIN 

⋅ n ⋅ = 12V ⋅10 

⋅ = 3. 

75V 

f 

8MHz 

CLK 

The calculations show a 0.375V or 11.1% 

output voltage step in response to a duty cycle 

change of one clock period which is clearly not 

acceptable. A visual representation of the output 

voltage and discrete duty cycle values around the 

nominal output voltage is shown in Fig. 7. 

V O 

, Output Voltage [V] 

4.5 

4.1 

3.7 

3.3 

2.9 

V O,MAX 

V O,MIN 

n=8 

D 8 

=0.25 

n=9 

D 9 

=0.281 

n=10 

D 10 

=0.312 

Regulation 

Window 

2.5 

0.22 0.26 0.30 0.34 

Analog (D) and Discrete (D X 

) Duty Cycle 

Fig. 7. Output voltage vs. duty ratio in digitally 

controlled power supply. 

Another instance where discrete duty cycle 

values can be observed is the effect of input 

voltage change on the output voltage of the 

converter. Utilizing the infinite resolution of 

analog controllers, the output voltage is regulated 

practically at a constant level, independently 

from the input voltage. With only a finite number 

of duty ratios being available in digital control 

the output voltage can not be held at a constant 

value. Fig. 8 shows the example converter’s 

output voltage as a function of V IN around the 

nominal 12V value. 

6-9

V O 

, Output Voltage [V] 

3.6 

3.5 

3.4 

3.3 

3.2 

V O,MAX 

V O,MIN 

3.1 n=10 n=9 n=8 

D 10 

=0.312 D 9 

=0.281 D 8 

=0.25 

3.0 

10 11 12 13 14 

V IN 

, Input Voltage [V] 

Fig. 8. Output voltage vs. input voltage in 

digitally controlled power supply. 

Due to the finite number of possible duty 

ratios the converter’s output voltage will be 

proportional to the input voltage until the 

operating conditions will demand the next 

smaller duty cycle. At that moment the output 

voltage suddenly drops to the new value 

corresponding to the new duty ratio as 


B. Digitizing Variables – Voltage Sense 

In addition to the effects of discrete time 

steps the various control variables are also 

digitized in the digital controller. This introduces 

another level of complexity in the design. First of 

all it is important to note that the digital 

controller measures everything as a voltage input 

connected to an on-board analog-to-digital 

converter, usually through a multiplexer. All 

voltages monitored by the ADC must be scaled to 

the input voltage range of the ADC, generally 

between ground and the reference of the ADC. 

Typical reference levels are either 1.25V or 2.5V 

and these references can be internal or external to 

the analog-to-digital converter. After the 

conversion, the measured voltage level will be 

represented by a digital value as shown in Fig. 9. 

IN1 

IN2 

IN3 

IN4 

IN5 

n n-1 3 2 1 

MUX A-to-D 1 0 …. 1 1 0 

+ 

2 n-1 2 n-2 

Fig. 9. Voltage measurement using ADC. 

The analog-to-digital converter can be 

characterized by the number of bits of its output 

and by the time required to produce the result. 

The ADC’s number of bits is directly related to 

the accuracy of the measurement because it 

defines the resolution. When the input signal to 

the ADC is equal to (or larger than) its reference 

voltage all output bits will be 1. From this 

relationship the resolution of the ADC can be 

calculated according to: 

VREF 

res 

ADC 

= 

n 

2 

where n is the number of bits of the analogto-digital 

converter. That means that the input 

voltage range is divide into 2 n number of equal 

bands and the ADC “identifies” the band 

containing the amplitude of the input signal. In 

order to establish the resolution of the actual 

measurement the gain and accuracy of the 

external resistive divider needs to be taken into 

account as well. For instance, measuring the 3.3V 

output of the earlier introduced example using an 

8-bit ADC with a 1.25V reference will require a 

3:1 divider in front of the input of the analog-todigital 

converter. Notice that the 1.25V should 

not be used as an equivalent of the 3.3V because 

potential over voltage conditions could not be 

sensed. The 3:1 divider will allow measurement 

of the output voltage in the 0V to 3.75V range. 

Now the resolution of the output voltage 

measurement can be established as: 

VFS 

res 

Vo 

= 

n 

2 

where V FS is the full scale amplitude and n is 

the number of output bits of the ADC. In our 

example the output voltage resolution is: 

3. 

75V 

resVo = = 14. 

6mV 

8 

2 

2 2 

2 1 

2 0 

6-10

This means that the converter’s output 

voltage can change as much as 14.6mV before it 

will become evident at the output of the analogto-digital 

converter and the duty cycle could be 

modified. The ambiguity introduced by the 

measurement resolution ultimately impacts the 

regulation accuracy in power supply applications. 

The worst case error can be calculated by the 

following expression: 

VFS 

ERES 

( in%) 

= ⋅100 

n 

2 ⋅VO 

Substituting the already familiar values from 

our example yields: 

3. 

75V 

( in%) 

= ⋅100 

= 0. 

44% 

ERES ± 

8 

2 ⋅3. 

3V 

This inaccuracy is additional to the error 

introduced by the tolerance of the reference and 

the resistive divider which scales the output 

voltage level to the input range of the ADC. 

Theoretically, using more bits in the analogto-digital 

converter increases the resolution and 

consequently the measurement accuracy as 

shown in Table 3. 

ADC 

Number of bits 

TABLE 3. ADC ACCURACY AS A 

FUNCTION OF BITS 

8 10 12 14 16 

E RES (in %) 0.444 0.111 0.028 0.007 0.002 

Another property of the analog-to-digital 

converter which deserves attention is the time 

needed between the command initiating the 

measurement and when the result is available in 

the output register of the ADC. This period 

consists of two intervals, the actual time needed 

to convert the analog signal to a digital word plus 

the number of instructions used to process, store 

and read the result. Since most modern 

microcontrollers and DSPs can access the result 

in a single instruction cycle, the most important 

parameter is the conversion time. Usually the 

conversion time is given indirectly by specifying 

the number of conversions in a second. For 

example, 200ksps (kilo-samples-per-second) 

performance translates to 200,000 conversions in 

a second, i.e. 200kHz. That means that the 

conversion time is around 5µs. Since the ADC is 

an autonomous peripheral, the microcontroller or 

DSP can perform other tasks during the 

conversion. 

The conversion time is important for two 

main reasons in power supply applications. The 

first problem is that the conversion time can be 

considered as a time delay. Its effect is similar to 

having a very slow comparator in an analog 

controller. There are plenty of functions in a 

power supply where this is acceptable like under 

voltage lockout, but it is certainly not adequate 

where quick response to a fast changing 

parameter is critical, such as for current 

protection or even for peak current mode control. 

In general, it can be said that digital controllers 

can not replicate the instantaneous reaction of the 

analog controllers due to the time lag of the 

ADC’s conversion time. 

The other aspect of the conversion time is 

related to the bandwidth of the control loop. The 

sample frequency, how often the output voltage 

can be measured, will be seriously impacted by 

the conversion time of the analog-to-digital 

converter. In an analog implementation the 

output voltage is sampled in every switching 

cycle. If similar performance is expected from 

the digital controller, the switching frequency 

must be equal or less than the maximum 

frequency which can be supported by the ADC. 

Even then it should be assumed that the output 

voltage is the only parameter the ADC is 

measuring which is clearly not the case in most 

power supply applications. 

C. Digital Pulse Width Modulation 

Now that some of the basic blocks and 

characteristics of a digital controller have been 

introduced, the operation of the analog and 

digital pulse width modulator can be compared. 

Fig. 10 illustrates the fundamental process to 

obtain the operating duty ratio of a power supply 

using an analog (top drawing) and a digital 

(bottom drawing) approach. 

The analog control circuit requires a 

reference, an error amplifier and a comparator to 

determine the required duty cycle. As shown in 

Fig. 10, the output voltage is compared to a 

reference using a resistive divider at the inverting 

6-11

input of the error amplifier. The control law is 

also implemented by the error amplifier by 

selecting the appropriate R and C values to set 

the poles and zeros of the differential equations 

governing the behavior of the negative feedback 

loop. The actual duty cycle is produced by a 

simple comparator by comparing the error 

voltage to an artificial ramp which also carries 

the information of the operating frequency of the 

circuit. The duty cycle generated this way can be 

any value allowing the analog controller to 

regulate the output voltage of the power supply 

exactly at the desired amplitude. 

V O(A) 

Compensation 

V ERROR 

D A 

+ 

V O(A) 

+ 

V REF 

V REF 

ADC 

f SW 

V O(D) 

PWM 

ALU 

f CLK 

f SW 

, PWM, 

Compensation 

D D 

Fig. 10. Comparison of analog and digital PWM 

implementation. 

The digital implementation of the pulse width 

modulator starts with a similar resistive divider 

which scales the output voltage to the input 

voltage range of the analog-to-digital converter. 

As mentioned before, the input voltage of the 

ADC at nominal output voltage must be less than 

V REF to accommodate output voltages above the 

nominal value during transient operation. The 

ADC then converts the output voltage to a 

representative digital word labeled as V O(D) in 

Fig. 10. The Arithmetic and Logic Unit (ALU), 

the digital core of the microcontroller or DSP 

takes care of the rest of the functions. It can 

establish the switching frequency from the clock 

frequency of the processor (f CLK ) and it will 

calculate a value for the power supply duty cycle 

(D D ). The digital representation of the nominal 

output voltage and some of the previously 

measured V O(D) values are stored in memory and 

available for a comparison to the most recent 

output voltage level produced by the ADC. The 

control law is also executed by the digital engine 

as programmed by the software. 

Without going into digital control theory, the 

Z-domain control function of our example buck 

converter which implements the equivalent of 

two poles and two zeros for a typical type 3 

compensation can be written in the following 

form: 

2 

K1⋅ 

z − K 2⋅ 

z + K3 

G( 

Z) 

= 

2 

z − K4 ⋅ z + K5 

This equation closely resembles the usual S- 

domain transfer function of the power supply. 

The computations to execute this control law in 

the digital domain can be summarized by the next 

two equations where n refers to the present cycle, 

n-1 and n-2 are the values from the previous two 

calculations respectively. The first step is to 

calculate the error between the desired and 

measured output voltage: 

E( n) 

= VO 

, NOM 

−VO 

( n) 

Using the just calculated value of E(n) and its 

earlier values from the previous two cycles along 

with the respective duty cycle values (from the 

memory of the digital controller) the new duty 

cycle D(n) can be computed: 

D( n) 

= a2⋅ 

D( 

n − 2) 

+ a1⋅ 

D( 

n − 1) 

+ b2⋅ 

E( 

n − 2) 

+ b1⋅ 

E( 

n − 1) 

+ b0 ⋅ E( 

n) 

6-12

The coefficients of the equation can be 

obtained by simple mathematical manipulations 

from the S-domain transfer function or 

synthesized directly from the component values 

of the power supply. These constants are stored 

in the memory of the digital controller and as 

such can be easily modified during debug or even 

while the power supply is running according to a 

specific mode of operation. 

D. Limit Cycle Oscillation 

To ensure stability with a digital controller, 

there are two fundamental requirements which 

must be satisfied. The first one is the traditional 

small signal stability criteria which is addressed 

by the appropriate selection of the various 

constants in the control law equations. 

The second constraint involves the time 

domain resolution of the digital PWM engine and 

the voltage resolution of the analog-to-digital 

converter. This unique problem is demonstrated 

in Fig. 11. 

ADC resolution 

PWM 

resolution 

V O 

=high 

V O 

=OK 

V O 

=low 

V O 

D 

V O,NOM 

Fig. 11. Demonstration of limit cycle oscillation 

with digital control. 

Assume that the power supply is running in 

steady state operation with a constant duty ratio 

producing an output voltage which is in the zero 

error bin (V O =OK). When the operating 

conditions change – the input voltage increases or 

some of the load is removed – the output voltage 

starts to climb. Slight output voltage variation is 

allowed and will not change the duty cycle as 

long as V O stays within the V O =OK band because 

the analog-to-digital converter will produce the 

same result. As soon as the output goes higher 

than the upper threshold of the zero error bin, the 

ADC output will change which indicates that the 

output is too high. The digital controller mimics 

the reaction of any analog controller under the 

same circumstances and will try to compensate 

by decreasing the duty ratio. The minimum 

change in the duty ratio is a function of the clock 

period of the digital PWM engine. In Fig. 11 a 

situation is depicted where shortening the ontime 

of the main power switch by one clock 

period (1/f CLK ) results a new output voltage in the 

V O =low band. This will initiate a correction 

asking for the next larger duty cycle value which 

will bring the output voltage back to the V O =high 

band. And the cycle starts again, the output 

voltage will oscillate. The smoothing of the 

output voltage waveform in Fig. 11 is 

accomplished by the averaging L-C output filter 

of the power supply. 

The obvious problem in this example is that 

the time domain resolution is too course with 

respect to the resolution of the analog-to-digital 

converter. This phenomenon is called limit cycle 

oscillation and it can happen regardless of 

whether the design meets all conventional 

stability criteria. The solution to this dilemma is 

to follow a design procedure where the ADC 

resolution is selected first, based on the required 

accuracy of the output voltage regulation. The 

duty cycle resolution is then adjusted to the ADC 

resolution by selecting an appropriate clock and 

switching frequency combination. 

IV. PROGRAMMABLE FUNCTIONS AND 

VARIABLES 

The development of a suitable power supply 

controller is primarily driven by the answers for 

three fundamental questions: 

• What functions to provide? (in addition to 

f SW , and PWM) 

• How to implement them? 

• When to execute them? 

With an analog approach, the first two 

questions are answered by selecting the PWM 

controller and some auxiliary components to 

match the intended features. Once the 

components are chosen and interconnected, the 

functions and the control algorithm are fixed and 

the circuit becomes dedicated to the particular 

application. Any change in functionality would 

require adding more components or redesigning 

6-13

the interaction among the different sections of the 

controller. Finally, the voltage levels and limits 

are set according to the predefined or user 

adjustable thresholds and by fixed external 

components. This will define permanently when 

the functions will be carried out. 

On the other hand, the hardware of the digital 

controller is designed almost independently of its 

functionality. Only the selection of the input 

parameters might impact the available functions 

and their implementation. Practically, all three 

questions are answered by the programming of 

the microcontroller or DSP. The software can 

integrate selected subroutines to address the 

necessary control functions. The control 

algorithm can be based on complex decisions 

evaluated by the digital controller and it can be 

easily modified by changing a few lines of code 

in the programming. The different thresholds and 

limits are also defined in the software as 

variables and their value can be modified easily. 

Through this mechanism, many operating 

parameters of the power supply can be 

customized without ever changing any 

component value in the circuit. 

Accordingly, programmability and flexibility 

are the most significant differentiators in favor of 

the digital power supply controllers. 

A. Miscellaneous Control Functions 

With a powerful processor, the digital 

controller is capable of performing many more 

functions beyond the basic voltage regulation 

task. By measuring just a few more working 

parameters of the power supply, a host of 

intelligent control and protection functions can be 

implemented. Some of the data and variables 

which can be easily made available for the digital 

controller through its analog-to-digital converter 

or by values stored as variables in memory are: 

• Input voltage 

• Average input current 

• Average output current 

• Operating temperature 

• Other output voltages in the system 

• Host supervisor with serial bus 

communication capability 

• DC Transfer function of the converter 

• Variable examples: 

- V OUT 

- V OVP 

- I OUT,MAX 

- P OUT,MAX 

- V IN,MIN 

- V IN,MAX 

- I IN,MAX 

- I PK,MAX 

- f SW 

- D MAX 

- V·s MAX 

- D MIN 

- t SS (soft-start time) 

A partial inventory of the possible functions 

using these additional measurements and 

variables is summarized in the following list: 

• Switching frequency modulation 

• Input voltage monitoring (UVLO, line OVP) 

• Shutdown, Enable 

• Soft-start profile 

• Sequencing – sync. rectifier control 

• D MAX limit 

• Volt-second clamp 

• Green mode operation (burst mode, D MIN 

limit) 

• Transient overload response 

• Current limit profile 

• Output characteristic (droop, constant power) 

• Temperature protection (derating, shutdown) 

• Communication 

Since these functions would be implemented 

in software, the behavior of the system could be 

tailored to specific applications rather easily. 

That’s where the flexibility of the digital 

controller would be the most valuable in contrast 

to the hard wired responses of analog controllers. 

Switching Frequency Modulation 

Because the operating frequency is defined 

by the digital controller, it can be managed 

through software. There are several applications 

where variable frequency operation can be 

beneficial. Off-line power supplies can take 

advantage of spreading EMI noise spectrum by 

slowly modulating the switching frequency of the 

converter in a relatively narrow band around the 

nominal operating frequency. This could reduce 

input EMI filter requirements, offer smaller size 

and lower cost. Another application where this 

6-14

opportunity might be welcomed is to meet green 

mode power consumption limit in standby. In 

most green mode implementations high 

efficiency, low power standby mode is facilitated 

by reduced switching frequency or by burst mode 

operation, both achievable by controlling the 

switching frequency using the digital controller’s 

software routines. 

Input Voltage Monitoring 

Knowing the input voltage of the converter 

allows the digital controller to accomplish some 

additional control functions. The most basic ones 

are line under voltage lock out (UVLO) and line 

over voltage protection (OVP). To realize these 

functions, the valid input voltage range of the 

converter is stored in the digital controller’s 

memory and the measurement is compared to 

those limits. When the input voltage is outside of 

the operating range, the power stage is disabled 

and all other operations of the controller can be 

suspended. This technique allows low power 

operation of the microcontroller or DSP because 

its clock frequency can be significantly reduced. 

It is also possible for the microcontroller to enter 

standby mode between measurements since all 

other tasks are put on hold until the input voltage 

returns to the nominal range. 

Some of the more sophisticated functions 

based on the actual input voltage level could be 

brown out protection when the converter’s input 

power is limited during brown out conditions. 

Another option is to implement an advanced 

volt-second clamp to protect the transformer from 

saturation in isolated topologies. When voltsecond 

clamping is employed in analog 

controllers, designers often face the trade off 

between fast transient response and effective 

protection due to the duty cycle limiting effect of 

the volt-second clamp. The ultimate flexibility of 

the digital control algorithm could help to 

overcome this trade-off according to the flow 

chart shown in Fig. 12. 

START V*S 

MEASURE 

V IN 

CALCULATE 

D VS 

END V*S 

START D PWM 

READ 

V OUT 

CALCULATE 

D PWM 

READ 

D VS 

D PWM 

>D VS 

YES 

COUNT= 

COUNT+1 

COUNT>5 

YES 

SET 

D LIM 

=D VS 

D PWM 

>D LIM 

YES 

SET 

D PWM 

=D LIM 

NO 

NO 

NO 

SET 

COUNT=0 

SET 

D LIM 

=D MAX 

D MAX 

ROUTINE 

DYNAMIC V S ROUTINE 

PWM ROUTINE 

STATIC V S ROUTINE 

END D PWM 

Fig. 12. Advanced volt-second clamp routine. 

6-15

Isolated converters frequently adhere to a 

maximum duty cycle limit (D MAX ) especially if 

they employ a single ended topology. D MAX is 

usually set during the power stage design and 

corresponds to operation at minimum input 

voltage. At that point D MAX =D VS , the volt-second 

duty ratio limit, calculated as a function of the 

input voltage. At higher input voltages the 

volt-second limit reduces the maximum operating 

duty cycle according to: 

VOUT 

N 

P 

DVS = ⋅ ⋅1. 

2 

VIN 

N 

S 

In this equation the volt-second clamp is set 

20% above the nominal duty ratio of the 

converter as indicated by the 1.2 multiplier. The 

lower of D MAX or D VS limits the actual duty ratio 

calculated by the controller based on the output 

voltage error (D PWM ). In normal, steady state 

operation none of these limits impact the 

operation of the power supply. 

The software routine illustrated in Fig. 12 

would allow the converter to operate beyond the 

volt-second limit for 5 cycles to accommodate 

fast transient response before cutting back the 

allowable maximum duty ratio to protect the 

converter. During the five transient cycles this 

example uses D MAX to limit the maximum 

operating duty ratio but the software could be 

easily modified to provide more protection if 

needed. 

Since the input voltage change is relatively 

slow, it will not be sampled in every switching 

period to save computing resources. Therefore, 

the static volt-second routine is independent from 

the PWM calculation as shown in Fig. 12 and 

once it is executed, its result can be used until the 

next calculation is completed. 

Current Sense 

The digital controller can also measure the 

input, output or both currents of the power 

supply. The collected current information can be 

utilized to implement various types of current 

limiting methods or can be combined with other 

parameters to customize the power supply’s 

output characteristic under overload conditions. 

The most frequently used current limit 

techniques include: 

• Constant output current 

• Foldback 

• Transient ride through (delayed shutdown) 

• Hiccup (shut down & retry) 

• Shutdown (permanent lock out) 

When foldback current limit is required, the 

output current must be measured and controlled 

as a function of the output voltage. The digital 

controller could implement the following 

relationship: 

IO( 

VO 

) = I 

MIN 

+ RLOAD( 

MIN ) 

⋅VO 

In addition, the maximum output current can 

be limited as well by comparing the result of the 

above equation to an absolute limit stored in the 

parameter table in memory. 

Transient current limit of the converter could 

be established in software by a simple routine 

similar to the one used for the dynamic override 

of the volt-second clamp (Fig. 12). Hiccup and 

shutdown type current limit actions are even 

simpler and lend themselves for easy execution in 

digital control. What will differentiate the digital 

implementation from traditional analog circuits is 

the possibility to effortlessly adjust the current 

limit threshold either through the programming 

interface (communication) or as a function of 

operating parameters like temperature. 

Furthermore, it is conceivable that the controller 

could switch between the different over current 

protection methods based on a pre-programmed 

algorithm during operation. One example for 

changing between different current limit methods 

is the incorporation of constant output power 

characteristic. Frequently done even with analog 

controllers in telecom rectifiers, in the nominal 

range (for instance, between 43V and 58V 

output) the current limit is a function of the 

output voltage to utilize the maximum power 

throughput of the converter. At low output 

voltages, power limiting would cause excessive 

current stress, thus the control changes to limit 

the current at a safe maximum value (constant 

output current characteristic). 

6-16

Soft-Start Operation 

The two most common soft-start methods 

used in integrated analog PWM controllers are 

shown in Fig. 13. These techniques are called 

open loop soft-start because the voltage 

regulation loop is open during the soft-start time 

interval. That also means that control must be 

asserted by some other means instead of the 

voltage error amplifier. In both examples the 

controlling variable is the voltage across the softstart 

capacitor, C SS . 

The top drawing depicts a voltage mode 

implementation since the control quantity is 

compared to a sawtooth waveform derived from 

the oscillator. As the voltage across C SS slowly 

ramps up, the operating duty cycle of the 

converter increases until the nominal value is 

reached. At that time the voltage regulation loop 

becomes operational and takes over the duty 

cycle control. According to the voltage mode 

operation just described, during soft-start the 

converter’s duty ratio is a simple function of the 

capacitor voltage which linearly increases with 

time. In other words the task at hand is to 

increase the duty ratio from zero to D NOM during 

the time defined by the value of the soft-start 

capacitor. 

This could not be easier to implement in a 

digital controller. The soft-start time can be given 

and the software can impose a gradually 

increasing maximum duty cycle limit on the 

PWM output to emulate the operation of the 

analog circuit. 

In the current mode implementation, as 

shown in the lower part of Fig. 13, the soft-start 

capacitor voltage controls the maximum current 

of the main power switch. The PWM comparator 

matches up the current sense voltage to the 

linearly increasing C SS voltage. Similar to the 

voltage mode operation, during soft-start the 

voltage loop is open. This algorithm implements 

soft-start by increasing the peak current limit 

from zero to full current capability during the 

time interval defined by the value of C SS . 

Again, this behavior can be replicated simply 

by ramping up the current limit threshold 

according to the required soft-start time stored in 

the program of the digital controller. 

I SS 

C SS 

V CT 

D(V SS 

) 

I SS 

PWM 

comparators 

C SS 

V CS 

I PK 

(V SS 

) 

Fig. 13. Typical soft-start circuits in analog 

PWM controllers. 

Temperature Monitoring 

Several microcontrollers and DSPs are 

equipped with on-board temperature sense 

elements or can measure temperature using an 

external sensor. As implied in the current sense 

section, the temperature information can be 

combined with an adjustable current limit 

threshold to provide protection against 

temperature related damage of the power supply. 

In addition to derating the output power of the 

converter, over-temperature shutdown with 

programmable threshold is also possible. 

Presence of a Higher Intelligence 

The controller of a power supply is just as 

good as the algorithm it implements, regardless 

of whether it is analog or digital. In an analog 

controller the algorithm gets embedded in the 

hardware during the circuit development. Digital 

power supply control replaces a lot of hard wired 

responses with intelligent software based 

decisions which supervises the operation of the 

power supply. One of the cornerstones of 

establishing intelligence is communication which 

is natural to digital controllers. 

6-17

The first instance of communication is in the 

programming, when the knowledge of the power 

supply designer gets “downloaded” into the 

microcontroller or DSP. But communication can 

be maintained and utilized during the entire 

lifetime of the power supply. The digital 

controller can provide the interface between the 

converter and the external world. Established, 

industry standard protocols make it easy to 

connect to other equipments. Most 

microcontrollers and DSPs offer one or more 

serial communication bus protocols implemented 

either in hardware or through software 

programming. Some of the potential suitable 

standard buses and their basic characteristics for 

power supply applications are: 

• I 2 C – Inter-Integrated Circuit 

! 2 wire, bi-directional bus 

! 100kb/s, 400kb/s, 3.4Mb/s selectable 

speed 

! device addressable bus 

• SMBus – System Management Bus 

! I2C like bus (2 wire, bi-directional) 

! speed is between 10kb/s and 100kb/s 

! limited device addressing 

• SPI – Serial Peripheral Interface 

! 3 wire bus plus chip select (Enable) 

! 1Mb/s, 10Mb/s speed 

! Master – slave arrangement 

• Microwire 

! version of SPI 

! variable length bit stream 

• CAN – Controller Area Network 

! 2 wire, differential bus 

! up to 1Mb/s speed 

Once the communication is established the 

power supply can talk and listen to the host 

computer of the larger system or it can accept 

commands from a human operator through a 

small touch pad. This new opportunity makes 

remote control and adjustments of the operating 

parameters and limits feasible. Furthermore the 

digital controller can store and provide data about 

the operation of the unit for diagnostic purposes. 

Monitoring long term trends in the operating 

parameters can be a very useful tool to predict 

pending failures of the power supply and to avoid 

down time of the system. 

V. HARDWARE EXAMPLE 

The most computation intensive tasks for the 

digital controller are clearly the output voltage 

regulation and implementation of digital pulse 

width modulation. Also, these are the most 

difficult, new theoretical areas of digital control 

for the practicing power supply designer. But 

before facing the first endeavors with Z- 

transformations, resolution issues and speed, 

digital control can provide tremendous benefits 

for power supplies as shown in the next circuit 

example. 

A. Digitally Assisted Power Supply 

This circuit demonstrates an approach which 

can provide a bridge between pure analog and 

fully digital power supply control. The 

converter’s specification is detailed next. 

V IN = 36 V to 75 V 

V IN,TURN-ON = 33 V 

V IN,TURN-OFF = 30 V 

V OUT = 12 V 

P OUT = 100 W 

I OUT,MAX = 8.3 A 

T AMB,MAX = 55°C 

f SW = 500 kHz 

Isolation: 500 V 

Communication: 

• JTAG – for programming 

• RS-232 (UART) – monitoring, adjustments 

Microcontroller: MSP430F1232 

PWM controller: UCD8509 

Form Factor: ¼ Brick 

Topology: Resonant Reset Forward 

B. Circuit Descriptions 

The forward converter is an isolated topology 

and utilizes a simple two-winding transformer to 

transfer power across the isolation boundary. 

Like in all forward based converters, the 

transformer operates in the first quadrant of the 

core’s magnetization curve. Accordingly, the 

transformer core must be reset to its initial 

demagnetized state before the next clock period 

starts. In this converter the reset action is 

provided by the resonance between the 

magnetizing inductance of the transformer and 

the node capacitance where the primary winding 

connects to the drain of the switching power 

6-18

transistor. Since the focus of this paper is to gain 

familiarity with digital control, the detailed 

power stage design is omitted. For completeness 

the schematic is provided in Fig. 14. 

The typical building blocks of the power 

stage are easily recognizable in the schematic. In 

line with industry standard design practices the 

converter has minimum on-board input 

capacitance, only 4uF for high frequency 

bypassing. The quarter brick requires additional 

energy storage capacitors on the system board 

located close to the input terminals of the 

module. 

The power transformer is a planar magnetic 

structure, manufactured by Payton Inc. The 

primary number of turns is 7 and the secondary is 

5 turns. There is a third auxiliary transformer 

winding which also has 5 turns and it is 

referenced to the primary side of the power 

supply. It is used for the bootstrap bias supply. 

When the converter is switching, the power 

consumption of the controller and gate drive 

circuit exceeds the current capability of the high 

voltage bias circuitry which draws power directly 

from the input terminal during start up. The 

bootstrap bias supply provides an efficient way to 

power the primary side control circuit while the 

converter is running. Since the input voltage can 

vary over a two to one range, the bootstrap 

supply uses an averaging L-C filter to generate a 

quasi regulated 12V rail. 

The forward converter utilizes the 

SUM65N20-30, 200V, 30mΩ MOSFET from 

Vishay as the main switching transistor. Its 

current is measured by a 50:1 current sense 

transformer which is terminated by a 3Ω current 

sense resistor and fed to the controller through a 

low pass filter. 

Due to the 12V output and its simplicity, 

rectification is implemented by two Schottky 

diodes on the secondary side of the transformer. 

Both diodes are equipped with a small R-C 

snubber to reduce the ringing on the switching 

waveforms. 

The averaging output filter is designed for 

approximately 12A as opposed to the specified 

8.3A maximum to allow experimenting with 

different current limit strategies. The output 

inductor value is 10µH. There are three output 

capacitors in parallel, an 83µF polarized energy 

storage capacitor and two high frequency filter 

components, 1µF and 0.1µF. 

The schematic in Fig. 14 also indicates the 

different signal connections to the control circuit 

which is shown in Fig. 15. 

+V IN 

+V OUT 

CS+ 

MBR0530 

10uH 

47n 3 150 50:1 

0.1uF 

SUM65N20-30 

OUT 

5 

-V IN 

-VO 

CS- 

7.5 

VIN 

7T 5T 1n 82uF 

4uF 

0.1uF 470uH 

7.5 1n 

+12V 

16V 

2x 

47uF 

5T 

-V 

BAS21 

OUT 

-12V 

2x 

1uF 

MBR20100CT 

VDS 

MBR0530 

GND 

+VO 

Fig. 14. 100-W resonant reset forward power stage. 

6-19

OUT 

+12V 

-12V 

10 

47uF 

1uF 

100p 

56p 

10n 

5k 

1k 

CS+ 

CS- 

VIN 

UCD8509 

14 

ENA HV 

1 

13 

ISET VDD 

2 

12 

AGND OUT 

3 

11 

3V3 PGND 

4 

5 10 

CS 

CLK 

9 

CLF ILIM 

6 

7 8 

MODE 

FB 

750 

180p 

MOC206 

1k 

2.7n 

TL431 

+VO 

52.3k 

150pF 

72k 

13.7k 

-VO 

750 

1uF 

147k 

2.5k 

1 

2 

3 

MSP430F1232 

TEST I/O-Program 

VCC I/O-TestData 

I/O-R OSC 

I/O-Program 

28 

27 

26 

JTAG connector 

PROGRAMMING/TEST 

VDS 

4 

VSS(GND) 

I/O-Program 

25 

BYD77D 

100k 

5 

6 

XOUT 

XIN 

I/O-TimerA_CR 

I/O-TimerA_CR 

24 

23 

15k 

7 

RST/NMI I/O-TimerA_CR 

22 

10k 

1.1M 

1k 

8 

I/O-ADC0 

I/O-ADCCLK 

21 

100p 

27.4k 

1.07M 

11k 

1k 

1.8n 

R 

10k 

T 

100p 

40k 

20k 

10k 

9 

10 

11 

12 

13 

14 

I/O-ADC1 I/O-ADC4-Ref+ 

I/O-ADC2 I/O-ADC3-Ref- 

I/O-ADC5 I/O-ADC7 

I/O-SPIbus I/O-ADC6 

I/O-SPIbus I/O-UART 

I/O-SPIbus I/O-UART 

20 

19 

18 

17 

16 

15 

10k 

1n 

1k 

1.15k 

3.6k 

RS232 Port 

COMMUNICATION 

Fig. 15. Digitally assisted power supply controller of the forward converter. 

6-20

The controller operates with a fixed, 500kHz 

switching frequency and implements current 

mode control using the primary switch current 

information. The primary side control circuit is 

comprised of two ICs representing the 

demarcation between analog and digital control 

functions. The digital portion of the control 

algorithm is implemented in the MSP430F1232. 

The microcontroller is connected to the power 

stage and powered through the UCD8509 type 

analog controller which was specifically 

developed for digital power supply control 

applications in single ended converters. The 

regulation of the power supply’s isolated output 

is performed by the opto isolated error amplifier 

section based on the popular TL431 integrated 

circuit. 

C. Functional Description 

The division between analog and digital 

control functions is based on the capabilities of 

the selected processor and the amount of 

computational resources needed to perform the 

control functions. In general, the more high speed 

control functions are moved to the digital 

domain, a higher performance, more expensive 

microcontroller or DSP is needed to execute the 

control algorithm. The most difficult functions 

for the digital controller are the voltage 

regulation loop, the digital pulse width 

modulation, the implementation of peak current 

mode control with slope compensation or input 

voltage feed forward in voltage mode control and 

over current protection. These functions 

correspond to fast changing signals which have to 

be measured and recalculated on the switching 

frequency basis or require immediate action to 

protect the power supply. The utilization of a 

dedicated analog building block can remove the 

burden of these computation intensive tasks from 

the processor and allow using a cost effective 

microcontroller. In addition, using analog circuits 

for the basic high speed power supply functions 

also permits the use of familiar analog control 

principles to ensure the stability of the power 

supply. The development of an analog controller 

also presents the opportunity to optimize the 

partitioning and the signal interface between the 

digital and analog portions of the controller. 

Analog Functions – UCD8509 

The UCD8509 is a highly integrated analog 

companion chip to a microcontroller to 

implement digitally assisted power supply 

control. Its primary purpose is to provide high 

speed, analog pulse width modulation and secure 

over current protection. It also includes all 

auxiliary housekeeping function to service the 

microcontroller and a specialized interface to 

effectively communicate using only a few digital 

signals. The simplified block diagram is 

illustrated in Fig. 16. 

ENA 

ISET 

AGND 

3V3 

CLK 

CLF 

FB 

1 

2 

3 

4 

5 

6 

7 

3.3V 

VDD 

3.3V 

BIAS REG. 

CURRENT 

LIMIT 

UVLO & 

BIAS OK 

START UP 

REG. 

PWM 

14 HV 

Fig. 16. UCD8509 simplified block diagram. 

13 

12 

11 

10 

9 

8 

VDD 

OUT 

PGND 

CS 

ILIM 

MODE 

In telecom or similar input voltage 

applications, an on-board start up regulator 

provides initial bias to the chip which can be 

connected directly to the input power source. The 

start up regulator’s maximum input voltage is 

110V. Once the power supply is up and running, 

the start up regulator turns off and the auxiliary 

power must be provided by a bootstrap power 

supply as shown in the schematic diagram in 

Fig. 14. The bootstrap voltage must be between 

8V and 15V which is the recommended operating 

voltage range of the UCD8509. 

The on-board 3.3V regulator draws power 

from the VDD rail and provides bias to the IC’s 

internal circuits and to the microcontroller. The 

maximum external current consumption must be 

kept below 10mA, thus using a low power 

microcontroller is desirable. 

6-21

The UCD8509 includes a high current output 

to drive the gate of an external power MOSFET. 

The gate driver switches between ground and the 

actual VDD voltage and has approximately 4A 

sink and 2.5A source current capability. 

The controller also accommodates a high 

speed analog PWM section which can be set up 

for voltage or peak current mode operation 

according to the MODE input. The operating 

mode can be selected by shorting the pin to 

ground or to 3.3V, or by the microcontroller 

driving the MODE pin directly. While the 

UCD8509 has no oscillator, an internal local 

ramp generator is employed for the pulse width 

modulation in voltage mode. The same ramp 

generator is used to provide slope compensation 

in current mode. The slope of the ramp is 

adjusted by an external resistor connected to the 

ISET pin. The converter’s operating duty cycle is 

controlled by the error voltage which has to be 

connected to the FB pin. 

One of the most important features of the 

UCD8509 is to provide instantaneous and 

autonomous over current protection for the power 

stage without any help from the microcontroller. 

This function is implemented in the current limit 

block. For autonomous operation the UCD8509 

has a default, internally set 0.5V current limit 

threshold which can be overridden by the 

microcontroller or by an external resistor network 

through the ILIM terminal. For added protection, 

the current limit adjustment range is internally 

limited between ground and twice the default 

value, i.e. between 0V and 1V. In case the cycle 

by cycle current limit circuit is activated, the 

UCD8509 will set the current limit flag (CLF) 

output high which can be read by the digital 

controller. The flag is automatically cleared 

before the beginning of the next switching period 

making it easy for the microcontroller to count 

the number of switching periods terminated by 

the current limit circuit. 

The operating principle of the UCD8509 and 

the interaction between the microcontroller and 

the analog PWM block can be explained using 

the timing diagram in Fig. 17. 

UVLO & 

BIAS OK* 

Start up Steady State Current limit 

ENA 

CLK 

RAMP* 

FB 

PWM* 

OUT 

CLF 

* - Internal signals 

Fig. 17. UCD8509 timing diagram (voltage mode operation). 

6-22

During initial start up the UCD8509 

establishes its own bias voltage (VDD) and the 

3.3V bias for the microcontroller. During this 

time the CLF output is high, indicating for the 

digital circuit that the analog functions are not yet 

available. When all internal voltages are at their 

nominal level the CLF signal is cleared and the 

operation can commence. At that time the 

microcontroller is expected to enable the 

operation by setting the enable signal high and 

start sending the CLK pulse train. 

The CLK signal carries two important pieces 

of information to supervise the operation of the 

UCD8509. As shown in Fig. 17, coinciding with 

the rising edge of CLK signal the pulse width 

modulator is reset and the gate drive output turns 

on indicating the beginning of the next switching 

period. Thus the switching frequency is 

determined by the rising edge of the waveform. 

The width of the CLK pulse limits the maximum 

on-time of the gate drive output. In fact, the duty 

ratio of the CLK signal is used as a variable 

maximum duty cycle clamp. According to the 

functions programmed in the microcontroller, the 

width of the CLK pulse is continuously 

recalculated by the digital controller and can be 

used to implement several control functions. 

Fig. 17 exemplifies how to use the CLK pulse 

width to implement soft-start. 

During normal operation the converter’s duty 

ratio is less than the limit imposed by the digital 

controller, hence it is determined strictly by the 

analog PWM circuit of the UCD8509. Therefore 

the time domain resolution of the microcontroller 

is not a concern anymore. Assuming that the 

voltage regulation loop is also analog, as it is the 

case in the example power supply in Fig. 14 and 

15, the small signal stability of the power supply 

can be ensured by obeying the familiar analog 

rules. 

In current limit, the UCD8509’s cycle-bycycle 

current limit comparator overrides both 

duty cycle values – the pulse width of the CLK 

input and the duty cycle of the analog pulse width 

modulator. The gate drive pulse terminates when 

the switch current reaches the current limit 

threshold. The threshold can be the default value 

or the adjusted voltage present at the ILIM pin. 

When the current limit circuit is activated the 

CLF signal goes high for the remainder of the 

switching period and the information can be 

managed by the microcontroller according to its 

software. 

An important feature of the current limit 

block is its complete independence from the 

signals of the digital controller. The current limit 

event is latched and kept in the memory of the 

UCD8509 until the next switching period is 

initiated by the microcontroller. This technique 

can protect the power stage in case the digital 

controller stalls. The CLK input can freeze in 

either state, the current limit circuit will protect 

the power stage and keep the power switch off 

until the pulse train is restored and the next rising 

edge of the CLK signal resets the current limit 

circuit. 

Software Functionality 

Since the UCD8509’s control functionality is 

limited to pulse width modulation, peak current 

limiting and start up bias generation, all other 

control functions on the primary side of the 

power supply must be executed by the digital 

controller. Accordingly, the MSP430F1232 

controls the following functions in the 

demonstration power supply: 

• Operating frequency 

• Input line UVLO 

• Input line OVP 

• Absolute duty cycle limit – D MAX 

• Volt-second clamp – D LIM (V IN ) 

• Soft-start – D LIM (t SS ) 

• Current limit threshold adjustment 

• Current limit profile (delayed shutdown based 

on the number of allowable events) 

• Temperature shutdown 

• MOSFET over voltage protection 

In order to perform these functions the 

microcontroller needs to know the following 

variables: 

• f CLK – its own clock frequency 

• f SW – switching frequency 

• V IN,ON – turn-on input voltage thresholds 

• V IN,OFF – turn-off input voltage thresholds 

• D MAX – maximum allowable duty ratio based 

on the reset requirements of the transformer 

• DC transfer function – to calculate 

appropriate volt-second limit 

6-23

• t SS – duration of the soft-start interval 

• T MAX – maximum board temperature 

• V DS,MAX – highest acceptable drain-source 

voltage 

These numbers can be entered through the 

graphical user interface of the demonstration 

software and will be incorporated in the 

executable code of the microcontroller. The 

screen shot of the demonstration software’s user 

interface is pictured in Fig. 18. 

In addition to the values entered by the user, 

the digital controller must measure and handle 

four more inputs: 

• V IN – input line voltage 

• V DS – drain to source voltage 

• T BOARD – board temperature 

• CLF – current limit flag 

The demonstration hardware measures two 

additional parameters for future expansion of the 

software functionality. These are V FB and I IN,AVE , 

the feedback voltage and the average input 

current, respectively. 

Fig. 18. Graphical user interface of the demonstration software. 

6-24

Setting the Operating frequency 

The MSP430F1232 is set up with a core 

clock frequency of 8MHz which frequency 

corresponds to the execution of the program 

instructions. The microcontroller can be tricked 

to operate its PWM timer at twice the clock 

frequency, which opportunity was utilized in this 

design. Based on f CLK =16MHz and f SW =500kHz, 

the switching period consists of: 

6 

16 ⋅10 

Hz 

n = 

= 32 

3 

500 ⋅10 

Hz 

clock cycle of the PWM timer. Accordingly, 

the minimum duty cycle adjustment can be 

calculated as: 

1 

∆ t = = 62. 

5ns 

6 

16 ⋅10 

Hz 

or the duty cycle resolution is given as: 

3 

∆ D = 500 ⋅10 

Hz ⋅62. 5ns = 0. 

03125 

Because the pulse width modulation is still 

done in analog by the UCD8509, the 

microcontroller’s resolution impacts only the 

accuracy of the maximum duty ratio and the 

volt-second limit. For these functions the 

achieved resolution is sufficient. 

Since the core of the microcontroller runs 

only with an 8 MHz clock frequency, every 

switching period contains 16 instruction cycles 

for program execution. 

Maximum Duty Cycle 

The power stage design allows a maximum 

operating duty ratio of approximately 80% to 

accommodate the reset time of the transformer. 

To provide some margin the controller is set up 

to limit the duty ratio at 75% or 24 clock cycles 

of the PWM timer (32·0.75=24). 

Input Voltage Measurement 

Knowing the actual input voltage value 

allows the digital controller to perform several 

housekeeping and protection functions. In this 

design the input voltage is measured by the onboard 

analog-to-digital converter. Since the ADC 

input is limited to the 0V – 2.5V range by the 

reference of the analog-to-digital converter, the 

anticipated input voltage range must be scaled 

down to meet this constraint. Assuming 100V 

maximum input voltage transient, the gain of the 

resistive divider can be calculated as: 

2. 

5V 

G INPUT 

= = 0. 

025 

100V 

This factor is implemented by the 1.07MΩ 

and 27.4kΩ resistors which are connected to the 

ADC6 input of the MSP430F1232 through an 

additional noise filter as shown in Fig. 15, the 

schematic diagram of the controller. 

The ADC of the MSP430F1232 is a 10-bit 

analog-to-digital converter, therefore the 100V 

full scale input voltage range is represented by 

2 10 =1,024 individual values and the measurement 

resolution is: 

100V 

resINPUT 

= ≅ 98mV 

10 

2 

As this number indicates it is really easy to 

accurately adjust the turn-on or turn-off input 

voltage levels of the power supply. The 

demonstration circuit uses the result of the input 

voltage measurement to provide software 

programmable line under and over voltage 

protection with user adjustable hysteresis and to 

implement an input voltage dependent duty ratio 

limit, also known as volt-second clamp. The V·s 

clamp is based on the DC transfer function of the 

power stage and can be calculated as: 

VOUT 

N 

P 

1 

DLIM 

( VIN 

) = ⋅ ⋅1. 

2 ≅ 18. 

5 ⋅ 

VIN 

N 

S 

VIN 

where N P and N S are the primary and 

secondary number of turns of the transformer and 

the 1.1 multiplier indicates that the volt-second 

clamp is set 10% higher than the operating duty 

ratio of the converter. The working of the voltsecond 

routine is demonstrated in Fig. 19 through 

21. 

6-25

CLK 

OUT 

V DS 

I D 

Fig. 19. Operating waveforms at V IN = 36 V. 

CLK 

OUT 

V DS 

I D 


CLK 

OUT 

V DS 

I D 


The converter’s steady state operating duty 

ratio can be deciphered from the V DS waveform 

of the switching transistor. The maximum 

allowable duty ratio (D LIM (V IN )) is calculated by 

the microcontroller and it is based on the actual 

input voltage level. Its value is represented by the 

duty ratio of the CLK waveform. As the three 

figures demonstrate, the duty ratio of the CLK 

signal is approximately 10% higher than the 

operating duty cycle of the converter at all three 

input voltages. 

Soft-Start 

The soft-start time of the converter can be 

programmed through the software and will be 

implemented by the digital controller by 

gradually increasing the duty ratio of the 

converter. It is the same method outlined earlier 

in the Soft-Start Operation section under 

Miscellaneous Control Functions. The practical 

implementation starts by calculating the number 

of duty cycle values between zero duty cycle and 

D MAX . 

6 

fCLK 

16 ⋅10 

Hz 

SSSTEPS = ⋅ DMAX 

= 

⋅0. 

75 = 24 

3 

fSW 

500 ⋅10 

Hz 

If the duty cycle limit would be increased by 

one step in every switching period the converter 

would reach maximum duty cycle in 24 

switching period or in 60us. This is an unusually 

fast start up and it is also questionable whether 

the output capacitor can be charged to the 

nominal level within this time interval. To 

achieve a reasonable soft-start time in the 

milliseconds range, each of the 24 duty cycle 

values between zero and D MAX has to be 

maintained for several switching periods. For 

instance, if the soft-start time is given as t SS =5ms, 

each duty ratio must be valid for n SS number of 

switching cycles which can be obtained as: 

3 

f 

SW 

500 ⋅10 

Hz 

nSS 

= ⋅tSS 

= 

⋅0. 

005 ≅ 104 

SSSTEPS 

24 

The effect of the gradually increasing discrete 

duty cycle values is demonstrated in Fig. 22. In 

order to show the step function in the output 

voltage waveform the soft-start time had to be 

extended to approximately 8 seconds. 

6-26

V O 

Fig. 22. Output voltage waveform with 

artificially long soft-start time. 

To override the default 0.5V current limit 

threshold of the analog current limit circuit, its 

ILIM pin voltage needs to be overridden. For 

current limit adjustment the UCD8509 expects an 

analog voltage at the ILIM terminal which can be 

generated by the microcontroller. Since the 

MSP430F1232 has no digital-to-analog converter 

on-board, the function is implemented by four of 

its digital I/O ports and an external resistor 

network as shown in Fig. 24. 

I/O-SPIbus 

I/O-SPIbus 

I/O-SPIbus 

I/O-TimerA_CR 

12 

13 

14 

22 

40k 

20k 

10k 

2.49k 

1n 

9 

ILIM 

MSP430F1232 

UCD8509 

V O 

Fig. 23. Output voltage ramp up with 5ms softstart 

time. 

The normal 5ms long soft-start waveform of 

the converter is shown in Fig. 23 and it 

demonstrates the usual monotonic ramp up of the 

converter’s output voltage. 

Current Limit Operation 

Using the capabilities of the UCD 8509, the 

digital controller is able to adjust the current limit 

threshold and also the overload behavior of the 

power supply. 

Fig. 24. Current limit adjustment using “poor 

man’s DAC”. 

The digital output ports are three state 

outputs, they can be high impedance or 

connected either to GND or to the VCC voltage 

of the microcontroller. When all four outputs are 

high impedance, the default 0.5V threshold of the 

UCD8509 prevails. Assuming that pin 22 of the 

MSP430F1232 is connected to ground, to limit 

the maximum ILIM voltage below the 1V 

maximum threshold of the UCD8509, the 

microcontroller can select from 27 individual 

current limit thresholds between 0V and 1V using 

the other three ports. 

During overload, the conduction time of the 

power MOSFET is limited by the cycle-by-cycle 

current limit circuit. When the current sense 

signal amplitude reaches the current limit 

threshold the gate drive output is immediately 

terminated to protect the power stage. This event 

is indicated by the CLF pin of the UCD8509 

going high and can be read by the 

microcontroller. The typical waveforms of the 

converter in current limit mode are shown in 

Fig. 25. 

6-27

CLK 

OUT 

V DS 

CLF 

Fig. 25. Current limit operation. 

In this design the power supply is allowed to 

operate in current limit mode for a fixed number 

of switching cycles before it shuts down. The 

number of cycles in current limit mode before 

shut down can be entered by the user through the 

GUI of the demonstrations software. This 

operating mode allows short periods of overload 

conditions – occurring typically during load 

transients – without the need to increase the 

steady state current limit of the power supply. 

Temperature Protection 

The demonstration power supply is equipped 

with a temperature shut down feature based on 

the board temperature of the module. In order to 

get a better reading of the critical temperature of 

the power components, an external sensor is 

favored over the built-in temperature sensor of 

the microcontroller. The thermistor is placed in 

close proximity to the power MOSFET. 

In order to eliminate any potential noise 

coupling, its signal is filtered near the input pin 

(pin 11 – I/O-ADC5) of the MSP430F1232. The 

shut down threshold as well as the hysteresis of 

the temperature protection is user adjustable 

using the parameter entry screen of the 

demonstration software. 

MOSFET Over Voltage Protection 

The last protection function of the converter 

is based on the peak voltage stress of the primary 

MOSFET. The maximum voltage across the 

drain source terminal of the device is scaled and 

peak rectified. Once the measured stress voltage 

reaches the user entered shutdown threshold the 

converter stops operating. The shut down is 

followed by an automatic restart, initiating the 

full soft-start routine. 

Software Algorithm 

Without going too deep into the fine details 

of the software, one important characteristic of 

the controlling algorithm must be highlighted. In 

most applications the available computational 

resources and data conversion speed necessitates 

that the execution of the software functions are 

distributed over several switching periods. 

Accordingly, the functions are divided to two 

categories; basic functions which must be 

executed in every switching period and auxiliary 

routines which are scheduled over a longer 

period. This scheduling technique is 


Timebase & CLK set 

Read T BOARD 

Start Measure V IN 


Service RS-232 port 


Update Parameters 

Check T BOARD 

limit 


Read V IN 

Start Measure V DS 


Update D LIM 


Check UVLO & OVP 


Read V DS 



Service RS-232 port 


Update Parameters 

Check V DS 

limit 


Read V IN 

Start Measure I IN,AVE 


Update D LIM 


Check UVLO & OVP 


Read I IN,AVE 



T SW 

Fig. 26. Software scheduling example. 

6-28

The diagram shows the program flow in 

steady state operation. The basic time base and 

CLK signal generation functions are performed 

in every switching cycle since they are essential 

to the proper operation of the analog companion 

circuit. In every third cycle the microcontroller 

initiates a signal measurement. The frequency of 

the ADC conversions is limited by the maximum 

speed of the analog-to-digital converter of the 

microcontroller. Since the most important input 

parameter is the input voltage, every second 

measurement cycle is dedicated to the input 

voltage measurement. In between the input 

voltage measurements the other analog 

parameters are measured in a rotating fashion. 

Once a measurement result is available, the 

microcontroller recalculates its internal variables 

and compares the measurement result against the 

limit values of the particular variable. In addition, 

a significant amount of the microcontroller’s 

resources are reserved for communication in the 

demonstration software because of the frequent 

update of the displayed results. 

Some of the software functions are assisted 

by specialized hardware resources in the 

MSP430F1232. For instance, no significant 

resources are allocated to handle the CLF signal. 

The number of current limit cycles is counted by 

the microcontroller’s capture & compare register 

which generates an interrupt when the allowed 

number of consecutive current limit cycles is 

reached. 

This short description of the software does 

not attempt to cover all aspects of the software 

development, but rather to show the level of 

expertise required to write the program. When 

power supply engineers make the first steps 

towards digital control, it might be wise to 

supplement their vast amount of power supply 

know-how with the proficiency of a skilled 

software engineer as it was the case in this 

project. 

VI. SUMMARY 

This paper aimed to introduce digital power 

supply control to the practicing power supply 

design community. Like most new technology, 

digital control in power supplies is expected to 

start its proliferation slowly. But this is definitely 

a trend not to overlook in the years to come. 

At the same time, it is important to remember 

that the power supply is still a fundamentally 

analog circuit. The knowledge of various power 

supply topologies and related analog design 

expertise can not be substituted even by the most 

advanced software algorithm. On the other hand, 

digital implementation of the converter’s control 

offers new opportunities to develop advanced 

features and make the power supply a more 

visible, more integrated part of the system. 

While transitioning to full digital control 

might require a completely different approach 

and skill set in the controller design, the circuit 

example of this paper presents a practical, 

intermediate step towards that final goal. As 

demonstrated by this converter, advanced 

features and protection functions, and 

communication capability can be integrated cost 

effectively and reliably in a quarter brick form 

factor. 

6-29

台灣新竹交通大學 808 實驗室 ( 電力電子系統與晶片設計實驗室 )

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