Modeling Techniques - é»åé»å ç³»çµ±èæ¶çè¨è¨å¯¦é©å®¤ - åç«äº¤éå¤§å¸

台灣新竹 ‧ 交通大學 ‧ 前瞻電力電子中心 808 實驗室 ( 電力電子系統與晶片實驗室 ) 

課程名稱 : 數位電源控制 (Digital Power Control) 

Modeling and Control of DC-DC Converters 

直流 / 直流轉換器之模型與控制 

鄒應嶼 

教授 

國立交通大學 

電機與控制工程研究所 

2012 年 3 月 12 日 

Power Electronic Systems & Chips Lab., NCTU, Taiwan 

Advanced Power Electronics Center, NCTU, Taiwan

台灣新竹交通大學 808 實驗室 ( 電力電子系統與晶片實驗室 ) 


Switching power converters 

+ 

+ 

+ − + 

+ 

− 

− − + 

− 

− 

PWM 

Modulator 

Loop 

Compensator 

− 

+ 

Switching converter 

power input 

Load 

+ 

v g (t) + 

– 

R v(t) 

– 

feedback 

connection 

transistor 

gate driver 

δ( t) 

δ (t) 

Pulse-width 

modulator 

v( t) 

v c 

compensator 

G c 

( s) 

voltage 

reference 

+ – Hv 

vref 

dT s 

T s 

t 

t 

Controller 

Efficiency 

Output Impedance 

Power Electronic Systems & Chips Lab., NCTU, Taiwan

課程講義 :【電力電子】 DC-DC Converter - Modeling Techniques 

交通大學 808- 電力電子實驗室 March 12, 2012 

台灣新竹 ‧ 交通大學 ‧ 電機與控制工程研究所 ‧808 實驗室 

電力電子系統晶片、數位電源、DSP 控制、馬達與伺服控制 

Lab-808: Power Electronic Systems & Chips Lab., NCTU, Taiwan 

http://pemclab.cn.nctu.edu.tw/ 

DC-DC Converters: Modeling Techniques 

鄒應嶼 

教授 

國立交通大學 

電機與控制工程研究所 

2012 年 3 月 10 日 

LAB808 

NCTU 

Lab808: 電力電子系統與晶片實驗室 

Power Electronic Systems & Chips, NCTU, TAIWAN 

台灣新竹 • 交通大學 • 電機與控制工程研究所 

Filename: \B01 投影片 :【1】電力電子 ( 研究所 )\PE-07:【1 基礎】02:DC-DC - Modeling Techniques.ppt 

1/107 

DC-DC Converters: Modeling Techniques 

1. Modeling of Switching Converters 

2. State-Space Averaging Technique 

3. PWM Switch Modeling Technique 

4. CIECM Modeling Techniques 

5. Modeling of Current-Mode DC-DC Converters 

6. Difficulties with Modeling and Control of SPS 

2/107 


電源系統與晶片、數位電源、馬達控制驅動晶片、DSP/FPGA 控制 



1




Modeling of Switching Converters 

電力電子系統與晶片實驗室 

Power Electronic Systems & Chips Lab. 

交通大學 • 電機與控制工程研究所 

3/107 

Modeling of Switching Converters 

• Why Modeling ? 

• Classification of Modeling Techniques 

• Modeling of Switching Power Converters 

• State-Space Averaging Technique 

• Transfer Functions 

• Small-Signal Equivalent Circuit Model 

4/107 





2



Objective of Modeling 

Static Characteristics 

Objective of Modeling 

Analysis 

Simulation 

Design 

Efficiency 


5/107 

Difficulties with Modeling of SPS 

Nonsmooth Systems (time and state discontinuity) 

Nonlinearity due to operating point 

Concepts of existence, uniqueness, stability not clearly 

defined for systems with discontinuous right half-plan zero 

Inherent Nonlinear Dynamic Behavior! 

Concept of chaotic dynamics relatively new to power 

electronics 

Magnetics 

Noises and EMI 

Thermal and Temperature Distribution 

6/107 





3



Working Profile of a Switching Converter 

v o 

Power-on 

i o 

Dell power edge 2400 (web/SQL server) 

Power-off 

Watts 

% CPU time 

7/107 

Static Characteristics of a DC-DC Converter 

L 

Buck 

v i 

D 

C 

v o 

L 

D 

Boost 

v i 

C 

v o 

D 

Buck-Boost v i L C 

v o 





4



Operating Region Operating Point Operating Mode? 

1.0 

V 

V 

OUT 

IN 

D = 1.0 

0.9 

V IN 

= constant 

0.75 

0.50 

DCM 

CRM 

0.7 

0.5 

CCM 

V 

OUT(max) 

V 

IN(min) 

0.25 

0.3 

0.1 

V 

OUT(min) 

V 

IN(max) 

0 

0 0.5 1.0 1.5 2.0 

I OUT(min) 

I OUT(max) 

I 

( 

I 

o 

LB, max 

) 

9/107 

Operating Point Steady-State Trajectory 

1.0 

V o /V i = 1.0 

D = 1.0 

Itest 

0.75 

0.9 

0.7 

I test 

2A 

R o 

= 500Ω 

CCM 

0.5 

0.5 

5msec 

100msec 

0.25 

0 

0.3 

DCM 

0.1 

20% 40% 50% 60% 80% 90% 100% 110% 

If the components are not ideal, its parasitic 

parameters will change its static curves. The 

illustrated example is obtained with the 

following parameters: 

R DS(ON) = 50 mΩ 

MOSFET reverse diode voltage drop = 0.7V 

Diode voltage drop = 0.7V 

Inductor ESR = 25mΩ 

Capacitor ESR = 2mΩ 

10/107 





5



Operating Point Small-Signal Perturbations 

1.0 

V o /V i = 1.0 

D = 1.0 

電流負載的步階切換 ! 

0.9 

0.75 

0.7 

CCM 

Step Load Change 

1A 

B 

0.5 

0.5 

Output Voltage 

0A 

0.3 

0.25 

DCM 

0.1 

Inductor Current 

0 

20% 40% 50% 60% 80% 90% 100% 110% 

11/107 

Operating Point Frequency Response 

Q Y = 7.070 

R o 

Q B = 3.535 

Q A = 1.414 

Q X = 0.707 

D = 1.0 

0.9 

OPY 

0.7 

Q B 

= 3.535 Q A 

= 1.414 

CCM 

0.5 

Q Y 

= 7.07 

0.3 

OPX 

Q X 

= 0.707 

DCM 

0.1 

20% 40% 50% 60% 80% 90% 100% 110% 

12/107 





6



Operating Region State-Variable Plane 

1.0 

0.75 

0.5 

0.25 

V o /V i = 1.0 

DCM 

D = 1.0 

0.9 

0.7 

0.5 

0.3 

0.1 

CCM 

則 

有 

部 

分 

會 

進 

入 

不 

連 

續 

導 

通 

工 

作 

區 

。 

通 

工 

作 

區 

內 

, 

但 

是 

從 

工 

作 

點 

到 

工 

作 

點 

從 

工 

作 

點 

到 

工 

作 

點 

的 

軌 

跡 

均 

在 

連 

續 

導 

0 

10% 20% 

40% 60% 80% 90% 100% 110% 

13/107 

Modeling of Switching Power Converters 

• Modeling of Voltage-Mode DC-DC Converters 

- Power Stage Modeling 

• State-space average model (Middlebrook and C'uk 1977) 

• Discrete time-domain model (Lee 1979) 

• Equivalent circuit model (Chetty 1981) 

• Unified topological model (Pietkiewicz and Tollik, 1987) 

• PWM switch model (Voperian 1988) 

• Injected-absorbed-current model (Kisovski 1991) 

- Error Processor Modeling (Chetty 1982) 

- Pulsewidth Modulator Modeling 

• Describing function model (Lee 1983) 

• Equivalent circuit model (Bello 1981) 

- Larger Signal Modeling (Vicua 1992) 

• Modeling of Current-Mode DC-DC Converters 

- Equivalent Circuit Model (Chetty 1981) 

- y-parameter Model (Middlebrook 1989) 

14/107 





7



Modeling Techniques 

State Space Averaging Method 

[1] R. D. Middlebrook and S. Cuk, “A general unified approach to modeling switching-converter 

stages,” IEEE PESC Conf. Rec., pp. 18-34, 1976. [Pioneer Paper] 

[2] S. Cuk and R. D. Middlebrook, “A general unified approach to modeling switching DC-to-DC 

converters in discontinuous conduction mode,” IEEE PESC Conf. Rec., pp. 36-57, 1977. 

Modeling of Switching Converters in DCM Operation 

[1] D. Maksimovic and S. Cuk, “A unified analysis of PWM converters in discontinuous modes,” IEEE 

Trans. Power Electron., vol. 6, pp. 476–490, May 1991. 

[2] J. Sun, D. M. Mitchell, M. F. Greuel, P. T. Krein, and R. M. Bass, “Averaged modeling of PWM 

converters operating in discontinuous conduction mode,” IEEE Trans. Power Electron., vol. 16, pp. 

482-492, July 2001. 

R. D. Middlebrook and S. Cuk, “A general unified approach to modeling switching-converter stages,” 

IEEE PESC Conf. Rec., pp. 18-34, 1976. 

15/107 

Modeling Techniques .. 

PWM Switch Method 

[1] V. Vorperian, “Simplified Analysis of PWM Converters Using Model of PWM Switch Part I: 

Continuous Conduction Mode,” IEEE Trans. on Aero. and Elec. Sys., vol. 26, no. 3, pp. 490-496, 

May 1990. 

[2] V. Vorperian, “Simplified Analysis of PWM Converters Using Model of PWM Switch Part II: 

Discontinuous Conduction Mode,” IEEE Trans. on Aero. and Electron. Sys., vol. 26, no. 3, pp. 

497-505, May 1990. 

Fast Analytical Techniques for Electrical and Electronic Circuits, 

V. Vorperian, Cambridge Press, 2004. 

Vatche Vorperian, (1984) Analysis of resonant converters. Dissertation (Ph.D.), California 

Institute of Technology, Advised by S. Cuk. 

1. Introduction 

2. Transfer functions 

3. The extra element theorem 

4. The N-extra element theorem 

5. Electronic negative feedback 

6. High-frequency and microwave circuits 

7. Passive filters 

8. PWM switching dc-to-dc converters 

16/107 





8




Discrete Time-Domain Method 

[1] F. C. Lee, R. P. Iwens, Y. Yu, and J. E. Triner, “Generalized computer-aided discrete time-domain 

modeling and analysis of DC-DC converters,” IEEE Trans. IECI, vol. 26, pp. 58-69, May 1979. 

Equivalent Circuit Method 

[1] P.R.K. Chetty, Switch-Mode Power Supply Design, TAB BOOKS, Inc., 1986. 

Modeling of Current-Programmed Converter 

[1] R. D. Middlebrook, “Modeling current programmed buck and boost converters,” IEEE Trans. on 

Power Electronics, vol. 4, pp. 36-52, January 1989. 

[2] Teuvo Suntio, “Analysis and modeling of peak-current-mode-controlled buck converter in DICM,” 

IEEE Trans. on Ind. Electron., vol. 48, no. 1, pp. 127-135, Feb. 2001. 

Unified Topological Method 

[1] Pietkiewicz, A. and D. Tollik, “Unified topological modeling method of switching dc-dc converters 

in duty-ratio programmed mode,” IEEE Trans. on Power Electron., vol. 2, no. 3, pp. 218-226, July 

1987. 

Injected-Absorbed-Current Method 

[1] Kislovski, A. S., R. Redl, and N. O. Sokal, Dynamic Analysis of Switching-Mode DC/DC 

Converters, Van Nostrand Reinhold, 1991. 

17/107 


Small-Signal z-Domain Analysis 

[1] D. M.Van de Sype, K. De Gusseme, F.M.L.L. DeBelie, A. P. Van den Bossche, and J. A. Melkebeek, 

“Small-signal z -domain analysis of digitally controlled converters,” IEEE Transactions on Power 

Electronics, vol. 21, no. 2, pp. 470- 478, March 2006. 

[2] D. M.Van de Sype, K. De Gusseme, A. P. Van den Bossche, and J. A. Melkebeek, “Experimental 

verification of the z-domain model for digitally controlled converters,” IEEE Power Electronics 

Specialists Conference, vol., no., pp.2164-2170, 16-16 June 2005. 

[3] Yu-Cheng Lin; Dan Chen; Yen-Tang Wang; Wei-Hsu Chang; “A novel loop gain correction method 

for digitally controlled DC-DC power converters,” IEEE Energy Conversion Congress and Exposition 

(ECCE) pp.3530-3535, 20-24 Sept. 2009. 

Digital Current-Mode Control 

[1]Y. S. Jung, “Small-signal model-based design of digital current-mode control,” IEE Proceedings - 

Electric Power Applications, vol.152, no.4, pp. 871- 877, 8 July 2005. 

[2] S. Chattopadhyay and S. Das, “A digital current-mode control technique for DC–DC converters,” 

IEEE Transactions on Power Electronics, vol.21, no.6, pp.1718-1726, Nov. 2006. 

18/107 





9



Modeling of DC-DC Converters 

Switch-Mode Power Supplies - 

SPICE Simulations and Practical 

Designs, Christophe Basso, 

McGraw-Hill, Feb. 1, 2008. 



Computer-Aided Analysis 

and Design of Switch-Mode 

Power Supplies, Yim-Shu 

Lee, Marcel Dekker, Inc., Feb. 

23, 1993. 

Mikko Hankaniemi, Dynamical 

Profile of Switched-Mode 

Converter – Fact or Fiction?, PhD 

Thesis, Tampere University of 

Technology, 2007. 

SMPS Simulation with SPICE 3, 

Steven M. Sandler, McGraw-Hill 

Professional, Dec. 1, 1996. 

δ() 

t 

δ (t) 

T s dT s 

Pulse-width 

modulator 

t 

v( t) 

v c 

G c ( s) 

t 

+ – H v 

voltage 

reference vref 

Teuvo Suntio, Dynamic Profile of 

Switched-Mode Converter: 

Modeling, Analysis and Control, 

John Wiley, May 2009. 

Dynamic Analysis of Switching-Mode 

DC/DC Converters, Andre'S. Kislovski, 

Richard Redl and Nathan O. Sokal, Van 

Nostrand Reinhold, New York, USA, 1991 

Complex Behavior of Switching 

Power Converters, 

Chi Kong Tse, CRC Press, 2004. 

PWM Switch Modeling of DC-DC Converters 

Advances in Averaged Switch Modeling and Simulation 

Dragan Maksimovic and Robert Erickson 

Colorado Power Electronics Center (CoPEC) 

IEEE PESC1999 Seminar 

The “PWM Switch” in mode transitioning SPICE models 

PCIM Germany 2005. 

Christophe Basso – On-Semi Application Manager 

20/107 





10



Timothy Hegarty, Voltage-mode control 

and compensation - Intricacies for buck 

regulators, EDN 2008. 

Control of DC-DC Converters 

Ray Ridley, 30 Years of currentmode 

control, 2008. 

Robert Mammano, SPS Topology - 

voltage Mode versus current-mode, 

DN-62 slua119. 

Lloyd Dixon, Control loop cookbook, 

TI-Unitrode slup113a. 

Lloyd Dixon, Average Current 

Mode Control of Switching 

Power Supplies, 1990. 

BUCK Converter Control Cookbook, 

Zach Zhang, Alpha & Omega 

Semiconductor, Inc. PIC-003. 

δ (t) 

gate driver 

Pulse-width 

modulator 

v c 

compensator 

G c ( s) 

+ – 

H. P. Forghani-Zadeh and G.A. Rincon-Mora, 

"Current-sensing techniques for DC-DC converters," 

The IEEE 45th Midwest Symposium on Circuits and 

Systems (MWSCAS), Aug. 2002. 

δ() 

t 

T s dT s 

t 

v( t) 

t 

voltage 

reference vref 

J. T. Mossoba and P. T. Krein, "Design and control 

of sensorless current mode DC-DC converters," 

IEEE APEC Conf. Rec., 2003. 

Brian Lynch, Current-mode vs. voltage-mode 

control in synchronous buck converters, TI. 


Define the Source 

Output Impedance! 

L 

L 

D 

Define the Operating Point! 

v i 

D 

C 

v o 

v i 

C 

v o 

Define the Load 

Disturbance 

Z os 

v g 

v o 

i o 

v~s 

Buck Converter 

Boost Converter 

V s 

d 

v i 

L 

D 

C 

v o 

v i 

L 1 C 1 

D C 2 

v o 

R L 

~ 

i d 

Define the 

Line 

Disturbance 

 

Buck/Boost Converter 

PW M 

Modulator 

digital signal processor 

C , uk Converter 

Switching power converters 

Loop 

Compensator 

analog signal processor 

v R 

load 

Output voltage 

feedback only! 

22/107 





11



Small-Signal Modeling of a 

Buck Converter 

1.0 

0.75 

0.50 

0.25 

V 

V 

OUT 

IN 

V IN 

= constant 

D = 1.0 

0.9 

CRM 

0.7 

CCM 

0.5 

0.3 

DCM 

0.1 

I 

( 

I 

0 

0 0.5 1.0 1.5 2.0 

o 

LB, max 

) 

V. Vorperian, "Simplified 

Analysis of PWM Converters 

Using Model of PWM Switch 

Part I: Continuous Conduction 

Mode," IEEE Trans. on Aero. and 

Elec. Sys., vol. 26, no. 3, pp. 490-496, 

May 1990. 




Part II: Discontinuous 

Conduction Mode," IEEE Trans. on 

Aero. and Electron. Sys., vol. 26, no. 3, 

pp. 497-505, May 1990. 

Averaged Switch Modeling of 

Boundary Conduction Mode DCto-DC 

Converters 

J, Chen, R. Erickson, and D. 

Maksimovic, IECON 2001. 


1.0 

V 

V 

OUT 

IN 

D = 1.0 

0.9 

V IN 

= constant 




Part II: Discontinuous 

Conduction Mode," IEEE Trans. on 

Aero. and Electron. Sys., vol. 26, no. 3, 

pp. 497-505, May 1990. 

0.75 

0.50 

CRM 

0.7 

0.5 

CCM 

D. Maksimovic and S. Cuk, “A 

unified analysis of PWM 

converters in discontinuous 

modes,” IEEE Trans. Power 

Electron., vol. 6, pp. 476–490, 

May 1991. 

0.3 

DCM 

0.25 

0.1 

I 

( 

I 

0 

0 0.5 1.0 1.5 2.0 

o 

LB, max 

) 

J. Sun, D. M. Mitchell, M. F. 

Greuel, P. T. Krein, and R. M. 

Bass, “Averaged modeling of 

PWM converters operating in 

discontinuous conduction mode,” 

IEEE Trans. Power Electron., 

vol. 16, pp. 482-492, July 2001. 

24/107 





12



Systematic View of DC-DC Converters 

Selection of Switching Frequency and PWM Strategies 

Efficiency 

Time Responses 

Frequency Responses 


Current Injection Testing 

PWM DC-DC Power Conversion and Regulation 

v i 

v o 

v p 

v x 

D 

Z f 

Z i 

D T ON 

= 

T ON 

T 

T 

v x 

v ref 

CLOCK RAMP 

26/107 





13



Signal Composition of a PWM DC-DC Converters 

v g 

$v g 

v $v 

V 

V g 

i g 

I g 

i $i 

I 

load 

$d 

$i g 

clock ramp 

D 

v c 

$v c 

modulatorpower-stage 

subsystem 

comparator 

V c 

analog 

amplifier 

reference 

27/107 

Frequency Spectrum 

output 

spectrum 

bandpass 

filter 

frequency 

f 2f 3f f s - f f s f s+ f 2f s 3f s 

28/107 





14



AC and DC Quantities in a PWM Switching DC-DC 

Converter 

v o 

$v o 

Analysis of Dynamic Responses 

V o 

I + i$ 

i 

i 

v d 

i o 

$i o 

I o 

INPUT 

V + v$ 

I 

i 

L i o 

v d C R v o 

o 

Load 

v c $v c 

V c 

Z f 

Z i 

v c 

v ref 

CLOCK RAMP 

29/107 

Small-Signal Modeling of a Switching Power Converter 

i = I + iˆ 

i 

I 

i 

power stage 

L 

i = I + iˆ 

v = V + v$ 

o 

O 

o 

o O o 

vi = VI +$ vi 

C 

open 

Z 

= + $ f 

d D d 

v c 

R L 

v o 

Z i 

$v i 

îo 

$d 

Averaged 

Power Stage 

The concerned transfer functions under 

small perturbations can be measured 

under an open loop condition. 

$v o 

v ref 

duty cycle 

modulator 

error processor 

30/107 





15



Definition of 

∧ 

d 

power switch gating waveform 

vo( t) 

io( t) 

v t i( ) 

vˆ 

, iˆ 

, vˆ 

o 

small signal perturbation 

o 

i 

V , I , V 

O O I 

t 

t on 

T 

d(t) 

D 

dt () 

t 

D = 

on 

T 

t 

dˆ 

x 

= 

T 

V , I , V 

O 

O 

I 

t 

t x 

t 

31/107 

Small-Signal Modeling of Voltage-Mode DC-DC 

Converters 

$v i 

$i o 

$ d 

Buck 

Boost 

Buck/Boost 

Power Stage 

$v o 

Pulse 

Modulator 

$v c 

Error 

Processor 

$v r 

32/107 





16



Modeling of Single-Loop DC-DC Converters 

$v i v 

$i $ 

o 

$d 

$ ; $ $ ; $ o 

vo 

vo 

v i d$ 

i o 

$v o 

$v i 

$i o 

$ d 

$v c 

$v o 

G v 

K PWM 

34/107 

v$ = f( v$ , i$ , d $ ) 

o i o 

Z p 

G d 

-A(s) 

K PWM 

$v c 

A(s) 

33/107 

Small Signal Transfer Functions 

v$ 

Gv 

() s = 

v 

Z 

G 

k 

p 

d 

v$ 

= 

i 

v $ 

o 

= 

d 

PWM 

o 

$ 

i d $ = 0,$ 

i o = 0 

o 

$ 

o d $ = 0, v$ 

i = 0 

$ 

v $ i= 0 , i$ 

o= 

0 

dˆ 

= 

ˆ 

v c 

: Open-loop input-to-output 

: Open-loop output impedance 

: Control to output transfer function 

: PWM modulator gain 

KPWM = 1 

V p 

: PWM dc gain 

v$ 

As () = 

v$ 

c 

o 

: Compensator gain 





17



Modeling of PWM DC-DC Converters 

• A dc-to-dc switching regulator incorporating a three-port duty ratio 

programmed modulator-power-stage subsystem whose transfer functions are 

defined in terms of ratios of small-signal ac quantities (hats) superimposed 

upon large-signal dc quantities (capitals). 

• The spectrum of the output signal contains the switching frequency, the 

control frequency, their respective harmonics, and sidebands. 

• The modeling objective is to find, as function of frequency, the loop gain and 

the closed properties of the regulator. 

• The essential prerequisite is to find the transfer function of the three-port 

subsystem of the modulator-power-stage. 

35/107 

Concerned Transfer Functions 

• Control-to-output transfer function 

• Line-to-output transfer function (audio susceptibility) 

• Reference-to-output transfer function 

• Input impedance 

• Output impedance 

A voltage sourcing power supply should have a low (zero) output 

impedance, while a current sourcing power supply should have a high 

(infinite) output impedance. 

36/107 





18



Closed-Loop Transfer Functions 

$v i v 

$i $ 

o 

$d 

$ ; $ $ ; $ o 

vo 

vo 

v i d$ 

i o 

$v o 

$v i 

$i o 

$ d 

$v c 

$v o 

G v 

K PWM 

38/107 

v$ = f( v$ , i$ , d $ ) 

o i o 

Z p 

G d 

-A(s) 

K PWM 

$v c 

A(s) 

G v,CL (Closed-loop Audio Susceptibility) 

v$ = G v$ + G d$ 

o v i d 

d$ =−AK PWM v$ 

o 

v$ 

v$ 

o 

i 

Gv 

Gv 

= = 1+ GK A 1+ 

T 

d 

PWM 

Z p,CL (Closed-loop Output Impedance) 

v$ = Z i$ + G d$ 

o p o d 

d$ =−AK v$ 

PWM o 

$v 

i 

o 

o 

Zp 

= 1+ 

T 

Loop Gain: T = A( s) 

K 

PWM 

G d 

37/107 


State-Space Averaging Technique 








19



State-Space Averaging Techniques 

• State Space Averaging Modeling 

• Static Analysis 

• Small-Signal Model at CCM 

• Small-Signal Model at DCM 

• Frequency Response Analysis 

39/107 

Concept of Time Averaging (Low Frequency Response 

Behavior) 

v o 

$v o 

V o 

Ii 

+ i $ i 

v d io 

$ 

i o 

L 

I o 

V 

I 

+ v$ 

i 

i o 

v d C R L 

v o 

v c $v c 

V c 

Z f 

Z i 

v c 

v ref 

CLOCK RAMP 

40/107 





20



Linear Approximation of State Space Trajectories 

x( t) 

x( ) 

&x= A1⋅ x+ B1⋅u 

dT s 

x ( ) 

&x = A ⋅ x+ B ⋅ u 

2 2 

T s 

x( 0) 

&x = A⋅ x+ B⋅ 

u 

t 

dT s 

( 1 − d ) T s 

( T on 

) 

( ) 

T off 

41/107 

State-Space Averaging Method (CCM) 

During 

During 

T 

T 

ON 

OFF 

⎧x& 

= A 

1x 

+ B 

1u 

⎨ 

⎩y 

= C 

1x 

+ E1u 

⎧x& 

= A 

2x 

+ B 

2u 

⎨ 

⎩ y = C 

2x 

+ E 

2u 

When the circuit time constant is far greater than the switching period, the 

above equations can be averaged as: 

Switch-ON Period 

Switch-OFF Period 

&x = A x + B u 

1 1 

y = C x+ 

E u 

1 1 

x d 1 

+ 

&x = A x+ 

B u 

2 2 

y= C x+ 

E u 

2 2 

x d 2 

averaging by using state duty ratio weighting 

42/107 





21



State-Space Averaging Method 

x& = ( A d + A d ) x+ ( B d + B d ) u 

1 1 2 2 1 1 2 2 

y= ( C d + C d ) x+ ( E d + E d ) u 

1 1 2 2 1 1 2 2 

x = Ax + Bu 

y = Cx + Du 

where 

A = A d + A d 

1 1 2 2 

B = B d + B d 

1 1 2 2 

C = C d + C d 

1 1 2 2 

E = E d + E d 

1 1 2 2 

43/107 

State Averaging by Active Duty Ratios 

During 

During 

T 

T 

ON 

OFF 

⎧x& 

= A 

1x 

+ B 

1u 

⎨ 

⎩y 

= C 

1x 

+ E 

1u 

⎧x& 

= A 

2x 

+ B 

2u 

⎨ 

⎩ y = C 

2x 

+ E 

2u 

When the circuit time constant is far greater than the switching 

period, the above equations can be averaged as: 

x& = ( A d + A d ) x + ( B d + B d ) u 

1 1 2 2 1 1 2 2 

y = ( C d + C d ) x + ( E d + E d ) u 

1 1 2 2 1 1 2 2 


&x = A x + B u 

1 1 

y = C x + E u 

1 1 


d 2 

&x = A x + B u 

2 2 

y = C x+ 

E u 

2 2 

x = Ax + Bu 

y = Cx + Du 

where 

A = A d + A d 

1 1 2 2 

B = B d + B d 

1 1 2 2 

C = C d + C d 

1 1 2 2 

E = E d + E d 

1 1 2 2 

d 1 

state averaging by using duty ratio weighting 

44/107 





22



Small-Signal Perturbation at a DC Operating Point 

Substitute x = X + x$ ; y = Y + y$ ; u = U + u$ ; 

d = D + d$ ; d = D − d$ 

1 1 2 2 

d 

( X+ x $) = A ( D d$ ) ( D d$ )( $) ( D d$ ) ( D d$ 1 1 + + A 

2 2 − X+ x + B 

1 1 + + B 

2 2 − )( U+ 

u$) 

dt 

} 

terms = 0 

d 

X + 

dt 

dc 

d 

dt 

6444444dc 

terms 

74= 

0 

444448 

xˆ 

= ( A D + A D ) X + ( B D + B D ) U + 

1 

1 

[( 

A − A ) X + ( B − B ) U] 

1 

1 

( A D 

1 

+ A 

2 

2 

2 

2 

D ) xˆ 

+ ( B D 

2 

( A 

141 

− A 

444 

2 

) dˆˆ 

x + ( B 

24444 

1 

− B 

2 

) dˆˆ 

u 

3 

1 

ignore nonlinear term 

1 

1 

2 

1 

1 

+ B 

2 

2 

dˆ 

+ 

2 

2 

D ) uˆ 

+ 

Note: 

The nonlinear dynamic system is linearized around a selected operating point! 

i 

45/107 

DC Model and AC Model 

DC Model 

X 

= −A −1 BU 

−1 

Y = ( − CA B+ 

E)U 

AC Model 

d 

x$ = Ax$ + Bu$ + Fd$ 

dt 

y$ = Cx$ + Eu$ + Gd$ 

where 

A = A D + A D 

1 1 2 2 

B = B D + B D 

1 1 2 2 

C= C D + C D 

1 1 2 2 

E = E D + E D 

1 1 2 2 

F = ( A − A ) X+ ( B −B ) U 

1 2 1 2 

G = ( C − C ) X+ ( E −E ) U 

1 2 1 2 

46/107 





23



Transfer Function Matrix 

x( 

s) 

= ( sI 

− A) 

−1 

= H ( s) 

u( 

s) 

+ 

u 

H d 

−1 

H ( s) = ( sI−A) 

B 

u 

Bu( 

s) 

+ ( sI 

− A) 

( s) 

d( 

s) 

−1 

H ( s) = ( sI−A) Fd( s) 

d 

−1 

Fd( 

s) 

−1 −1 

y() s = [ C( sI− A) B+ E]() u s + [ C( sI− A) F+ 

G]() 

d s 

= G ()() s u s + G ()() s d s 

u 

−1 

Gu() s = C( sI− A) 

B+ 

E 

−1 

Gd () s = C( sI− A) 

F+ 

G 

d 

⎡vo( 

s) 

⎤ ⎡G 

⎢ = 

ii 

( s) 

⎥ ⎢ 

⎣ ⎦ ⎣G 

u11 

u21 

( s) 

( s) 

G 

G 

u12 

u22 

( s) 

⎤⎡vi 

( s) 

⎤ ⎡G 

( s) 

⎥⎢ 

id 

( s) 

⎥ + ⎢ 

⎦⎣ 

⎦ ⎣G 

d1 

d 2 

( s) 

⎤ 

d( 

s) 

( s) 

⎥ 

⎦ 

47/107 

Open Loop Transfer Functions 

• control-to-output (open-loop transfer function): 

vo() 

s 

−1 

= Gd 

1() s = Gd() s = C( sI− A) 

F+ 

G 

1 

ds () 

• line-to-output (audio susceptibility): 

vo() 

s 

−1 

= Gu 

11() s = Gu() s = C( sI− A) 

B+ 

E 

11 

v () s 

i 

• output impedance: 

vo() 

s 

= Gu 

() s = 

u() s = ( s − ) 

− 1 

12 

G C I A B+ 

E 

12 

i () s 

d 

1 

11 

12 

48/107 





24



Example: Buck Converter 

Step 1. Draw the linear equivalent circuit for each switching state of the converter. 

Q L i L 

i o 

x 1 

x 2 

r L 

R v o 

i d 

y i 2 i c i R 

r 

u c 

1 v i D 

u 2 

C v c y 1 

Q closed, D open 

D closed, Q open 

L 

r L 

i L 

i o 

i d 

L 

i L 

i o 

i d 

i i 

i c 

i R 

i c 

r L 

R v o 

i R 

i i 

50/107 

v i R v o 

r c 

r c 

C 

v c 

C 

v c 

49/107 

Select State Variables 

Select the inductor current i L and capacitor voltage v L state variables. 

⎡x1 

⎤ ⎡ ⎤ 

⎥ = iL 

x= 

⎢ ⎢ ⎥ 

⎣x2 

⎦ ⎣v 

c⎦ 

Select the input dc voltage and output disturbance current as input variables. 

⎡u1 

⎤ ⎡ ⎤ 

⎥ = vi 

u= 

⎢ ⎢ ⎥ 

⎣u 

2⎦ 

⎣i 

d⎦ 

Select the output voltage and input current as output variables. 

⎡y1 

⎤ ⎡ ⎤ 

= ⎢ ⎥ = vo 

y ⎢ ⎥ 

⎣y2 

⎦ ⎣i 

⎦ 





25



Derive Circuit Equations: State Equations 

Step 2. Write the circuit equations for each equivalent circuit in a state-variable format. 

r L 

i L 

i o 

i d 

Q-ON and D-OFF State: 

i i 

L 

r c 

i c 

i R 

v i 

R 

v o 

C 

v c 

 

 

v L di ir rC dv 

L 

c 

i 

= + 

LL+ C 

+ v 

dt dt 

dvc 

rC 

C + vC 

= ( iL 

−iC 

−id 

) R 

dt 

dvc 

= ( iL 

−C 

+ id 

) R 

dt 

dvc 

= iLR− 

RC + idR 

dt 

C 

dvc 

( R+ rC 

) C = iLR−vC 

−idR 

dt 

dvc 

R 1 R 

= iL 

− vC 

− id 

dt ( R+ 

r ) C ( R+ 

r ) C ( R+ 

r ) C 

C 

C 

C 

51/107 

State-Space Average Modeling: State Equations 

 

R 1 R 

Replace C dv in with iL 

− vC 

− i 

dtc 

d 

( R+ 

r ) ( R+ 

r ) ( R+ 

r ) 

C 

C 

C 

We can obtain: 

di 

= + 

⎛ 

+ ⎜ 

⎝ 

R 

L 

v 

i 

L iLrL 

rC 

iL 

vC 

id 

vC 

dt ⎜ 

+ 

( R+ 

rC 

) ( R+ 

rC 

) ( R+ 

rC 

) 

− 

1 

− 

R 

⎞ 

⎟ ⎠ 

diL 

RrC 

rC 

RrC 

L = vi 

−iLr 

L 

− iL 

+ vC 

− id 

−v 

dt ( R+ 

r ) ( R+ 

r ) ( R+ 

r ) 

C 

⎛ Rr ⎞ ⎛ 

C 

=− 

⎜ + rL 

iL 

− 

R r 

⎟ 

⎜ 

⎝ + 

C ⎠ ⎝ 

C 

R ⎞ Rr 

vC 

vi 

R r 

⎟ + − 

+ 

C ⎠ R+ 

C 

i 

C 

d 

rC 

C 

diL 

1 ⎛ Rr ⎞ 

C 1 ⎛ R ⎞ 1 1 ⎛ Rr ⎞ 

C 

= − rL 

iL 

vC 

vi 

id 

dt L 

⎜ + 

R r 

⎟ − 

+ − 

C 

L 

⎜ 

R r 

⎟ 

C 

L L 

⎜ 

R r 

⎟ 

⎝ + ⎠ ⎝ + ⎠ ⎝ + 

C ⎠ 

52/107 





26




 

 

i = i 

i 

o 

L 

L 

v = ( i −i 

−i 

) R 

L 

C 

= i R−i 

R−i 

R 

C 

C 

d 

d 

⎛ R 1 R ⎞ 

= iLR− 

RC 

⎜ iL 

− vC 

− id 

idR 

( R rC 

) C ( R rC 

) C ( R rC 

) C 

⎟− 

⎝ + + + ⎠ 

RrC 

R RrC 

= iL 

+ vC 

− id 

( R+ 

r ) ( R+ 

r ) ( R+ 

r ) 

C 

C 

RrC 

R RrC 

vo 

= iL 

+ vC 

− id 

( R+ 

r ) ( R+ 

r ) ( R+ 

r ) 

C 

C 

C 

⎡ 1 ⎛ Rr ⎞ ⎛ ⎞⎤ 

⎡ 

C 

1 R 1 

⎢− 

⎜ + r 

⎟ 

L 

− 

⎜ 

⎟⎥ 

⎢ 

⎡i& 

L 

⎤ 

⎢ L⎝ 

R+ 

rC 

⎠ L⎝R+ 

r ⎠⎥⎡i 

C L ⎤ ⎢ 

⎥⎢ 

⎥ + L 

⎢ ⎥ = 

⎣v& 

⎢ ⎛ ⎞ ⎛ ⎞ ⎣ ⎦ ⎢ 

C⎦ 

1 R 1 1 vC 

⎢ 

⎜ 

⎟ − 

⎜ 

⎟⎥ 

⎢0 

⎣ C⎝ 

R+ 

rC 

⎠ C⎝ 

R+ 

rC 

⎠⎦ 

⎣ 

⎡ RrC 

R ⎤ ⎡ RrC 

⎤ 

⎡vo 

⎤ 

⎢ 

⎥ 

⎡ ⎤ 

⎢ 

− 

⎥ 

⎡ ⎤ 

⎢ ⎥ = 

iL 

+ + ⎢ ⎥ + 0 vi 

R rC 

R rC 

R+ 

rC 

⎢ 

⎥ ⎢ ⎥ 

⎢ ⎥ 

⎣i 

⎦ 

⎣vC 

⎦ 

⎣id 

⎦ 

⎣ 1 0 ⎦ ⎣0 

0 ⎦ 

1 ⎛ Rr ⎞⎤ 

C 

− 

⎜ 

⎟⎥ 

L⎝ 

R+ 

r ⎠⎥⎡v 

C i⎤ 

⎛ ⎞⎥ 

⎢ ⎥ 

1 R 

− 

⎣id 

⎦ 

⎜ 

⎟⎥ 

C ⎝ R+ 

rC 

⎠⎦ 

Q-OFF and D-ON 

State Equation 

53/107 


r L 

i L 

i o 

i d 

Q-OFF and D-ON State: 

i i 

L 

r c 

C 

i c 

v c 

R 

i R 

v o 

 

 

0= L di + ir + rC dv 

L 

c 

LL C 

+ v 

dt dt 

dvc 

rC 

C + vC 

= ( iL 

−iC 

−id 

) R 

dt 

dvc 

= ( iL 

−C 

−id 

) R 

dt 

dvc 

= iLR−RC 

−idR 

dt 

C 

dvc 

( R+ rC 


−idR 

dt 

dvc 

R 1 R 

= iL 

− vC 

− i 

dt ( R+ 

r ) C ( R+ 

r ) C ( R+ 

r ) C 

C 

C 

C 

d 

54/107 





27




dvc 

( R+ rC 


−idR 

dt 

dvc 

R 1 R 

= iL 

− vC 

− id 

dt ( R+ 

r ) C ( R+ 

r ) C ( R+ 

r ) C 

C 

C 

C 

R 1 R 

Replace C dv c 

in with iL 

− vC 

− id 

dt 

( R+ 

r ) ( R+ 

r ) ( R+ 

r ) 

We can obtain: 

 

di 

0= 

+ 

C 

⎛ 

+ ⎜ 

⎝ 

R 

C 

− 

L 

L iLrL 

rC 

iL 

vC 

id 

vC 

dt ⎜ 

+ 

( R+ 

rC 

) ( R+ 

rC 

) ( R+ 

rC 

) 

1 

C 

− 

R 

⎞ 

⎟ ⎠ 

diL 

RrC 

rC 

RrC 

L =−i 

LrL 

− iL 

+ vC 

− id 

−v 

dt ( R+ 

r ) ( R+ 

r ) ( R+ 

r ) 

C 

⎛ Rr ⎞ ⎛ 

C 

R ⎞ Rr 

=− 

⎜ + rL 

iL 

vC 

− 

R r 

⎟ − 

⎜ 

C 

R r 

⎟ 

⎝ + ⎠ ⎝ + 

C ⎠ R+ 

C 

C 

i 

C 

d 

rC 

C 

diL 

1 ⎛ Rr ⎞ 

C 

1 ⎛ R ⎞ 1 ⎛ Rr ⎞ 

C 

=− rL 

iL 

v 

i 

Ci 

d 

dt L 

⎜ + 

R r 

⎟ − 

− 

C 

L 

⎜ 

R r 

⎟ 

C 

L 

⎜ 

R r 

⎟ 

⎝ + ⎠ ⎝ + ⎠ ⎝ + 

C ⎠ 

55/107 


 

 

i i = 0 

v = ( i − i − i ) R 

o 

L 

L 

C 

= i R − i R − i R 

C 

C 

d 

d 

⎛ R 1 

= iLR 

− RC 

⎜ iL 

− v 

⎝ ( R + rC 

) C ( R + rC 

) C 

RrC 

R RrC 

= iL 

+ vC 

− id 

( R + r ) ( R + r ) ( R + r ) 

C 

C 

C 

R ⎞ 

− id 

− id 

R 

( R rC 

) C 

⎟ 

+ ⎠ 

RrC 

R RrC 

vo 

= iL 

+ vC 

− id 

( R+ 

r ) ( R+ 

r ) ( R+ 

r ) 

C 

C 

C 

⎡ 1 ⎛ Rr ⎞ ⎛ ⎞⎤ 

⎡ 

C 

1 R 

⎢− 

⎜ + rL 

⎟ − 

⎜ 

⎟⎥ 

⎢0 

⎡i& 

L 

⎤ 

⎢ ⎝ + ⎠ ⎝ + ⎠⎥⎡ 

⎤ ⎢ 

⎥ = L R rC 

L R r i 

C L 

⎢ 

⎢ 

⎥⎢ 

⎥ + 

⎣v& 

⎛ ⎞ ⎛ ⎞ ⎣ ⎦ ⎢ 

C⎦ 

1 R 1 1 vC 

⎢ 

⎜ 

⎟ − 

⎜ 

⎟⎥ 

⎢0 

⎣ C ⎝ R+ 

rC 

⎠ C ⎝ R+ 

rC 

⎠⎦ 

⎣ 

⎡ RrC 

R ⎤ ⎡ RrC 

⎤ 

⎡vo 

⎤ 

⎢ 

⎥ 

⎡ ⎤ 

⎢ 

− 

⎥ 

⎡ ⎤ 

⎢ ⎥ = 

iL 

+ + ⎢ ⎥ + 0 vi 

R rC 

R rC 

R + rC 

⎢ 

⎥ ⎢ ⎥ 

⎢ ⎥ 

⎣ii 

⎦ 

⎣vC 

⎦ 

⎣id 

⎦ 

⎣ 0 0 ⎦ ⎣0 

0 ⎦ 

1 ⎛ Rr ⎞⎤ 

C 

− 

⎜ 

⎟⎥ 

L ⎝ R+ 

r ⎠⎥⎡v 

C i⎤ 

⎛ ⎞⎥⎢ 

⎥ 

1 R 

− 

⎣id 

⎦ 

⎜ 

⎟⎥ 

C ⎝ R + rC 

⎠⎦ 

Q-ON and D-OFF 

State Equation 

56/107 





28




Q Conducted: 

⎡ 1 ⎛ Rr ⎞ ⎛ ⎞⎤ 

⎡ 

C 

1 R 1 

⎢− 

⎜ + r 

⎟ 

⎜ 

⎟ 

L 

− ⎥ ⎢ 

⎡i& 

L 

⎤ 

⎢ 

L⎝ 

R+ 

rC 

⎠ L⎝ 

R+ 

r ⎠⎥⎡i 

C L ⎤ ⎢ 

⎢ 

⎥⎢ 

⎥ 

⎣ ⎦ 

+ L 

⎢ ⎥ = 

⎣v& 

⎛ ⎞ ⎛ ⎞ ⎢ 

C⎦ 

1 R 1 1 vC 

⎢ 

⎜ 

⎟ − 

⎜ 

⎟⎥ 

⎢0 

⎣ C ⎝ R+ 

rC 

⎠ C ⎝ R+ 

rC 

⎠⎦ 

⎣ 

⎡ RrC 

R ⎤ ⎡ RrC 

⎤ 

⎡vo 

⎤ 

⎢ 

⎥ 

⎡ ⎤ 

⎢ 

− 

⎥ 

⎡ ⎤ 

⎢ ⎥ = 

iL 

+ + ⎢ ⎥ + 0 vi 

R rC 

R rC 

R+ 

rC 

⎢ 

⎥ ⎢ ⎥ 

⎢ ⎥ 

⎣ii 

⎦ 

⎣vC 

⎦ 

⎣id 

⎦ 

⎣ 1 0 ⎦ ⎣0 

0 ⎦ 

1 ⎛ Rr ⎞⎤ 

C 

− 

⎜ 

⎟⎥ 

L⎝ 

R+ 

r ⎠⎥⎡v 

C i⎤ 

1 ⎛ R ⎞⎥⎢ 

⎥ 

− 

⎣id 

⎦ 

⎜ 

⎟⎥ 

C ⎝ R+ 

rC 

⎠⎦ 

D Conducted: 

⎡ 1 ⎛ Rr ⎞ ⎛ ⎞⎤ 

⎡ 

C 

1 R 

⎢− 

⎜ + rL 

⎟ − 

⎜ 

⎟⎥ 

⎢0 

⎡i& 

L 

⎤ 

⎢ ⎝ + ⎠ ⎝ + ⎠⎥⎡ 

⎤ ⎢ 

⎥ = L R rC 

L R r i 

C L 

⎢ 

⎢ 

⎥⎢ 

⎥ + 

⎣v& 

⎞ ⎣ ⎦ ⎢ 

C⎦ 

1 ⎛ R ⎞ 1 ⎛ 1 vC 

⎢ 

⎜ 

⎟ − 

⎜ 

⎟⎥ 

⎢0 

⎣ C ⎝ R+ 

rC 

⎠ C ⎝ R+ 

rC 

⎠⎦ 

⎣ 

⎡ RrC 

R ⎤ ⎡ RrC 

⎤ 

⎡vo 

⎤ 

⎢ 

⎥ 

⎡ ⎤ 

⎢ 

− 

⎥ 

⎡ ⎤ 

⎢ ⎥ = 

iL 

+ + ⎢ ⎥ + 0 vi 

R rC 

R rC 

R+ 

rC 

⎢ 

⎥ ⎢ ⎥ 

⎢ ⎥ 

⎣i 

⎦ 

⎣vC 

⎦ 

⎣id 

⎦ 

⎣ 0 0 ⎦ ⎣0 

0 ⎦ 

1 ⎛ Rr ⎞⎤ 

C 

− 

⎜ 

⎟⎥ 

L⎝ 

R+ 

r ⎠⎥⎡v 

C i⎤ 

⎛ ⎞⎥⎢ 

⎥ 

1 R 

− 

⎣id 

⎦ 

⎜ 

⎟⎥ 

C ⎝ R+ 

rC 

⎠⎦ 

57/107 


Q Conducted: 

⎡ 1 ⎛ Rr ⎞ 

C 

⎢− 

⎜ + rL 

⎟ 

⎢ L ⎝ R + rC 

A 

⎠ 

1 

= 

⎢ 1 ⎛ R ⎞ 

⎢ 

⎜ 

⎟ 

⎣ C ⎝ R + rC 

⎠ 

⎡ RrC 

R ⎤ 

C = ⎢ + + ⎥ 

1 R r , 

C 

R rC 

⎢ 

⎥ 

⎣ 1 0 ⎦ 

1 ⎛ R ⎞⎤ 

⎡1 

1 ⎛ Rr ⎞⎤ 

C 

− ⎜ ⎟⎥ 

⎢ − ⎜ ⎟⎥ 

L ⎝ R + rC 

⎠⎥ 

⎢ L L ⎝ R + rC 

, B = 

⎠⎥ 

1 

1 ⎛ 1 ⎞⎥ 

⎢ 1 ⎛ R ⎞⎥ 

− 

⎜ 

⎟⎥ 

⎢ 0 − 

⎜ 

⎟⎥ 

C ⎝ R + rC 

⎠⎦ 

⎣ C ⎝ R + rC 

⎠⎦ 

⎡ RrC 

⎤ 

⎢ 

0 − 

E = + ⎥ 

1 R rC 

⎢ ⎥ 

⎣0 

0 ⎦ 

D Conducted: 

⎡ 1 ⎛ Rr ⎞ 

C 

⎢− 

⎜ + rL 

⎟ 

⎢ L ⎝ R + rC 

A 

⎠ 

2 

= 

⎢ 1 ⎛ R ⎞ 

⎢ 

⎜ 

⎟ 

⎣ C ⎝ R + rC 

⎠ 

⎡ RrC 

R ⎤ 

C = ⎢ + + ⎥ 

2 R r , 

C 

R rC 

⎢ 

⎥ 

⎣ 0 0 ⎦ 

1 ⎛ R ⎞⎤ 

⎡ 1 ⎛ Rr ⎞⎤ 

C 

− ⎜ ⎟⎥ 

⎢0 

− ⎜ ⎟⎥ 

L ⎝ R + rC 

⎠⎥ 

⎢ L ⎝ R + rC 

, B = 

⎠⎥ 

2 

1 ⎛ 1 ⎞⎥ 

⎢ 1 ⎛ R ⎞⎥ 

− 

⎜ 

⎟⎥ 

⎢0 

− 

⎜ 

⎟⎥ 

C ⎝ R + rC 

⎠⎦ 

⎣ C ⎝ R + rC 

⎠⎦ 

⎡ RrC 

⎤ 

⎢ 

0 − 

E = + ⎥ 

2 R rC 

⎢ ⎥ 

⎣0 

0 ⎦ 

58/107 





29



State-Space Average Modeling: Averaging 

Step 3. Average each state by using duty ratio as a weighting factor and then combine the 

two sets of equations into a single set. 

Q : &x = A 

1x + B 

1u 

D : &x = A 

2x + B 

2u 

x d 

y = C x + E u 1 + y = C x + E u 

1 1 

2 2 

x d 2 


x& = ( A d + A d ) x + ( B d + B d ) u 

1 1 2 2 1 1 2 2 

y = ( C d + C d ) x + ( E d + E d ) u 

1 1 2 2 1 1 2 2 

&x = Ax + Bu 

y = Cx + Eu 

where 

A = A d + A d 

1 1 2 2 

B = B d + B d 

1 1 2 2 

C = C d + C d 

1 1 2 2 

E = E d + E d 

1 1 2 2 

59/107 

State-Space Average Modeling: Perturbation 

Step 4. Perturb the averaged equation set to produce DC and small signal terms and eliminate 

nonlinear product terms. 

Substitute x= X+ x$ ; y = Y+ y$ ; u= U+ 

u$ ; 

d = + $ ; = − $ 

1 

D1 d d2 D2 

d 

into the averaged equations (in Steps 3) x& = ( A1d1+ A2d2) x + ( B1d1+ 

B2d2) 

u 

y= ( Cd + C d ) x+ ( Ed + E d ) u 

d 

dt 

1 1 2 2 1 1 2 2 

( X + xˆ ) = ( A ( D + dˆ) 

+ A ( D 

− dˆ))( 

X + xˆ ) + 

( B1( 

D1 

+ dˆ) 

+ B 2( 

D2 

− dˆ))( 

U + uˆ ) 

= A X A ˆ 

1D1 

+ 

1dX 

+ A1D1xˆ 

+ A1dˆˆ 

x + 

A X A ˆ 

2D2 

− 

2dX 

+ A 

2D2xˆ 

− A 

2d 

ˆˆ x + 

B U B ˆ 

1D1 

+ 

1dU 

+ B1D1uˆ 

+ B1dˆˆ 

u + 

B D U − B dˆ 

U + B D uˆ 

− B dˆˆ 

u 

2 

1 

2 

1 

2 

2 

2 

2 

2 

2 

60/107 





30



State-Space Average Modeling: Perturbation 

Perturbation of the State Equations 

Operating Point 

x 1 

New Coordinates 

d 

( X+ x$ ) = ( A1D1 + A2D2) X+ ( B1D1 + B2D2) 

U + 

dt 

( A D A D ) x$ 1 1 

+ 

2 2 

+ ( B1D1 + B2D2)$ 

u+ 

( A − A ) X+ ( B − B ) U d$ 

+ 

1 2 1 2 

( A − A ) d $ x$ + ( B −B ) d $ u$ 

1 2 1 2 

x 1 

Y + y$ = ( C ( D + d$ ) + C ( D − d$ ))( X+ x $ ) + 

1 1 2 2 

( E ( D + d$ ) + E ( D − d$ ))( U + u $ ) 

1 1 2 2 

= ( C D + C D ) X+ ( E D + E D ) U + 

1 1 2 2 1 1 2 2 

( C D + C D )$ x+ ( C − C ) X + ( E − E ) U d$ 

+ 

1 1 2 2 1 2 1 2 

( E D + E D )$ u+ ( C − C )$ xd $ + ( E −E ) d $ u$ 

1 1 2 2 1 2 1 2 

ˆx 2 

ˆx 1 

61/107 

State-Space Average Modeling: DC Analysis 

DC Analysis: 

Set all variational terms to zero, we can obtain 

0 = 

1D1+ 2D2 + 

1D1+ 

2D2 

X 

( A A ) X ( B B ) U 

= AX+ 

BU 

Y= ( CD + C D ) X+ ( ED + E D ) U 

= CX+ 

EU 

Therefore 

=− −1 

1 1 2 2 1 1 2 2 

A BU 

−1 

Y =− ( CA B+ 

E)U 

62/107 





31



State-Space Average Modeling: DC Model 

Eliminate the DC term d X = 0 AX + BU = 0 and Y CX EU 

dt = + 

We obtain the dc model equation: 

D. 

C. 

⎧ 

⎛ R ⎞ 

⎪ 0 = [ − r ] 

⎜ 

⎟ 

L 

+ ( R // rC 

) I 

L 

− V 

⎪ 

⎝ R + rC 

⎠ 

⎪ ⎛ R ⎞ ⎛ 1 ⎞ 

⎪ 0 = 

⎜ 

⎟I 

L 

− 

⎜ 

⎟V 

C 

⎨ ⎝ R + rC 

⎠ ⎝ R + rC 

⎠ 

⎪ 

⎪ 

⎛ R ⎞ 

Vo 

= ( R // rC 

) I 

L 

− ⎜ ⎟VC 

⎪ 

⎝ R + rC 

⎠ 

⎪ 

⎩I 

S 

= DI 

L 

C 

+ V D 

i 

Comments: 

1. DC model gives DC information (steady-state behavior). 

2. DC model can be used for loss estimation. 

63/107 

State-Space Average Modeling: AC Model 

Neglect the nonlinear product term d $ ⋅ x$ and d$ ⋅ u$ 

We obtain the ac model (small-signal) equation: 

d 

x$ = A x$ + Bu$ + Fd$ 

dt 

y$ = Cx$ + Eu$ + Gd$ 

where 

A = A1D1 + A2D2 

B = B1D1 + B2D2 

C = C1D1 + C2D2 

E = E1D1 + E2D2 

F = ( A1 − A2) X + ( B1 − B2) 

U 

G = ( C − C ) X + ( E −E ) U 

1 2 1 2 

⎧ diˆ 

⎛ ⎞ 

L ⎛ rL 

+ R// 

rC 

⎪ 

⎟ 

⎞ R 

= −⎜ 

iˆ 

1 

+ 

⎜ 

⎟vˆ 

L 

⎪ dt ⎝ L ⎠ L⎝ 

R+ 

rC 

⎠ 

⎪ 

⎛ ⎞ ⎛ ⎞ 

⎪ 

dvˆ 

C 

1 R 

= − 

⎜ 

⎟iˆ 

1 1 

L 

− 

⎜ 

⎟vˆ 

C 

AC . . ⎨ dt C⎝ 

R+ 

rC 

⎠ L⎝ 

R+ 

rC 

⎠ 

⎪ 

⎪ 

⎛ R ⎞ 

vˆ 

= R r i + 

⎪ 

⎜ 

⎟ 

o 

( // 

C)ˆ 

L 

vˆ 

C 

⎝ R+ 

rC 

⎠ 

⎪ 

⎪⎩ 

iˆ 

s 

= Diˆ 

L 

+ ILdˆ 

C 

⎛ D⎞ 

⎛Vi 

⎞ 

+ ⎜ ⎟vˆ 

+ ⎜ ⎟dˆ 

i 

⎝ L ⎠ ⎝ L ⎠ 

Comments: 

1. AC model gives small signal information. 

2. AC model parameter value depends on dc operating point. 

64/107 





32



Time-to-Frequency Transform 

Step 5. Transform ac state-space model into frequency domain (Laplace transform, s-domain). 

d 

x$ = Ax$ + Bu$ + Fd$ 

dt 

y$ = Cx$ + Eu$ + Gd$ 

In the following, the hat above the variables will be neglected for simplicity. The small signal 

(or ac term) of a variable is denoted using lower case letter. Thus, the dynamic equation of a 

PWM dc-dc converter can be represented as: 

d 

x = Ax+ Bu+ 

Fd 

dt 

y= Cx+ Eu+ 

Gd 

65/107 

Time-to-Frequency Transform 

Take Laplace transform: 

sx( s) = Ax( s) + Bu( s) + Fd ( s) 

y() s = Cx() s + Eu() s + Gd() 

s 

−1 −1 

x() s = ( sI− A) Bu() s + ( sI− 

A) Fd() 

s 

= H ()() s u s + H ()() s d s 

u 

−1 

H () s = ( sI−A) 

B 

u 

−1 

H () s = ( sI−A) Fd() 

s 

d 

d 

−1 −1 

y() s = [ C( sI− A) B+ Eu ]() s + [ C( sI− A) F+ 

G]() 

d s 

= G ()() s u s + G ()() s d s 

u 

−1 

G () = C( sI− A) 

B+ 

E 

u 

s 

−1 

Gd() s = C( sI− A) 

F+ 

G 

d 

G ( s) 

= C( 

sI 

− A) 

u 

−1 

⎡Gu 

B+ 

E = ⎢ 

⎣Gu 

11 

21 

( s) 

( s) 

G 

G 

u12 

u22 

( s) 

⎤ 

( s) 

⎥ 

⎦ 

66/107 





33



State-Space Average Modeling: Transfer Functions 

Interpretation of the transfer function matrix 

Input-to-output voltage gain 

(audio susceptibility) 

⎡vo⎤ 

⎡G 

⎢ 

i 

⎥ = ⎢ 

⎣ i ⎦ ⎣G 

u11 

u21 

( s) 

( s) 

G 

G 

u12 

u22 

Output impedance 

( s) 

⎤⎡vi⎤ 

⎡G 

( s) 

⎥⎢ 

i 

⎥ + ⎢ 

⎦⎣ 

d ⎦ ⎣G 

d1 

d 2 

( s) 

⎤ 

d 

( s) 

⎥ 

⎦ 

Control-to-output 

voltage gain 

Input Admittance 

Load-to-line current gain 

Control-to-input 

current gain 

67/107 

State-Space Average Modeling: Transfer Functions 

Disturbances 

Results 

$v i 

K PWM 

A(s) 

$i o 

$ d 

iˆ 

i 

vˆ 

i 

v$ 

$ ; $ o 

v 

v i$ 

i 

i 

i 

; 

ˆ 

iˆ 

o 

o 

o 

i 

i 

; 

ˆ 

dˆ 

v 

; $ o 

d$ 

î i 

$v o 

Control action 

$v c 

Loop compensator 

68/107 





34



State-Space Averaging: Time-to-Frequency Transform 

⎡ 

⎤ 

⎢ 

⎥ 

vˆ 

o( 

s) 

⎢ 

1+ 

srC 

C 

= V 

⎥ 

i 

dˆ( 

s) 

⎢ ⎛ 

L ⎞ 

⎥ 

2 ⎛ R+ 

r ⎞ 

C 

⎢1+ 

s⎜rC 

C + [ R// 

rL 

] C + ⎟+ s LC⎜ 

⎟⎥ 

⎣ ⎝ 

R+ 

rL 

⎠ ⎝ R+ 

rC 

+ rL 

⎠⎦ 

⎡ 

⎤ 

⎢ 

⎥ 

vˆ 

o( 

s) 

⎢ 

1+ 

srC 

C 

= D 

⎥ 

vˆ 

⎢ ⎛ 

⎞ ⎛ + ⎞⎥ 

i( 

s) 

L 2 R rC 

⎢1+ 

s⎜rC 

C + [ R// 

rL 

] C + ⎟+ s LC⎜ 

⎟⎥ 

⎣ ⎝ 

R+ 

rL 

⎠ ⎝ R+ 

rC 

+ rL 

⎠⎦ 

vo() 

s 

Zo() 

s = = G 

i () s d 

d 

u12 

= 0 

vi 

= 0 

() s 

69/107 

State-Space Averaging: Time-to-Frequency Transform 

Note: In most conditions, because R >>(r L + r C ), the above equations can be approximated as 

⎡ 

⎤ 

vˆ 

⎢ 

⎥ 

o( 

s) 

1+ 

srC 

C 

= Vi 

⎢ 

⎥ 

dˆ( 

s) 

⎢ ⎛ L ⎞ 2 

1+ 

s⎜ 

+ ( r 

⎥ 

C 

+ rL 

) C⎟ + s LC 

⎢⎣ 

⎝ R ⎠ ⎥⎦ 

⎡ 

⎤ 

vˆ 

s ⎢ + sr C ⎥ 

o( 

) 

1 C 

= Vi 

⎢ 

⎥ 

dˆ( 

s) 

⎢ ⎛ L ⎞ 2 

1+ 

s⎜ 

+ ( r + r C ⎟ + s LC⎥ 

C L) 

⎢⎣ 

⎝ R ⎠ ⎥⎦ 

v$ o( s) 

1+ srC 

C 

= V 

ds $ 

i 2 

() Δs 

ω 

o 

⎡ 

⎤ 

vˆ 

⎢ 

⎥ 

o( 

s) 

1+ 

srC 

C 

= D⎢ 

⎥ 

vˆ 

⎢ ⎛ L 

i( 

s) 

⎞ 2 

1+ 

s⎜ 

+ ( r 

⎥ 

C 

+ rL 

) C⎟ + s LC 

⎢⎣ 

⎝ R ⎠ ⎥⎦ 

2 ωo 

2 

Δs 

= s + s + ωo 

Q 

1 

ωo 

= 

LC 

1 1 

Q = 

ω L 

o + ( rL 

+ rC 

) C 

R 

70/107 





35



State-Space Average Modeling 

v$ ( s) 

v$ o 

o 

( s) 

The small signal control-to-output $ , and line-to-output are transfer 

d 

functions of two poles and one zero ( s ) 

v$ i 

( s) 

( s + z1) 

K 

( s+ p )( s+ 

p ) 

1 2 

with its parameters depending upon component values and operating point. p 1 , p 2 can be 

complex poles or real poles. But p 1 , p 2 and z 1 all lie on LHP. 

Note: The equivalent series resistance of the capacitor will introduce a LHP zero. 

71/107 

State-Space Averaging: Output Impedance 

Output Impedance: Z s 

s s 

1 + + ( ) 

v$ o 

( s) 

ω1Q1 ω1 

= R 

i$ 2 

( s) 

Δs 

ω 

d 

o 

2 

o 

vo( s) 

−1 

() = = c( sI− A) 

B+ 

du 

i () s d = 0 

d 

u= 

0 

2 ω 

o 

Δs s 

Q s 2 

= + + ω 

o 

1 1 1 

ω 

o 

= , 

Q = 

LC 

ω L 

o + ( rL 

+ rC) 

C 

R 

1 rL 

1 1 

ω1 = ; Q1 

= 

LC r 

L 

C 

ω1 

+ rC 

L 

r 

C 

72/107 





36



Modeling of Load Impedance and Disturbances 

Z os 

PWM 

Modulator 

v g 

v o 

v R 

v~s 

V s 

Boost Converter Buck/Boost Converter Buck Converter 

R L 

~ 

id 

load 

Gate 

Drive 

Loop 

Compensator 

L 

r L 

i L 

i o 

i d 

Q 

i c 

i R 

v i 

D 

r c 

C 

v c 

R 

v o 

Modeling of Source Impedance and Disturbances 

Z os 

PWM 

Modulator 

v g 

v o 

v R 

v~s 

V s 

Boost Converter Buck/Boost Converter Buck Converter 

R L 

~ 

id 

load 

Gate 

Drive 

Loop 

Compensator 

L 

Protection 

F1 

Input EMI Filter 

Rectifier 

V o 

G 

N 

RV1 

F2 

C y 

C x 

T y 

T x 

C y 

C x 

PWM 

Isolation 

V SENSE 

R. D. Middlebrook, "Input Filter Considerations in Design and Application of Switching Regulators," IEEE Industry 

Applications Society Annual Meeting, 1976 Record, pp. 366-382. 





37



Dynamic Responses for Step Load Changes 

Adaptive voltage 

positioning offset 

V OFFSET (40mV) 

Nominal set 

point voltage 

V SET (2.0V) 

Dynamic voltage 

tolerance, V DYN- 

(100mV for 2μs) 

Initial voltage drop is 

mainly due to the product 

of the load current step 

and ESR of the capacitors. 

ΔV = ΔI × ESR. 

(ESL effects are ignored) 

Output voltage 

V OUT (50mV/Div) 

Steady state voltage at 

high current is 

approximately 

V SET + V OFFSET − I OUT × R SENSE 

Output current transient 

step, ΔI = 0 to 14A 

(5A/Div) 

L = .5μH; 

C OUT 

= 6× 

1500μF Sanyo MV - GX; R = 2.5mΩ 

2 

SENSE 

Intel: VRM (Voltage Regulator Module) and Enterprise Voltage Regulator-Down (EVRD) 11.0 

Design Guidelines, Nov. 2006. 

75/107 

Buck Converter with Load Current Disturbance 

Block Diagram Representation 

v i 

Q 

D 

L 

r L 

r c 

C 

i L 

i c 

v c 

i o 

R 

v o 

i d 

i R 

i d 

ΔI d 

i d 

i R 

1 

R 

ΔT 

Load Current Slew Rate 

t 

ΔI 

d 

ΔT 

Q 

1 i L i C 

rC + 1 

sL + r L 

sC 

v o 

v i D 

i o 





38



Control-to-Output Transfer Functions 

DC-DC Converters in CCM Operating Mode 

v i 

D 

L 

C 

v o 

• Buck 

v$ o() 

s 1+ 

rC 

Cs 

= V 

ds $ 

i 

( ) s 2 1 

( ) + 

Q s + 1 

ω ω 

o 

o 

1 

ωo 

= 

LC 

1 1 

Q = 

ω L 

o + ( rL 

+ rC 

) C 

R 

v i 

L 

D 

C 

v o 

• Boost 

' 2 

v$ o() 

s Vi ( 1+ rCs 

C 

)( 1−sL( D R)) 

= 

$ ' 2 

ds () D s 2 1 

( ) + 

Q s + 1 

ω ω 

o 

o 

ω = 

o 

D 

LC 

D 1 

Q = 

ω L r C 

o 

L 

+ + rC 

C 

D R D 

D 

• Buck/Boost 

' 2 

v$ o() 

s Vi ( 1+ rCCs)( 1−sDL ( D R)) 

v i L C v o 

= 

$ () 

' 2 

ds D s 2 1 

( ) + 

Q s + 1 

ω ω 

o 

o 

D 

ωo 

= 

LC 

D 1 

Q= 

ω L r 

o 

C 

+ ( 

( D ) R D 

2 

+ 

rL 

2) 

C 

( D ) 

77/107 

Transfer Functions of Buck Converters 

Transfer Function 


v$ o ( s) 

1 + rCs C 

= V i 

d$ 2 

( s ) Δs 

ω 

o 

FD 

= 

Δ 

1 

i$ L 

( s) 

V 

i 

1 + rCs 

L 

= 

d$ 2 

( s ) r Δs 

ω 

L 

o 

FD 

= 

Δ 

2 

v$ o 

( s ) 1 + rC 

Cs 

= D 

2 

v$ ( s) 

Δs 

ω 

i 

o 

FU 

= 

Δ 

11 

i$ L 

( s) 

= 

v$ ( s) 

i 

D 

R 

1 + RCs 

2 

Δs 

ω 

o 

FU 

= 

Δ 

21 

v$ o 

( s) 

= R 

i$ ( s) 

d 

eq 

s s 

1 + + ( ) 

ω 

1Q1 ω 

1 

2 

Δs 

ω 

o 

2 

FU 

= 

Δ 

12 

i$ L 

( s) 

1 rC 

Cs FU 

=− + = 

i$ 2 

( s) 

Δs 

ω Δ 

d 

o 

22 

2 ω 

o 

Δs = s + 

Q s 2 

+ ω , R = r 

o eq L 

1 1 1 

ω 

o 

= , 

Q = 

LC 

ω L 

o + ( rL 

+ rC) 

C 

R 

1 rL 

1 1 

ω1 = ; Q1 

= 

LC r 

L 

C 

ω1 

+ rC 

L 

r 

C 

78/107 





39



Transfer Functions of Boost Converters 


s s 

( 1 + )( 1 − ) 

v$ o( s) 

V 

i 

ω 

z 

ω 

a 

F 

D 

= 

= 

$ ( ) ( 

' 

d s D ) 

2 2 

Δs 

ω 

Δ 

o 

1 


RC 

$ 1 + 

iL 

( s) 

2V 

I 

= 

2 

$ ( ) ( 

' 

d s D ) 

3 2 

R Δs 

ω 

o 

FD 

= 

Δ 

2 

v$ o 

( s ) 1 1 FU 

= = 

' 

2 

v$ ( s) 

D Δs 

ω Δ 

i 

o 

11 

i$ L 

( s) 

2V 

i 

1+ 

RC 

= 

v$ ( s) ( D 

' 3 2 

) R Δs 

ω 

i 

o 

FU 

= 

Δ 

21 

v$ o 

( s) 

= R 

v$ ( s) 

i 

eq 

s s 

1 + + ( ) 

ω 

1Q 

1 

ω 

1 

2 

Δs 

ω 

o 

2 

FU 

= 

Δ 

12 

i$ L 

( s) 

1 1 + rC 

Cs 

=− 

$ ' 

2 

i ( s) 

D Δs 

ω 

d 

o 

FU 

= 

Δ 

22 

Δs s 

Q s Q D ' 

2 ω 

o 2 

1 

= + + ω 

o 

, = 

ω L rC 

o 

L ' 

+ + DrC 

C 

' 

' 

DR D 

' 

D 

ω 

o 

= 

LC 

' 

D Req 

1 1 

ω1 = ; Q1 

= 

LC r 

L 

C 

ω 1 ( + rC 

' 2 C ) 

D R 

' 2 

1 ( D ) R rL 

ω z = ; ω a = Req 

= 

' 

rC 

L 

D 

C 

2 

D 

D r ' 

C 

eq 

79/107 

Transfer Functions of Buck/Boost Converters 


s s 

( 1+ )( 1− 

) 

v$ o( s) 

Vi ωz ωa 

FD 

= 

= 

$ ( ) ( 

' 

d s D ) 

2 2 

Δs 

ω Δ 

v$ o 

( s) 

D ( 1 + rCs 

C 

) FU 

= 

= 

' 

2 

v$ ( s) 

D Δs 

ω Δ 

i 

v$ o ( s) 

= R 

i$ ( s) 

d 

eq 

s s 

1 + + ( ) 

ω1Q1 ω1 

2 

Δs 

ω 

o 

o 

o 

2 

11 

FU 

= 

Δ 

12 

1 


i$ L( s) 

Vi 

1 + RCs FD 

= 

= 

$ ( ) ( 

' 

d s D ) 

2 2 

R Δs 

ω Δ 

i$ L( s) 

D 11+ 

RCs FU 

= 

= 

v$ ( s) ( D 

' 2 2 

) R Δs 

ω Δ 

i 

i$ L( s) 

11+ 

rCs 

C 

FU 

=− 

= 

$ ' 

2 

i ( s) 

D Δs 

ω Δ 

d 

o 

o 

o 

22 

2 

21 

2 ω 

o 

Δs = s + 

Q s 

2 

+ ω o 

' 

' 

D 

D 

ω 

o 

= , 

Q = 

LC 

ω 

' 2 

1 ( D ) R 

rL 

D 

ω 

R 

rC 

DL 

D D r 

z 

= , ω 

a 

= ; 

eq 

= + 

' 2 ' 

( ) 

C 

1 

L r r 

+ ( + C 

' 2 ' ' 2 

( D ) R D ( D ) ) 

o C L 

Req 

1 1 

ω1 = ω 

o 

; 

Q1 

= 

r 

L 

C 

ω 

1 

' 2 

+ rC 

C 

D R 

eq 

C 

80/107 





40



Q-factor of Buck Converter 

D 

L 

C 

• Buck 

v$ o() 

s 1+ 

rC 

Cs 

= V 

ds $ 

i 

( ) s 2 1 

( ) + 

Q s + 1 

ω ω 

o 

o 

1 

ωo 

= 

LC 

1 1 

Q = 

ω L 

o + ( rL 

+ rC 

) C 

R 

1 1 

Q = 

= 

ω L 

o + ( rL 

+ rC 

) C 

R 

1 

1 

LC 

1 

= 

L 

+ ( rL 

+ rC 

) C 

1 

R 

R 

1 

L 

+ ( rL 

+ rC 

) 

C 

C 

L 

= 

1 

Zo 

rL 

+ r 

+ 

R Z 

o 

C 

v i v o 

C 

1 1 

1 

Q = 

= 

ω L 

Z 

o 

o 

rL 

+ r 

+ ( rL 

+ rC 

) C + 

R 

R Z 

o 

C 

1 1 

Q = 

≈ 

ω L 

o + ( rL 

+ rC 

) C 

R 

LC 

= 

L 

R 

R 

L 

81/107 

Summary: Buck Converters at CCM 


v$ o ( s) 

1 + rCs C FD 

= V i = 

d$ 2 

( s ) Δs 

ω Δ 

o 

1 


i$ L 

( s) 

V 

i 

1 + rCs 

L 

FD 

= 

= 

d$ 2 

( s ) r Δs 

ω Δ 

L 

o 

2 

v i 

r L 

Q i L i o 

L 

D 

r c 

C 

i c 

v c 

i R 

i d 

v o 

v$ o 

( s ) 1 + rC 

Cs FU 

= D = 

2 

v$ ( s) 

Δs 

ω Δ 

i 

v$ o( s) 

= R 

i$ ( s) 

d 

eq 

s s 

1 + + ( ) 

ω1Q1 ω1 

2 

Δs 

ω 

o 

o 

2 

11 

FU 

= 

Δ 

12 

i$ L 

( s) 

D 1 + RCs 

= 

2 

v$ ( s) 

R Δs 

ω 

i 

o 

FU 

= 

Δ 

i$ L 

( s) 

1 rC 

Cs FU 

=− + = 

i$ 2 

( s) 

Δs 

ω Δ 

d 

o 

22 

21 

i i 

L 

Q ON 

r 

i L L io i d 

i c i R 

r c 

v i 

R v o 

C v c 

i i 

L 

D ON 

r L i L i o 

i d 

i c i R 

r c 

R v o 

C 

v c 



&x = A x + B u 

1 1 

y = C x+ 

E u 

1 1 

x d 1 

&x = A x+ 

B u 

2 2 

y= C x+ 

E u 

2 2 

x d 2 


x = Ax + Bu 

y = Cx + Du 

where 

A = A d + A d 

1 1 2 2 

B = B d + B d 

1 1 2 2 

C = C d + C d 

1 1 2 2 

E = E d + E d 

1 1 2 2 

82/107 





41




PWM Switch Model 




83/107 


• Introduction 

• PWM Switch and its Invariant Properties 

• CCM Analysis 

DC and Small-Signal Model of PWM Switch 

PWM Switch Model of Buck Converters 

PWM Switch Model of Boost Converters 

PWM Switch Model of Buck/Boost Converters 

PWM Switch Model of Cuk Converters 


Right-half Plane Zero of the Converters 

PWM Switch Model Including Storage-Time Modulation 

• DCM Analysis 

DC and Small Model of PWM Switch 


Zero of Control-to-Output Transfer Function in DCM 

84/107 





42



PWM Switch Model (1990) 

PWM Switch Method 

[1] V. Vorperian, “Simplified Analysis of PWM Converters Using Model of PWM Switch Part I: 

Continuous Conduction Mode,” IEEE Trans. on Aero. and Elec. Sys., vol. 26, no. 3, pp. 490-496, 

May 1990. 

[2] V. Vorperian, “Simplified Analysis of PWM Converters Using Model of PWM Switch Part II: 

Discontinuous Conduction Mode,” IEEE Trans. on Aero. and Electron. Sys., vol. 26, no. 3, pp. 

497-505, May 1990. 



1. Introduction 

2. Transfer functions 

3. The extra element theorem 

4. The N-extra element theorem 

5. Electronic negative feedback 

6. High-frequency and microwave circuits 

7. Passive filters 

8. PWM switching dc-to-dc converters 

85/107 

Pulse-Width Modulator 

v c 

K 

m 

1 

= = constant 

v 

p 

For natural sampling, 

ds( t) 

v p 

v 

D T ON 

vc 

= = 

p 

T v 

S 

p 

ds $ () = Kv() 

s 

m c 

86/107 





43




(active) 

i% () t 

a 

d 

1-d 

~ 

ic ( t ) 

c 

Instantaneous value 

(common) 

v% () t 

ap 

v% () t 

cp 

p 

(passive) 

PWM Switch Modeling 

[1] V. Vorperian, R. Tymerski, and F.C.Y. Lee, “Equivalent circuit models for resonant and PWM switches,” IEEE 

Transactions on Power Electronics, vol. 4, no. 2, pp. 205-214, Apr 1989. 

[1] V. Vorperian, “Simplified Analysis of PWM Converters Using Model of PWM Switch Part I: Continuous 

Conduction Mode,” IEEE Trans. on Aero. and Electron. Sys., vol. 26, no. 3, pp. 490-496, May 1990. 

[2] V. Vorperian, “Simplified Analysis of PWM Converters Using Model of PWM Switch Part II: Discontinuous 

Conduction Mode,” IEEE Trans. on Aero. and Electron. Sys., vol. 26, no. 3, pp. 497-505, May 1990. 

[3] E. Van Dijk, J. N. Spruijt, D. M. O'Sullivan, and J. B. Klaassens, “PWM-switch modeling of DC-DC converters,” 

IEEE Transactions on Power Electronics,, vol. 10, no. 6, pp. 659 -665, Nov 1995. 

87/107 

Modeling of the Switch 

i 

a 

= Di 

c 

i% () t 

~ t 

ic ( ) 

a 

v 

cp 

= Dv 

ap 

v ap 

v cp 

v% ap 

() t 

v% () t 

cp 

Note: 

i 

a 

denotesthe averagevalueof 

~ 

i ( t) 

a 

During a PWM switching interval: 

~ ⎧ 

~ ie 

( t), 

ia 

( t) 

= ⎨ 

⎩ 0, 

0 ≤ t ≤ DT 

DT ≤ t ≤ T 

s 

s 

s 

⎧v 

~ 

ap 

t 

v~ 

( ), 

cp 

( t) 

= ⎨ 

⎩ 0, 

0 ≤ t ≤ DT 

DT ≤ t ≤ T 

s 

s 

s 

88/107 





44



Small-Signal Perturbation 

Make a small-signal perturbation at a DC operating point 

We can obtain 

d= D+ d $ 

ia= Ia+ 

i$ 

a 

i = I + i$ 

c c c 

v = V + v$ 

cp cp cp 

v = V + v$ 

ap ap ap 

i 

a 

= Di 

c 

ia 

= dic 

I 

a 

+ iˆ 

a 

= ( D + dˆ)( 

I 

c 

+ iˆ 

c 

) 

I + iˆ 

= DI + I dˆ 

+ Diˆ 

+ di ˆˆ 

a 

a 

c 

c 

c 

c 

v 

cp 

= Dv 

ap 

v 

cp 

= dv 

ap 

V + v$ = ( D+ d$ )( V + v $ ) 

cp cp ap ap 

V + v$ = DV + V d$ + Dv$ + dv $ $ 

cp cp ap ap ap ap 

89/107 

DC and AC Analysis 

For dc analysis, eliminate all small signal perturbation terms, we can get its 

equivalent dc model. 

I 

V 

a 

cp 

= DI 

c 

= DV 

ap 

For ac analysis, set all dc terms to zero and neglect second order nonlinear 

terms, we can get its equivalent small-signal ac model. 

iˆ = I dˆ 

+ Diˆ 

a 

c 

v$ = V d$ + Dv$ 

cp ap ap 

c 

90/107 





45




DC Model: 

AC Model: 

⎧ I 

a 

= DI 

c 

⎪⎧ 

iˆ 

= Diˆ 

+ I dˆ 

a c c 

⎨ 

⎨ 

⎩V 

cp 

= DV 

ap 

⎪⎩ vˆ 

= Dvˆ 

cp ap 

+ V 

Vap I a I c 

a 

c 

D d $ 

îa 

a 

1 D 

V V 

ap 

cp 

I 

c 

d$ 

ap 

dˆ 

Dˆ i c 

1 D 

îc 

c 

p 

p 

91/107 

DC Analysis of a Buck Converter 

a 

c 

L 

a 

c 

r L 

p 

r L 

r C 

C 

R 

V i 

1 

p 

D 

R 

V o 

DC Analysis 

V ⎛ ⎞ 

o 

R 

= D⋅ 

⎜ 

⎟ 

Vi 

⎝R+ 

rL 

⎠ 

92/107 





46



AC Analysis of a Buck Converter 

Small-signal equivalent circuit 

model of the buck converter. 

L 

r L 

i L 

i o 

i c 

Note: 

In the following, the hat above 

the small signal variables are 

neglected for simplicity. 

r C 

C 

i i 

V i 

i S 

i D 

v o 

R 

v c 

i d 

a 

V i 

d ˆ 

D 

c 

L 

r L 

i L 

i o 

vˆi 

i i 

i a 

1 

Id 

c 

$ 

p 

i c 

D 

r C 

C 

i c 

R 

v c 

i R 

94/107 

i R 

v o 

i d 

93/107 

AC Analysis: Control-to-Output Transfer Function 

i i 

a 

V 

ap 

D d 

c 

L 

r L 

i L 

i o 

' 

i c 

i R 

1 D 

p 

r C 

C 

R 

v c 

v o 

Short the unrelated voltage source and open the unrelated current source 





47



AC Analysis: Control-to-Output Transfer Function 

v 

cp 

v 

o 

Vi 

= 

D d ⋅ D 

= v 

cp 

R//( rC 

+ 1/ sC) 

( r + sL) + R//( r + 1/ sC) 

L 

C 

R( 1+ 

srC 

C) 

= Vd 

i 2 

s( R+ r) LC+ srrC ( + rRC+ L+ rRC) + ( R+ 

r) 

C L C L C L 

vo() 

s 

R( 1+ 

srC 

C) 

Gd 

() s = = Vi 

2 

ds () s RLC+ s( r r C + L + r RC + r RC) + ( R+ 

r ) 

L C L C L 

if r L



AC Analysis: Line-to-Output Transfer Function 

v 

cp 

= v D 

i 

R( 

rC 

+ 1/ sC) 

R//( 

rC 

+ 1/ sC) 

R + rC 

+ 1/ sC 

vo 

= vcp 

= vi 

D 

( r ) //( 1/ ) 

R( 

rC 

1/ sC) 

L 

+ sL + R rC 

+ sC 

+ 

( rL 

+ sL) 

+ 

R + r + 1/ sC 

R( 

rC 

+ 1/ sC) 

R(1 

+ srC 

C) 

= vi 

D 

= viD 

( r + sL)( 

R + r + 1/ sC) 

+ R( 

r + 1/ sC) 

( r + sL)( 

sRC+ 

sr C + 1) + R( 

sr C + 1) 

L 

R(1+ 

srC 

C) 

= vi 

D 

2 

s ( R + r ) LC + s( 

r r C + r RC + L + r RC) 

+ ( R + r ) 

C 

C 

L C 

L 

vo() 

s 

R( 1+ 

srC 

C) 

Gv 

() s = = D 

2 

v () s s RLC+ s( r r C+ L+ r RC + r RC) + ( R+ 

r ) 

i 

C 

C 

L C L C L 

if r L



AC Analysis: Disturbance-to-Output Transfer Function 

v 

i 

o 

d 

R( 

rC 

+ 1/ sC) 

= R //( rC 

+ 1/ sC) //( rL 

+ sL) 

= 

//( rL 

+ sL) 

R + r + 1/ sC 

R( 

rC 

+ 1/ sC) 

( rL 

+ sL) 

R + rC 

+ 1/ sC 

R( 

rC 

+ 1/ sC)( 

rL 

+ sL) 

= 

= 

R( 

rC 

+ 1/ sC) 

+ r 

R rC 

sC R rC 

sC rL 

sL 

L 

+ sL 

( + 1/ ) + ( + + 1/ )( + ) 

R + r + 1/ sC 

C 

C 

C 

C 

2 

[ r LC + sr r C + sL + r ] 

R s 

C L C 

L 

= 

2 

sr RC + R + s RLC + s r LC + sr r C + sr RC + sL + r 

2 

C 

L 

C 

C L 

L 

C 

2 

[ r LC + sr r C + sL + r ] 

R( 

srC 

C + 1)( rL 

+ sL) 

R s 

C 

L C 

L 

= 

= 

R( 

sr C + 1) + ( sRC + sr C + 1)( r + sL) 

sr RC + R + ( sRC + sr C + 1)( r + sL) 

L 

C 

L 

v 

i 

d 

o 

2 

RsrLC 

C 

+ sL ( + rrC 

L C 

) + rL 

= 

2 

s ( R+ r ) LC + s L+ ( r + r ) RC + r r C + ( R+ 

r ) 

C C L C L L 

99/107 


if r L




2 1 rL 

v s 

s rC 

s 

o( 

) 

+ + 

Z s 

C LC 

o( 

) = = 

i s 1 rC 

r 

d( 

) 2 ⎡ + 

L⎤ 

1 

s + s 

⎢ 

+ + 

⎣RC 

L ⎥ 

⎦ LC 

2 1 

ω o = 

LC 

ω= 1 LC 

ω 1 o 

r C 

r L 

= + + 

Q RC L 

2 

1 ωo 

1 1 1 1 

Q= 

= 

= 

ω 1 rC 

+ rL 

r r L 

o o 

⎛ 1 

C 

+ 

+ 

ω 

L ⎞ ωo 

LC⎜ 

+ ⎟ + ( rC 

+ rL 

) L 

RC L ⎝RC 

L ⎠ R 

101/107 


1 1 

Q = 

ω L 

o + ( rC 

+ rL) 

L 

R 

Z ( s) 

op 

2 ⎡ 1 rC 

+ rL 

⎤ 1 

= s + s 

⎢ 

+ + 

⎣RC 

L ⎥ 

⎦ 

2 ω = 

o 2 

s + s +ω 

o 

Q 

2 1 rL 

Zoq( 

s) 

= s rC 

+ s + 

C LC 

r ⎛ 

2 L ⎞ 

L 

rC 

= 

⎜ LCs + s + 1 

⎟ 

LC⎝ 

rL 

rL 

⎠ 

2⎛ 

1 

= Reqω 

o 

⎜ s 

2 

⎝ω1 

2 

LC 

1 ⎞ 

+ s + 1⎟ 

ω1Q 

1 ⎠ 

ωo 

Δs= s 2 + s + ω 

2 

Q 

R 

eq 

= r 

L 

1 

ω 1 

= r L 

r LC 

C 

1 rL 

Q1 

= ω L 

1 

o 

102/107 





51




The exact output impedance is derived as: 

v 

i 

o 

d 

= 

= 

= 

R 

C 

2 

s ( R + r ) LC + s 

C 

2 

[ s r LC + s( 

L + r r C ) + r ] 

[ L + ( r + r ) RC + r r C ] 

C 

C L 

+ ( R + r ) 

2 

s rC 

LC + s( 

L + rL 

rC 

C ) + rL 

2 rC 

⎡ L 

C ⎤ rL 

s (1 + ) LC + s r r C r r 

R ⎢ 

+ ( 

C 

+ 

L 

) + 

C L 

+ (1 + ) 

⎣ R 

R ⎥ 

⎦ R 

2 1 rL 

rC 

rL 

s rC 

+ s( 

+ ) + 

C L LC 

2 rC 

⎡ 1 1 rL 

rC 

⎤ rL 

1 

s (1 + ) + s ( rC 

rL 

) + (1 + ) 

R ⎢ 

+ + + 

⎣ RC L R ⎥ 

⎦ R LC 

L 

L C 

L 

L 

103/107 


2 

Z ( s) 

= s r 

R 

oq 

eq 

= r 

= R 

L 

⎛ 1 rL 

r 

+ s⎜ 

+ 

⎝C 

L 

2⎛ 

1 

ω 

⎜ 

o 

s 

2 

⎝ω1 

eq 

C 

1 

ω 1 = r L 

r LC 

C 

1 1 

Q1 

= 

ω L 

1 + rC 

C 

r 

L 

2 

C 

⎞ r ⎛ 

L 

rL 

r 

⎟+ = 

⎜ 

⎠ LC LC⎝ 

r 

1 ⎞ 

+ s + 1 

⎟ 

ω1Q 

1 ⎠ 

C 

L 

2 L ⎞ 

LCs + ( + r C) 

s + 1 

⎟ 

C 

rL 

⎠ 

104/107 





52



Output Impedance of the Buck Converter 

Output Impedance of the Buck Converter: 

2 1 rL 

rC 

rL 

v s 

s rC 

s 

o( 

) 

+ ( + ) + 

Z s 

C L LC 

o( 

) = = 

i s rC 

1 1 rL 

rC 

r 

d 

( ) 2 ⎡ 

⎤ L 

1 

s (1+ 

) + s ( rC 

rL 

) + (1+ 

) 

R ⎢ 

+ + + 

⎣RC 

L R ⎥ 

⎦ R LC 

vo( s) 

Zo( s) 

= = R 

i ( s) 

d 

eq 

s s 

1+ + ( ) 

ω1Q1 ω1 

2 

Δs 

ω 

o 

2 

2 ωo 

Δs= s + 

Q s 2 

+ ω , R = r 

o eq L 

1 1 1 

ωo 

= , 

Q = 

LC 

ω L 

o + ( rL 

+ rC) 

C 

R 

1 rL 

1 1 

ω1 = ; Q1 

= 

LC r 

L 

C 

ω1 

+ rC 

L 

r 

C 

105/107 

Recommended Books: Modeling and Simulation 

Dynamic Analysis of Switching-Mode DC/DC Converters, 

Andre'S. Kislovski, Richard Redl, and Nathan O. Sokal, 

Van Nostrand Reinhold, New York, 1991. 

Switch-Mode Power Supply Simulation: Designing with SPICE 3 

Steven M. Sandler, 

McGraw-Hill Professional; 1 edition, Nov. 11, 2005. 

Switch-Mode Power Supplies - SPICE Simulations and Practical Designs, 

Christophe Basso, 

McGraw-Hill, Feb. 1, 2008. 

Complex Behavior of Switching Power Converters, 

Chi Kong Tse, CRC Press, 2004. 

106/107 





53



References: Modeling of DC-DC Converters 

Recommended Readings 

[1] D. Maksimovic, A. M. Stankovic, V. J. Thottuvelil, G. C. Verghese, "Modeling and simulation of power electronic converters," 

Proceedings of the IEEE, vol. 89, no. 6, pp. 898-912, June 2001. 

[2] A. J. Forsyth and S. V. Mollov, "Modelling and control of DC-DC converters," IEEE Power Engineering Journal, vol. 12, no. 5, 

pp. 229-236, 1998. 

[3] R. D. Middlebrook, "Small-signal modeling of PWM switched-mode power converters," IEEE Proc. vol. 76, no. 4, pp. 343- 

354, April 1988. 

[4] R. D. Middlebrook and S. C'uk, "A general unified approach to modeling switching converter power stages," IEEE PESC Conf. 

Rec., pp. 18-34, 1976. [Pioneer paper] 

SPS Modeling and Control Loop Design 

[5] V. Vorperian, “Simplified Analysis of PWM Converters Using Model of PWM Switch Part I: Continuous Conduction Mode,” 

IEEE Trans. on Aero. and Electron. Sys., vol. 26, no. 3, pp. 490-496, May 1990. 

[6] V. Vorperian, “Simplified Analysis of PWM Converters Using Model of PWM Switch Part II: Discontinuous Conduction 

Mode,” IEEE Trans. on Aero. and Electron. Sys., vol. 26, no. 3, pp. 497-505, May 1990. 

[7] V. Voperian, R. Tymerski, and F. C. Lee, “Equivalent circuit models for resonant and PWM switches,” IEEE Trans. on Power 

Electronics, vol. 4, no. 2, pp. 205-214, April 1989. 

[8] E. Van Dijk, J. N. Spruijt, D. M. O'Sullivan, and J. B. Klaassens, “PWM-switch modeling of DC-DC converters," IEEE 

Transactions on Power Electronics, vol. 10, no. 6, pp. 659 -665, Nov 1995. 


[11] D. Maksimovic and S. Cuk, “A unified analysis of PWM converters in discontinuous modes,” IEEE Trans. Power Electron., 

vol. 6, pp. 476–490, May 1991. 

[12] J. Sun, D. M. Mitchell, M. F. Greuel, P. T. Krein, and R. M. Bass, “Averaged modeling of PWM converters operating in 

discontinuous conduction mode,” IEEE Trans. Power Electron., vol. 16, pp. 482-492, July 2001. 

107/107 





54

Advances in Averaged Switch 

Modeling and Simulation 

Dragan Maksimovic * and Robert Erickson 

Colorado Power Electronics Center 

CoPEC 

http://ece-www.colorado.edu/~pwrelect 

* Acknowledgment: the work by Dragan Maksimovic was supported in part by the National Science Foundation 

CAREER Award, Grant No. ECS-9703449. 

1. Introduction: converter modeling approaches and objectives 

2. Averaged switch modeling of PWM converters operating in the 

continuous conduction mode (CCM) 

• Basics of averaged switch modeling 

• Switch network steady-state and small-signal models 

• Using averaged-switch model to predict converter steady-state 

characteristics and small-signal dynamics in CCM 

• PSpice implementation of the averaged switch model 

• Application examples: small-signal dynamics, 

conduction losses and efficiency of a Sepic converter 

• Averaged switch modeling exercise: include switching losses

3. Averaged switch modeling of PWM converters operating in 

discontinuous conduction mode (DCM) 

• Averaged switch model in DCM 

• Switch network steady-state and small-signal models in DCM 


characteristics and small-signal dynamics in DCM 

• Combined CCM/DCM averaged switch model 

• PSpice implementation of combined CCM/DCM models 

• Application examples: 

Large-signal transient response of a SEPIC 

Flyback converter small-signal frequency responses in CCM 

and DCM 

4. Averaged modeling of PWM converters with current-programmed 

mode (CPM) control 

• Averaged switch model in CCM and DCM 

• Steady-state and AC models in CCM and DCM 

• Large-signal averaged CCM/DCM model for CPM controller 

• PSpice implementation of the CPM controller model 

• Application example: buck converter with CPM controller 

5. Single-phase low-harmonic rectifiers 

• The ideal rectifier 

• Averaged models of rectifiers 


DCM boost rectifier 

SEPIC rectifier with nonlinear-carrier control 

6. Summary 

7. Bibliography

• http://ece-www.colorado.edu/~pwrelect/publications 

seminar slides, collection of simulation examples, library of PSpice 

models used in the examples, and many other CoPEC publications 

and presentation materials 

• http://ece-www.colorado.edu/~pwrelect/ is the CoPEC home page 

• http://ece-www.colorado.edu/~pwrelect/book/bookdir.html 

is the home page for the Textbook: R.W.Erickson, Fundamentals of 

Power Electronics 

• Power Electronics courses at the University of Colorado: 

• Power Electronics 1: http://ece-www.colorado.edu/~ecen5797 

• Power Electronics 2: http:// ece-www.colorado.edu/~ecen5807 

• Power Electronics Lab: http:// ece-www.colorado.edu/~ecen4517 

• All simulation examples completed using free PSpice evaluation 

version available from: http://www.orcad.com 

Engineering design based on converter modeling: 

• Predict converter system behavior, validate models by experiments 

• Use the model to predict performance under worst-case conditions 

• Improve design until worst-case behavior meets specifications 

(or until reliability and production yield are acceptably high) 

Models: 

• Circuit models that yield design-oriented, analytical results 

• Models for computer simulation 

Results of interest: 

• Steady-state characteristics 

• Component stresses, losses, efficiency 

• Large and small-signal dynamic responses

• Describe basic averaged switch modeling approach 

• Develop averaged models for 

Converters in continuous conduction mode (CCM) 

Converters in discontinuous conduction mode (DCM) 

Converters with Current-Programmed Mode (CPM) controller 

Single-phase power-factor correctors 

• Summarize analytical results for steady-state and dynamic responses 

• Demonstrate PSpice implementations of averaged-switch models and 

controllers 

• Present application examples 

Large-signal transient responses and small-signal dynamics of DC-DC 

converters and single-phase power-factor correctors 

• Switch network is replaced by averaged circuit model. Switching 

harmonics are removed, and low-frequency components of waveforms 

are modeled in a simple way. 

• A very general approach to modeling converter losses, efficiency, and 

dynamics. 

• Yields an intuitive understanding of converter behavior in CCM, DCM, 

current-programmed mode, etc. 

• Applicable to all types of converters: dc-dc converters, as well as dc-ac 

inverters, ac-dc low-harmonic rectifiers, ac-ac matrix converters. 

• Well-suited to simulation 

• Well developed and understood technique, easily taught to students. 

• Main reference for the material in this seminar: 

R.W.Erickson, Fundamentals of Power Electronics, Chapman and 

Hall, 1997. 

Bibliography has a large collection of other selected references

averaging 

Switching 

network + d + 

– – 

Averaged 

switch 

model 

+ 

– 

Switching converter circuit 

Large-signal averaged circuit model 

+ 

- 

D 

1 

2 

S 

4 A 

ccm-dcm1 

5 

duty 

3 K 

simulation 

model 

+ 

– 

linearization 

+ 

– 

D+d^ 

DC and small-signal averaged circuit model 

Model implementation for simulation 

DC, AC and Transient simulation 

G ( s) 

c 

1 s / ws 

Gco 

1 (1/ Q) 

s / w ( s / w ) 

o 

2 

o 

Analytical results: 

steady-state characteristics 

and small-signal dynamics 

• Basics of averaged switch modeling 

• Switch network steady-state and small-signal models 


characteristics and small-signal dynamics in CCM 

• PSpice implementation of averaged switch models 

- ideal switches (ccm1) 

- switches with conduction losses (ccm2) 

- switches in converters with isolation transformer (ccm3) 

- switch with conduction losses in converters with (possibly) 

isolation transformer (ccm4) 

• Application example: 

- SEPIC small-signal frequency response, conduction losses and 

efficiency 

• Averaged switch modeling exercise: include switching losses

Given a PWM converter operating in continuous conduction mode: 

V g 

L 1 

C 1 

D 1 

+ 

+ C – L 2 

R v 

2 

Q 1 

– 

SEPIC 

example 

Separate the switching elements from the remainder of the converter... 

• Define a switch 

network, 

containing all of 

the converter 

switching 

elements. 

• The remainder of 

the converter is 

linear and timeinvariant. 

• The terminal 

voltages and 

currents of the 

switch network 

can be arbitrarily 

defined. 

v g 

(t) 

L 1 

+ L – 2 

i L1 

(t) 

+ v C1 

(t) – 

+ 

C 1 

C 2 

v C2 

(t) R 

i L2 

(t) 

– 

i 1 

(t) Switch network i 2 

(t) 

+ 

v 1 

(t) 

– Q 1 D 1 

– 

v 2 

(t) 

+ 

Duty 

cycle 

d(t)

Power input 

v g 

(t) 

Time-invariant network 

containing converter reactive elements 

+ C 

L 

– 

R 

Load 

+ 

v(t) 

+ v C 

(t) – 

i L 

(t) 

– 

i 1 

(t) 

i 2 

(t) 

+ 

Switch network 

+ 

v 1 

(t) 

port 1 

port 2 

v 2 

(t) 

– 

– 

Control 

input 

d(t) 

The number of ports in the switch network is less than or equal 

to the number of SPST switches in the converter 

Simple dc-dc case, in which converter contains two SPST 

switches: switch network contains two ports 

The switch network terminal waveforms are then the port voltages and 

currents: v 1 

(t), i 1 

(t), v 2 

(t), and i 2 

(t). 

Two of these waveforms can be taken as independent inputs to the 

switch network; the remaining two waveforms are then viewed as 

dependent outputs of the switch network. 

Switch network also includes control input d(t) 

Definition of the switch network terminal quantities is not unique. 

Different definitions lead equivalent results having different 

forms

i 1 

(t) 

+ 

i 2 

(t) 

+ 

i 1 

(t) Ts 

+ 

1 : D 

i 2 

(t) Ts 

+ 

v 1 

(t) 

v 2 

(t) 

v 1 

(t) Ts 

v 2 

(t) Ts 

– 

– 

– 

– 

i 1 

(t) 

+ 

i 2 

(t) 

+ 

i 1 

(t) Ts 

+ 

D' : 1 

i 2 

(t) Ts 

+ 

v 1 

(t) 

v 2 

(t) 

v 1 

(t) Ts 

v 2 

(t) Ts 

– 

– 

– 

– 

i 1 

(t) 

+ 

i 2 

(t) 

+ 

i 1 

(t) Ts 

+ 

D' : D 

i 2 

(t) Ts 

+ 

v 1 

(t) 

v 2 

(t) 

v 1 

(t) Ts 

v 2 

(t) Ts 

– 

– 

– 

– 

• The switch network can be defined arbitrarily, as long as 

its terminal voltages and currents are independent, and 

the switch network contains no reactive elements. 

• It is not necessary that some of the switch network terminal quantities 

coincide with inductor currents or capacitor voltages of the converter, or 

be nonpulsating. 

• The object is simply to write the averaged equations of the switch network; 

i.e., to express the average values of half of the switch network terminal 

waveforms as functions of 

the average values of the remaining switch network terminal waveforms, 

and 

the control input.

v 1 (t) 

v C1 + v C2 

v 1 (t) Ts 

0 

0 

0 

dT s 

T s 

t 

v g (t) 

i L1 (t) 

+ 

+ v (t) – 

L 1 C 1 

C1 

L 2 C 2 

v C2 (t) R 

i 1 (t) 

i L1 + i L2 

i L2 (t) 

– 

i 1 (t) T2 

0 

0 

0 dT s 

v 2 (t) 

v C1 + v C2 

T s 

t 

i 1 (t) 

+ 

v 1 (t) 

– 

+ 

– 

D 1 


Q 1 

– 

v 2 (t) 

+ 

i 2 (t) 

v 2 (t) T2 

0 

0 0 dT s 

T s 

t 

Duty 

cycle 

d(t) 

i 2 (t) 

i L1 + i L2 

i 2 (t) Ts 

0 

0 

0 

dT s 

T s 

t 

x(t) Ts 

= 1 T s 

t 

t + T s 

x(t)dt 

Now average all waveforms over one switching period: 

v g 

(t) Ts 

Power input 

Averaged time-invariant network 

containing converter reactive elements 

+ C 

L 

– 

R 

Load 

+ 

v(t) Ts 

+ v C 

(t) Ts 

– 

i L 

(t) Ts 

– 

i 1 

(t) Ts 

i 2 

(t) Ts 

+ 

v 1 

(t) Ts 

– 

port 1 

Averaged 


port 2 

+ 

v 2 

(t) Ts 

– 

Control 

input 

d(t)

The basic assumption is made that the natural time constants of the 

converter are much longer than the switching period, so that the 

converter contains low-pass filtering of the switching harmonics: 

One may average the waveforms over an interval that is short 

compared to the system natural time constants, without 

significantly altering the system response. 

In particular, averaging over the switching period T s 

removes the 

switching harmonics, while preserving the low-frequency 

components of the waveforms. 

This step removes the small but mathematically-complicated 

switching harmonics, leading to a relatively simple and tractable 

converter model. 

In practice, the only work needed for this step is to average the switch 

dependent waveforms. 

(small switching ripple is neglected) 

v 1 

(t) 

v C1 

+ v C2 

v 2 

(t) 

v C1 

+ v C2 

v 1 (t) Ts 

0 

0 

0 

dT s 

T s 

t 

v 2 (t) T2 

0 

0 

0 dT s 

T s 

t 

v 1 (t) Ts 

= d'(t) 

v C1 (t) Ts 

+ v C2 (t) Ts 

v 2 (t) Ts 

= d(t) 

0 

0 

i 1 (t) Ts 

= d(t) i L1 (t) Ts 

+ i L2 (t) Ts 

i 2 (t) Ts 

= d'(t) i L1 (t) Ts 

+ i L2 (t) Ts 

v C1 (t) Ts 

+ v C2 (t) Ts 

i 1 

(t) 

i L1 

+ i L2 

i 2 

(t) 

i L1 

+ i L2 

0 

0 

0 

dT s 

T s t 

0 dT s 

T s t 

i 1 (t) T2 

i 2 (t) Ts

We can write 

i L1 (t) Ts 

+ i L2 (t) Ts 

= i 1(t) Ts 

d(t) 

Result 

+ 

– 

Hence 

v C1 (t) Ts 

+ v C2 (t) Ts 

= v 2(t) Ts 

d(t) 

v 1 (t) Ts 

= d'(t) 

d(t) 

i 2 (t) Ts 

= d'(t) 

d(t) 

i 1 

(t) Ts 

d'(t) + d'(t) 

v 1 

(t) Ts 

v 

d(t) 2 (t) Ts 

i 

– d(t) 1 (t) Ts 

– i 2 

(t) Ts 

Averaged switch network 

v 2 (t) Ts 

Modeling the switch network via 

averaged dependent sources 

i 1 (t) Ts 

+ 

v 2 

(t) Ts 

Original switch network 

i 1 

(t) 


i 2 

(t) 

+ 

– 

v 1 

(t) 

v 2 

(t) 

– Q 1 D 1 

+ 

Duty 

cycle 

d(t) 

Averaged steady-state model: 

“DC transformer” 

• Correctly represents the 

relationships between the dc 

and low-frequency 

components of the terminal 

waveforms of the switch 

network 

+ 

V 1 

– 

I 1 D' : D 

I 2 

– 

V 2 

+

Replace switch network with dc transformer model 

C 1 

L 2 R 

I L1 

+ V C1 

– 

+ 

V g 

+ 

– 

L 1 

C 2 

V C2 

I L2 

– 

I 1 

D' : D 

+ 

V 1 

– 

– 

V 2 

+ I 2 

• Can now let inductors 

become short circuits, 

capacitors become open 

circuits, and solve for dc 

conditions. 

• Can simulate this model 

using PSPICE, to find 

transient waveforms 

Perturb and linearize the switch 

network averaged waveforms 

about a quiescent operating 

point. Let: 

d(t)=D + d(t) 

v 1 (t) Ts 

= V 1 + v 1 (t) 

i 1 (t) Ts 

= I 1 + i 1 (t) 

v 2 (t) Ts 

= V 2 + v 2 (t) 

i 2 (t) Ts 

= I 2 + i 2 (t) 

Voltage equation becomes 

D + d V 1 + v 1 = D'–d V 2 + v 2 

Eliminate nonlinear terms 

and solve for v 1 

terms: 

V 1 + v 1 

= D' 

D V 2 + v 2 – d V 1 + V 2 

D 

= D' 

D V 2 + v 2 

– d 

V 1 

DD'

Current equation becomes 

D + d I 2 + i 2 = D'–d I 1 + i 1 

Eliminate nonlinear terms 

and solve for i 2 

terms: 

I 2 + i 2 

= D' 

D I 1 + i 1 – d I 1 + I 2 

D 

= D' 

D I 1 + i 1 – d 

I 2 

DD' 

Reconstruct an equivalent circuit that corresponds to these smallsignal 

equations: 

I 1 + i 1 

I 2 + i 2 

+ 

+ 

– 

V 1 + v 1 

V 1 

D' : D 

– 

DD' d I 2 

V 2 + v 2 

DD' d 

– 

+ 

Transistor port 

Diode port 

A general small-signal ac model for the PWM switch network 

operating in CCM.

Replace switch network with small-signal ac model: 

C 1 

L 2 R 

V C1 + v C1 

+ 

V g + v g 

I L1 + i L1 

I L2 + i L2 

+ 

– 

L 1 

C 2 

V C2 + v C2 

– 

D' : D 

+ 

– 

V 1 

DD' d 

I 2 

DD' d 

Can now solve this 

model to determine ac 

transfer functions 

i 1 

(t) 

+ 

v 1 

(t) 

i 2 

(t) 

+ 

v 2 

(t) 

I 1 + i 1 1 : D 

I 2 + i 2 

+ 

+ 

V 1 d 

V 1 + v 1 

I 2 d 

V 2 + v 2 

+ 

– 

– 

– 

– 

– 

i 1 

(t) 

+ 

v 1 

(t) 

i 2 

(t) 

+ 

v 2 

(t) 

I 1 + i 1 D' : 1 

I 2 + i 2 

+ 

V 1 + v 1 

+ 

– 

V 2 d 

I 1 d 

+ 

V 2 + v 2 

– 

– 

– 

– 

i 1 

(t) 

+ 

v 1 

(t) 

i 2 

(t) 

+ 

v 2 

(t) 

I 1 + i 1 D' : D 

I 2 + i 2 

+ 

+ 

– 

V 1 + v 1 

V 1 

DD' d I 2 

V 2 + v 2 

DD' d 

+ 

– 

– 

– 

–

Control-to-output and line-to-output transfer functions G vd 

(s) and G vg 

(s) 

Converter G g0 G d0 0 Q z 

buck 

D 

V 

1 

D 

LC 

R 

C 

L 

boost 

1 

V 

D' 

D' 

D' 

D'R 

C D' 2 R 

LC 

L L 

buck-boost 

– 

D' 

D V 

D' 

DD' 2 

D'R 

C D' 2 R 

LC 

L DL 

where the transfer functions are written in the standard forms 

G vd (s)=G d0 

1– s z 

1+ s 

Q 0 

+ s 0 

2 

G vg (s)=G g0 

1 

1+ s 

Q 0 

+ s 0 

2 

ccm1 

i 1 (t) 

+ 

v 1 (t) 

_ 

1 

D 

S 

2 

switch 

network 

3 

K 

A 

4 

i 2 (t) 

+ 

v 2 (t) 

_ 

averaging 

i 1 

i 2 

averaged-switch 

+ 

1 model 3 

D(sub-circuit) 

K 

1-d + E 

– t G d 

d v 1-d 

v 2 

d i 1 

1 

S 

A 

_ 

2 

5 

4 

duty 

d 

+ 

v 2 

_ 

• Controlled voltage source E t 

replaces the transistor, controlled 

current source G d 

replaces the diode 

• Duty ratio d is input to the subcircuit 

• Large-signal, nonlinear model suitable for DC, AC or Transient 

simulation 

• The same model can be applied in any two-switch PWM converter 

(the transistor and the diode need not have a common node) 

• Limitations: ideal switches, CCM only, valid for two-switch 

converters without isolation transformer

ccm1 

D 

S 


1 network 

(sub-circuit) 

+ E 

– t G d 

2 

5 

duty 

U1 

D 

1 4 A 

ccm1 

2 3 

S 5 K 

duty 

3 

4 

K 

A 

********************************************************** 

* MODEL: ccm1 

* Application: two-switch PWM converters 

* Limitations: ideal switches, CCM only, no transformer 

********************************************************** 

* Parameters: none 

********************************************************** 

* Nodes: 

* 1: transistor+ (D) 

* 2: transistor- (S) 

* 3: diode cathode (K) 

* 4: diode anode (A) 

* 5: duty ratio (duty) 

********************************************************** 

.subckt ccm1 1 2 3 4 5 

Et 1 2 value={(1-v(5))*v(3,4)/v(5)} 

Gd 4 3 value={(1-v(5))*i(Et)/v(5)} 

.ends 

********************************************************** 

ccm1 

+ 

- 

L1 

1 800u 

Vg 

50V 

2x 

R1 

0.5 

C1 

2 3 4 

100u 

R2 

0.1 

L2 

100u 

C2 

100u 

V 

R3 

50 

U1 

D 

1 4 A 

ccm1 

2 3 

S 5 K 

duty 

sepic-ccm1.sch 

ACMAG=1V 

DC=0.5V 

+ 

- 

Vd 

Objective: generate small-signal control-to-output frequency responses

ccm1 

(A) sepic-ccm1.dat 

80 

magnitude || vout/d || 

40 

0 

-20 

0d 

DB(V(4)) 

phase of vout/d 

-100d 

-200d 

small-signal control-to-output response 

Vout=50V, R=50, D=0.5 

-270d 

10Hz 100Hz 1.0KHz 10KHz 100KHz 

P(V(4)) 

Frequency 

• Subcircuit ccm1 is implementation of a large-signal, nonlinear 

averaged model of the switch network 

• Averaged circuit model of the converter is obtained simply by replacing 

switching devices with the averaged-switch subcircuit model 

• Linearization and AC small-signal analysis are performed by the 

simulator 

• Small-signal dynamic responses can be easily generated for different 

operating points or different sets of parameter values

• MOS transistor model: on-resistance R ON 

• Diode model: constant forward voltage drop V D 

in series with R d 

resistance 

• Switch network 

+ 

i 1 (t) 

v 1 (t) 

_ 

1 

D 

S 

2 

switch 

network 

3 

K 

A 

4 

i 2 (t) 

+ 

v 2 (t) 

_ 

• Waveforms 

v 1 

(t) 

v+V D 

+R d 

i 

i 1 

(t) 

i 

R on 

i 

0 dT s 

T t 

s 

v 2 

(t) 

v-R on 

i 

0 dT s 

T t 

s 

i 2 

(t) 

i 

0 dT -V t 

s 

D 

-R d 

i T s 

0 dT s 

T s 

t 

ccm2 

v 1 

(t) 

i 1 

(t) 

v+V D 

+R d 

i 

i 

R on 

i 

0 dT s 

T t 

s 

0 dT s 

T t 

s 

v 2 

(t) 

i 2 

(t) 

v-R on 

i 

i 

t 

0 dT -V 

s 

T 0 dT 

s 

s 

T t 

D 

-R d 

i 

s 

v 

1 

T 

v 

dR 

1 Ts 

v1 

v 

T 2 

s 

s 

R 

on 

i 

d 

1 

on 

T 

s 

T 

s 

i 

T 

s 

v 

T 

s 

1 d 

1 d v 

d 

R 

2 

d 

i 

1 

T 

s 

T 

s 

i 1 

T 

d 

i 

s T s 

i (1 d) 

2 

V 

T 

s 

1 d 

d 

i 

T 

i2 

i 

T 

1 

D 

1 

s T s 

R 

d 

d 

d 

i 

v 

1 

T 

s 

s 

V 

D

ccm2 

D 

S 


sub-circuit 

1 

+ 

– E ron 

+ E 

– t 

2 

G d 

5 

duty 

Subcircuit implementation 

U2 

D 

1 

ccm2 

2 

S 5 

duty 

3 

4 

4 A 

3 K 

K 

A 

********************************************************** 

* MODEL: ccm2 

* Application: two-switch PWM converters, includes 

* conduction losses due to Ron, VD, Rd 

* Limitations: CCM only, no transformer 

********************************************************** 

* Parameters: 

* Ron=transistor on resistance 

* VD=diode forward voltage drop (constant) 

* Rd=diode on resistance 

********************************************************** 

* Nodes: (same as in ccm1) 

********************************************************** 

.subckt ccm2 1 2 3 4 5 

+params: Ron=0 VD=0 Rd=0 

Eron 1 1x value={i(Et)*(Ron+(1-v(5))*Rd/v(5))/v(5)} 

Et 1x 2 value={(1-v(5))*(v(3,4)+VD)/v(5)} 

Gd 4 3 value={(1-v(5))*i(Et)/v(5)} 

.ends 

********************************************************** 

ccm2 

+ 

- 

L1 

1 800u 

Vg 

50V 

2x 

R1 

0.5 

C1 

2 3 

4 

100u 

R2 

0.1 

L2 

100u 

C2 

100u 

V 

Iload 

1A 

10K 

R4 

+ 

- 

PARAMETERS: 

Ron 0.0 

U1 

D 

1 4 A 

ccm2 

2 3 

Ron={Ron} S 5 K 

duty 

+ 

DC=0.5V Vd 

- 

Rd=0.05 

VD=0.8V 

Objective: find converter efficiency as a function of the transistor 

on-resistance, for a range of loads

ccm2 

100 

(D) sepic-ccm2.dat 

Efficiency [%] (only conduction losses are included) 

95 

R on =0 

90 

0.1 

0.2 

85 

0.3 

-100*V(4)* I(Iload)/ V(1)/ I(Vg) 

80 

1.0A 1.5A 2.0A 2.5A 3.0A 3.5A 4.0A 4.5A 5.0A 

I_Iload 

0.4 

R on =0.5 

ccm3 

Switch network Waveforms 

1:n 

v 1 

(t) 

v 

i 1 

(t) 

i 

i 1 

(t) 

+ 

v 1 

(t) 

_ 

1 

D 

S 

2 

switch 

network 

3 

K 

A 

4 

i 2 

(t) 

+ 

v 2 

(t) 

_ 

0 dT s 

T t 

s 

v 2 

(t) 

n v 

0 dT s 

T t 

s 

i 2 

(t) 

i/n 

PRIMARY SECONDARY 

t 

0 dT s 

T 0 dT 

s 

s 

T t 

s 

1 d 

nd 

v1 

v 

T s 

2 T s 

1 d 

nd 

i2 

i 

T s 

1 T s 

• Converters: Flyback, Cuk, Sepic, Inverse Sepic (Zeta), with isolation transformer

ccm3 

D 

S 


1 network 

(sub-circuit) 

+ E 

– t G d 

2 

5 

duty 

U3 

D 

1 

ccm3 

2 

S 5 

duty 

3 

4 

4 A 

3 K 

K 

A 

********************************************************** 

* MODEL: ccm3 

* Application: two-switch PWM converters, 

* with (possibly) transformer 

* Limitations: ideal switches, CCM only 

********************************************************** 

* Parameters: 

* n=transformer turns ratio 1:n (primary:secondary) 

********************************************************** 


********************************************************** 

.subckt ccm3 1 2 3 4 5 

+params: n=1 

Et 1 2 value={(1-v(5))*v(3,4)/v(5)/n} 

Gd 4 3 value={(1-v(5))*i(Et)/v(5)/n} 

.ends 

********************************************************** 

ccm4 

• Combined ccm2 and ccm3 averaged-switch models 

• Parameters: 

• Transistor on resistance R on 

• Diode forward voltage drop V D 

• Diode on resistance R d 

• Transformer turns ratio n 

• A general model implementation valid for all two-switch converters 

operating in CCM

ccm4 

D 

S 


sub-circuit 

1 

+ 

– E ron 

+ E 

– t 

2 

G d 

5 

duty 

Subcircuit implementation 

U4 

D 

1 

ccm4 

2 

S 5 

duty 

3 

4 

K 

A 

4 A 

3 K 

* MODEL: ccm4 

* Application: two-switch PWM converters, includes 

* conduction losses due to Ron, VD, Rd 

* and (possibly) transformer 

* Limitations: CCM only 

********************************************************** 

* Parameters: 

* Ron=transistor on resistance 

* VD=diode forward voltage drop (constant) 

* Rd=diode on resistance 


********************************************************** 


********************************************************** 

.subckt ccm4 1 2 3 4 5 

+params: Ron=0 VD=0 Rd=0 n=1 

Eron 1 1x value={i(Et)*(Ron+(1-v(5))*Rd/n/n/v(5))/v(5)} 

Et 1x 2 value={(1-v(5))*(v(3,4)+VD)/v(5)/n} 

Gd 4 3 value={(1-v(5))*i(Et)/v(5)/n} 

.ends 

• Use averaged-switch modeling approach to construct an 

averaged model that includes switching losses 

• Loss mechanism example: diode reverse recovery

Example: diode stored 

charge in boost converter 

v g 

(t) 

i L 

L 

(t) 

+ 

– 

i 1 

(t) 

+ 

v 1 

(t) 

i 2 

(t) 

+ 

v 2 

(t) C 

R 

+ 

v(t) 

v 1 

(t) 

Waveforms: 

– 

– 

– 

v 2 

v 2 

i 2 

(t) 

• Other switching loss mechanisms 

0 

0 

are ignored in this example; one 

dT t 

s 

can include other losses if 

t r 

desired, using a similar procedure 

T s 

i 1 

i 1 

• Determine averaged terminal 

waveforms of switch network 

0 

0 

t 

Area –Q r 

• Construct averaged equivalent 

circuit model 

1 

v1 t 1 d T 

T 

s tr 

v2 

t 

s T 

T 

s 

s 

v 1 

(t) 

v 2 

v 2 

i2 t 1 

Ts 

d 

i 

1 

t 

Ts 

Q 

T 

r 

s 

0 

0 

t 

t r 

dT s 

t 

i 2 

(t) 

T s 

i 1 

i 1 

t r 

= diode reverse recovery time 

Q r 

= diode recovered charge 

0 

0 

Area –Q r

v 1 

+ 

t 

_ 

i 1 

t 

r 

v1 t 1 d v t 

T 

2 

s T 

T 

s 

s 

i 

t 

2 

1 

T 

s 

d 

t 

tr 

T 

s 

i 

1 

t 

i 2 

v 2 

T 

t 

s 

+ 

t 

_ 

Q 

r 

t 

r 

T 

v 1 

s 

i 

1 

t 

+ 

_ 

t 

i 1 

Ts 

t 

T 

s 

Ts 

1 

d 

tr 

T 

s 

:1 

Q 

r 

i 2 

t 

r 

T 

s 

t 

i 

Ts 

+ 

1 Ts 

_ 

v 2 

t 

Ts 


averaged switch model 

• Diode reverse recovery time affects conversion ratio 

• Stored charge leads to power loss, modeled by current sink 

Original 

converter 

v g 

(t) 

i L 

L 

(t) 

+ 

– 

i 1 

(t) 

+ 

v 1 

(t) 

i 2 

(t) 

+ 

v 2 

(t) 

C 

R 

+ 

v(t) 

– 

– 

– 

Averaged 

model 

v g 

(t) Ts 

i L 

(t) Ts 

L 

+ 

– 

t r 

i 1 

(t) Ts 

+(1–d) :1 

T s 

+ 

v 1 

(t) Ts 

i 2 

(t) Ts 

+ 

+ 

Q r 

v 2 

(t) Ts C R v(t) 

T Ts 

s 

– 

– 

–

P 

P 

out 

in 

VI 

2 

V I 

g 1 

I 

I 

2 

1 

Qr 

Ts 

D 

t 

T 

r 

1 1 D 

V 

s 

V 

g 

VI2 

V I 

g 

1 

1 

1 D 

tr 

D 

T 

s 

I 

2 

I 

2 

Qr 

T 

s 

1 

1 

tr 

1 D T 

s 

1 

1 

Qr 

I T 

load 

s 

Efficiency due to diode reverse recovery. Other switching loss mechanisms 

can be included using a similar procedure. 

• Basic idea of average-switch modeling: 

Define a switch network, containing all of the converter switching 

elements 

Average terminal waveforms over a switching period 

Use controlled sources with values equal to average of the switch 

network terminal waveforms 

The result is a large-signal, nonlinear, time-invariant model that can be 

inserted back into the converter network 

• The choices of the switch network and the independent terminal 

waveforms are not unique - there are many ways to construct averaged 

switch models 

• Averaged-switch model (suitable for circuit analysis or simulation) 

yields predictions of converter steady-state and low-frequency dynamic 

properties 

• Next: apply the averaged-switch modeling approach to other cases of 

interest.

• Averaged switch model in DCM 


characteristics and small-signal dynamics in DCM 

• Combined CCM/DCM averaged switch model 

• PSpice implementation of combined CCM/DCM models 

- ideal switches (ccm-dcm1) 

- ideal switches in converters with isolation transformer (ccm-dcm2) 


- comparison of transient simulation results in a SEPIC example 

using (1) switching circuit model and (2) averaged model 

- small-signal dynamic responses of a flyback converter operating in 

CCM or DCM 

- more converter examples using averaged-switch subcircuits 

Steady-state output voltage becomes strongly load-dependent 

Simpler dynamics: one pole and the RHP zero are moved to very high 

frequency, and can normally be ignored 

Traditionally, boost and buck-boost converters are designed to operate 

in DCM at full load 

All converters may operate in DCM at light load 

So we need equivalent circuits that model the steady-state and smallsignal 

ac models of converters operating in DCM 

The averaged switch approach yields an intuitive result that is relatively 

easy to solve

• Define switch terminal 

quantities v 1 

, i 1 

, v 2 

, i 2 

, as 

shown 

• Let us find the averaged 

quantities v 1 

, i 1 

, v 2 

, 

i 2 

, for operation in DCM, 

and determine the 

relations between them 

v g 


i 1 

i 2 

+ 

– 

v 1 

+ 

– 

– 

+ 

v L 

L 

– 

i L 

v 2 

+ 

C 

R 

+ 

v 

– 

i L 

(t) 

v L 

(t) 

v g 

v g 

L 

i pk 

v 

L 

0 

t 

i 1 

(t) 

v 1 

(t) 

Area q1 

i pk 

i 1 (t) Ts 

v g 

– v 

0 

v 1 (t) Ts 

0 

v g 

v 

i 2 

(t) 

i pk Area q 2 

v g 


i 1 

i 2 

+ 

– 

v 1 

+ 

– 

– 

+ 

v L 

L 

– 

i L 

v 2 

+ 

C 

R 

+ 

v 

– 

v 2 

(t) 

T s 

i 2 (t) Ts 

v g 

– v 

v 2 (t) Ts – v 

0 

d 1 

T s 

d 2 

T s 

d 3 

T s 

t

Peak inductor current: 

i pk = v g 

L d 1T s 

Average inductor voltage: 

v L (t) Ts 

= d 1 v g (t) 

Ts 

+ d 2 v(t) Ts 

+ d 3 0 

i 1 

(t) 

v 1 

(t) 

Area q1 

v 1 (t) Ts 

i pk 

i 1 (t) Ts 

v g 

– v 

v g 

In DCM, the diode switches off when the 

inductor current reaches zero. Hence, i(0) 

= i(T s 

) = 0, and the average inductor 

voltage is zero. This is true even during 

transients. 

v L (t) Ts 

= d 1 (t) v g (t) 

Ts 

+ d 2 (t) v(t) Ts 

= 0 

Solve for d 2 

: 

d 2 (t)=–d 1 (t) 

v g (t) 

Ts 

i 2 

(t) 

v 2 

(t) 

T s 

0 

i pk Area q 2 

i 2 (t) Ts 

v g 

– v 

v 2 (t) Ts – v 

0 

d 1 

T s 

d 2 

T s 

d 3 

T s 

t 

Average the v 1 

(t) waveform: 

i 1 

(t) 

Area q1 

i pk 

v 1 (t) Ts 

= d 1 (t) 0+d 2 (t) v g (t) 

Ts 

– v(t) Ts 

+ d 3 (t) v g (t) 

Ts 

i 1 (t) Ts 

Eliminate d 2 

and d 3 

: 

v 1 (t) Ts 

= v g (t) 

Ts 

v 1 

(t) 

v g 

– v 

v 1 (t) Ts 

v g 

Similar analysis for v 2 

(t) waveform leads to 

0 

i 2 

(t) 

v(t) Ts 

d 1 

T s 

T s 

t 

v 2 (t) Ts 

= d 1 (t) v g (t) 

Ts 

– v(t) Ts 

+ d 2 (t) 0+d 3 (t) – v(t) Ts 

i pk Area q 2 

=– v(t) Ts 

i 2 (t) Ts 

v 2 

(t) 

v g 

– v 

v 2 (t) Ts 

– v 

0 

d 2 

T s 

d 3 

T s

Average the i 1 

(t) waveform: 

i 1 (t) Ts 

= 1 T s 

t + T s 

i 1 (t)dt = q 1 

Note i 1 

(t) Ts 

is not equal to d i L 

(t) Ts 

! 

t 

The integral q 1 

is the area under the i 1 

(t) 

waveform during first subinterval. Use triangle 

area formula: 

q 1 = 

Eliminate i pk 

: 

i 1 (t) Ts 

= d 2 1(t) T s 

2L 

t 

Similar analysis for i 2 

(t) waveform leads to 

i 2 (t) Ts 

= d 2 2 

1(t) T v 1 (t) 

s 

Ts 

2L v 2 (t) Ts 

T s 

t + T s 

i 1 (t)dt = 1 2 d 1T s i pk 

v 1 (t) Ts 

i 1 

(t) 

v 1 

(t) 

i 2 

(t) 

v 2 

(t) 

Area q1 

v 1 (t) Ts 

0 

i pk 

i 1 (t) Ts 

v g 

– v 

v g 

T s 

i pk Area q 2 

i 2 (t) Ts 

v g 

– v 

v 2 (t) Ts – v 

0 

d 1 

T s 

d 2 

T s 

d 3 

T s 

t 

i 1 (t) Ts 

= d 2 1(t) T s 

2L 

v 1 (t) Ts 

i 1 (t) Ts 

R e 

(d 1 

) 

+ 

i 1 (t) Ts 

= v 1(t) Ts 

R e (d 1 ) 

R e (d 1 )= 

2L 

d 1 2 T s 

v 1 (t) Ts 

– 

Low-frequency components of input port waveforms 

obey Ohm’s law

i 2 (t) Ts 

= d 2 1(t) T s 

2L 

2 

v 1 (t) Ts 

v 2 (t) Ts 

i(t) 

+ 

i 2 (t) Ts 

v 2 (t) Ts 

= v 1(t) Ts 

R e (d 1 ) 

2 

= p(t) Ts 

p(t) 

v(t) 

– 

• Output port is a source of power p(t) 

• Power p(t) is independent of load characteristics 

• Power p(t) is dependent on (equal to) the power apparently 

consumed by the switch network input port 

i(t) 

+ 

i(t) 

v(t)i(t) = p(t) 

p(t) 

v(t) 

– 

v(t) 

• Must avoid open- and short-circuit 

connections of power sources 

• Power sink: negative p(t)

In a lossless two-port network without internal energy storage: 

instantaneous input power is equal to instantaneous output power 

In all but a small number of special cases, the instantaneous power 

throughput is dependent on the applied external source and load 

If the instantaneous power depends only on the external elements 

connected to one port, then the power is not dependent on the 

characteristics of the elements connected to the other port. The other 

port becomes a source of power, equal to the power flowing through 

the first port 

A power source (or power sink) element is obtained 

Series and parallel 

connection of power 

sources 

P 1 

P 2 

P 3 

P 1 

+ P 2 

+ P 3 

P 1 

Reflection of power 

source through a 

transformer 

P 1 

n 1 

: n 2

i 1 (t) Ts 

R e 

(d 1 

) 

+ 

p(t) Ts 

i 2 (t) Ts 

+ 

v 1 (t) Ts 

v 2 (t) Ts 

– 

– 

A two-port lossless network 

Input port obeys Ohm’s Law 

Power entering input port is transferred to output port 

Original circuit 


i 1 

i 2 

+ 

– 

v 1 

v 2 

+ 

v g 

+ 

– 

– 

+ 

v L 

L 

– 

i L 

+ 

C 

R 

v 

– 

Averaged model 

i 1 (t) Ts 

+ 

v 1 (t) Ts 

R e 

(d) 

p(t) Ts 

i 2 (t) Ts 

– 

v 2 (t) Ts 

+ 

v g (t) 

Ts 

+ 

– 

– 

L 

+ C R v(t) Ts 

–

Let 

L 

C 

short circuit 

open circuit 

I 1 

P 

V + 

g 

R e 

(D) 

R 

– 

+ 

V 

Converter input power: 

P = V 2 

g 

R e 

Converter output power: 

P = V 2 

R 

Equate and solve: 

P = V 2 

g 

= V 2 

R e R 

V 

V g 

= 

R 

Re 

– 

V 

= R is a general result, for any system that can 

V g Re be modeled as an LFR. 

For the buck-boost converter, we have 

R e (D)= 2L 

D 2 T s 

Eliminate R e 

: 

V 

V g 

=– 

D 2 T s R 

2L 

=– D K 

which agrees with the results of previous steady-state analyses.

• Determine averaged terminal waveforms of switch network 

• In each case, averaged transistor waveforms obey Ohm’s law, while 

averaged diode waveforms behave as dependent power source 

• Can simply replace transistor and diode with the averaged 

model as follows: 

i 1 

(t) 

+ 

i 2 

(t) 

+ 

+ 

p(t) Ts 

i 2 (t) Ts 

+ 

v 1 

(t) 

v 2 

(t) 

v 1 (t) Ts 

i 1 (t) Ts 

R e 

(d 1 

) 

v 2 (t) Ts 

– 

– 

– 

– 

Buck 

v g (t) 

Ts 

R e 

(d) 

L 

R e = 2L 

+ 

+ p(t) C R v(t) – Ts Ts 

p(t) Ts 

d 2 T s 

– 

Boost 

v g (t) 

Ts 

+ 

– 

L 

R e 

(d) 

C 

R 

+ 

v(t) Ts 

–

Cuk 

C 1 

L2 R e = 2 L 1||L 2 

d 2 T s 

p(t) Ts 

p(t) Ts 

L 1 

+ 

v g (t) + 

Ts 

R C – 2 

R v(t) e 

(d) 

Ts 

– 

SEPIC 

L C 1 1 

+ 

v g (t) + 

Ts 

R L C – 2 

2 

R v(t) e 

(d) 

Ts 

– 

Let L short circuit 

C open circuit 

Buck 

V g 

R e 

(D) 

+ P 

R 

– 

+ 

V 

– 

Boost 

+ 

V g 

+ R e 

(D) – 

P R 

V 

–

Converter M, CCM M, DCM 

Buck D 2 

1+ 1+4R e /R 

Boost 

Buck-boost, Cuk 

SEPIC 

1 

1–D 

– D 

1–D 

D 

1–D 

1+ 1+4R/R e 

2 

– R 

Re 

R 

R e 

I > I crit 

I 

for CCM 

for DCM 

I crit = 1–D 

D 

V g 

R e (D) 

Large-signal averaged model 

Perturb and linearize: let 

i 1 (t) Ts 

+ 

p(t) Ts 

i 2 (t) Ts 

+ 

d(t)=D + d(t) 

v 1 (t) Ts 

= V 1 + v 1 (t) 

v 1 (t) Ts 

R e 

(d) 

v 2 (t) Ts 

i 1 (t) Ts 

= I 1 + i 1 (t) 

v 2 (t) Ts 

= V 2 + v 2 (t) 

– 

– 

i 2 (t) Ts 

= I 2 + i 2 (t) 

d(t) 

i 1 (t) Ts 

= d 2 1(t) T s 

2L 

i 2 (t) Ts 

= d 2 1(t) T s 

2L 

v 1 (t) Ts 

i 1 = v 1 

r + j 1 d + g 1 v 2 

1 

2 

v 1 (t) Ts 

v 2 (t) Ts 

i 2 =– v 2 

r + j 2 d + g 2 v 1 

2

i 1 

(t) 

+ 

i 2 

(t) 

+ 

i 1 

(t) 

+ 

i 2 

(t) 

+ 

v 1 

(t) 

v 2 

(t) 

v 1 

(t) 

v 2 

(t) 

– 

– 

– 

– 

In any event, a small-signal two-port model is used, of the form 

i 1 

g 2 v 1 j 2 d r 2 

i 2 

v 2 

+ 

+ 

v 1 r 1 j 1 d g 1 v 2 

– 

– 

i 1 i 2 

– 

g 2 v 1 j 2 d r 2 v 2 

v + 

1 r – 

1 j 1 d g 1 v 2 

+ 

Switch type g 1 j 1 r 1 g 2 j 2 r 2 

Buck, 

Fig. 10.16(a) 

1 

R e 

2(1 – M)V 1 

DR e 

R e 

2–M 

MR e 

2(1 – M)V 1 

DMR e 

M 2 R e 

Boost, 

Fig. 10.16(b) 

1 

(M –1) 2 2MV (M –1) 2 2M –1 

R 1 

R 

e M e (M –1) 2 2V 

R 1 

e 

D(M –1)R e D(M –1)R e 

(M –1) 2 R e 

Buck-boost, 

Fig. 10.7(b) 

0 

2V 1 

DR e 

R e 

2M 

Re 

2V 1 

DMR e 

M 2 R e

When expressed in terms of R, L, C, and M (not D), the smallsignal 

transfer functions are the same in DCM as in CCM 

Hence, DCM boost and buck-boost converters exhibit two poles 

and one RHP zero in control-to-output transfer functions 

But, value of L is small in DCM. Hence 

RHP zero appears at high frequency, usually greater than 

switching frequency 

Pole due to inductor dynamics appears at high frequency, near 

to or greater than switching frequency 

So DCM buck, boost, and buck-boost converters exhibit 

essentially a single-pole response 

A simple approximation: let L 0 

Buck, boost, and buck-boost converter models all reduce to 

DCM switch network small-signal ac model 

+ 

v g 

+ 

– 

r 1 j 1 d g 1 v 2 g 2 v 1 j 2 d r 2 C R 

v 

– 

Transfer functions 

control-to-output 

line-to-output 

G vd (s)= v d 

vg =0= G d0 

1+ s p 

G vg (s)= v v g d =0 

= G g0 

1+ s p 

with 

G d0 = j 2 R || r 2 

p = 1 

R || r 2 C 

G g0 = g 2 R || r 2 = M

Converter G d0 G g0 p 

Buck 

2V 

D 

1–M 

2–M M 

2–M 

(1 – M)RC 

Boost 

2V 

D 

M –1 

2M –1 

M 

2M –1 

(M–1)RC 

Buck-boost 

V 

D 

M 

2 

RC 

R = 12 

i(t) L 

+ v L 

(t) – 

D 1 

i D 

(t) 

i C 

(t) 

+ 

L = 5 µH 

V g 

+ 

– 

Q 1 

C 

R 

v(t) 

C = 470 µF 

– 

f s = 100 kHz 

The output voltage is regulated to be V = 36 V. It is desired to determine G vd (s) at the 

operating point where the load current is I = 3 A and the dc input voltage is V g = 24 V.

P = IV– V g = 3A 36 V – 24 V =36W 

R e = V 2 

g (24 V)2 

= 

P 36 W =16 

D = 

2L 

R e T s 

= 

G d0 = 2V D 2M M –1 2(36 V) 

= 

–1 (0.25) 

f p = 

p 

2 = 2M –1 

2(5 H) 

(16 )(10 s) 

2 

(36 V) 

(24 V) –1 

2 (M–1)RC = 2 

2 

=0.25 

=72V 37 dBV 

(36 V) 

(24 V) –1 

(36 V) 

(24 V) –1 

=112Hz 

(36 V) 

(24 V) –1 (12 )(470 F) 

60 dBV 

|| G vd 

|| G vd 

40 dBV G d0 

37 dBV 

|| G vd 

|| 

f 

20 dBV 

p 

112 Hz 

0 dBV 

–20 dBV 

–40 dBV 

0˚ 

G vd 

–20 dB/decade 

0˚ 

–90˚ 

–180˚ 

–270˚ 

10 Hz 100 Hz 1 kHz 10 kHz 100 kHz 

f

• Observed high-frequency response due to inductor dynamics 

• Averaged-switch model derivation used: 

v L 

T s 

0 

which is consistent with the fact that in DCM the inductor current starts 

from zero and ends at zero in each switching cycle, even in transients 

• However, high-frequency dynamics due to the inductor indicates that 

the AC voltage across the inductor in the small-signal model is not zero 

• Model predictions at high frequencies are not quite correct 

• Corrected averaged models that include the inductor in the averaged 

switch model have recently been described 

See References: [Sun et. al. PESC’99], [Ben-Yaakov et.al. PESC’94] 

Objective: a general large-signal averaged-switch model 

• Valid in CCM and DCM 

• 5 terminals: 

transistor port (2 terminals) 

diode port (2 terminals) 

duty ratio input (1 terminal) 

• DCM/CCM boundary resolved within the model, based only on the 

terminal voltages/currents of the model 

• Spice compatible

i 1 (t) 

+ 

v 1 (t) 

1 

switch 

network 

3 

i 2 (t) 

+ 

v 2 (t) 

_ 

2 

4 

_ 


model 

i 1 

CCM i 2 

+ 

1 

3 

1-d + E 

– t G d 

d v 1-d 

v 2 

d i 1 

1 

+ 

v 2 

i 1 

+ 

1 

v 1 


model 

DCM 

R e (d) 

p(t) 

3 

i 2 

+ 

v 2 

_ 

2 

5 

duty 

d 

4 

i 1 

_ 


model 

CCM/DCM 

_ 

i 2 

2 

5 

duty 

d 

4 

_ 

_ 

1 

2 

? 

5 

duty 

d 

3 

4 

+ 

v 2 

_ 

+ 

1-u 

1 

+ 


model 

CCM/DCM 

3 

K 

1-u 

u i 1 

A 

4 

i 1 

v E t 

G d 

v 

– 

2 

u v 1 2 

, DCM 

_ 

2 

D 

S 

5 

duty 

d 

i 2 

+ 

_ 

u 

d 

2 

d, 

d 

2 

2Lf 

s 

i 

v 

1 

2 

CCM 

CCM/DCM boundary: 

u 

MAX 

d, 

d 

2 

d 

2 

2Lf 

s 

i 

v 

1 

2 

u = equivalent switch duty ratio

ccm-dcm1 

************************************************************************************** 

* MODEL: ccm-dcm1 

* Application: two-switch PWM converters, CCM or DCM 

* Limitations: ideal switches, no transformer 

************************************************************************************** 

* Parameters: 

* L=equivalent inductance (relevant for DCM) 

* fs=switching frequency 

************************************************************************************** 


************************************************************************************** 

.subckt ccm-dcm1 1 2 3 4 5 params: L=1 fs=1E6 

Et 1 2 value={(1-v(u))*v(3,4)/v(u)} 

Gd 4 3 value={(1-v(u))*i(Et)/v(u)} 

Ga 0 a value={MAX(i(Et),0)} 

Va a b 

Rdummy b 0 10 

Eu u 0 table {MAX(v(5), v(5)*v(5)/(v(5)*v(5)+2*L*fs*i(Va)/v(3,4)))} (0 0) (1 1) 

.ends 

************************************************************************************** 

i 1 

+ 

v 1-u 

1 

v2 

n u 

_ 

1 


model 

CCM/DCM 

D 

+ 

– 

S 

2 

E t 

G d 

5 

duty 

d 

i 2 

3 + 

K 

1-u i1 v 

n u 

2 

A 

4 

_ 

u 

d 

2 

d, 

d 

2 

2nLf 

s 

i 

v 

1 

2 

, 

CCM 

DCM 

CCM/DCM boundary: 

u 

MAX 

d, 

d 

2 

d 

2 

2nLf 

s 

i 

v 

1 

2 

u = equivalent switch duty ratio

ccm-dcm2 

* MODEL: ccm-dcm2 

* Application: two-switch PWM converters, CCM or DCM with (possibly) transformer 

* Limitations: ideal switches, no transformer 

**************************************************************************************** 

* Parameters: 

* L=equivalent inductance (relevant for DCM), referred to primary 



**************************************************************************************** 


**************************************************************************************** 

.subckt ccm-dcm2 1 2 3 4 5 params: L=1 fs=1E6 n=1 

Et 1 2 value={(1-v(u))*v(3,4)/v(u)/n} 

Gd 4 3 value={(1-v(u))*i(Et)/v(u)/n} 

Ga 0 a value={MAX(i(Et),0)} 

Va a b 

Rdummy b 0 10 

Eu u 0 table {MAX(v(5), v(5)*v(5)/(v(5)*v(5)+2*L*n*fs*i(Va)/v(3,4)))} (0 0) (1 1) 

.ends 

**************************************************************************************** 

• ccm-dcm1 (for non-isolated converters) and ccm-dcm2 (for converters 

that may include isolation transformer) are general, large-signal 

averaged-switch models (PSpice subcircuits) valid for both CCM and 

DCM 

• Can be applied to DC, AC, or Transient simulation of any two-switch 

PWM converter 

• Limitations: ideal switches, no losses are modeled, but the model can 

be refined further to include conduction losses 


• Comparison of Transient simulation results in a Sepic converter 

example using: 

– (1) switching circuit model 

– (2) ccm-dcm2 averaged switch model 

• AC simulation results for a flyback converter operating in CCM or 

DCM

L3 

22x 

R6 

22 

C3 

23 

24 

V 

21 

800u 

+ Vg2 

- 50V 

0.5 

100u 

Resr3 

0.2 

R4 

0.1 

L4 

100u 

C4 

100u 

R5 

100 

R11 

20 

S2 

+ + 

- - 

V4 

+ 

M1 

switch 

- 

IRF640 

R7 

10 

D1 

MUR820 

V3 

+ 

- 

Switching frequency 100kHz, duty ratio D=0.5 

ccm-dcm2 

+ 

- 

L1 

1 800u 

Vg 

50V 

2x 

R1 

0.5 

C1 

2 3 4 

100u 

ACMAG=1V 

DC=0.5V 

Resr1 

0.2 

+ 

- 

L2 

100u 

Vd 

R2 

0.1 

U6 

D 

1 4 A 

ccm-dcm2 

2 

S 

5 

duty 

3 K 

C2 

100u 

V 

R3 

100 

R10 

20 

S1 

+ + 

- - 

switch 

V4 

+ 

- 

Exactly the same PSpice circuit, except the MOSFET M1 and the 

diode D1 replaced by the ccm-dcm2 subcircuit, and pulsating 

gate drive V3 replaced by a duty-ratio voltage source Vd

80V 


(B) sepic-switch.dat 

V out 

start-up transient 

60V 

Switching model 

40V 

load transient 

20V 

0V 

0s 5ms 10ms 15ms 20ms 

V(24) V(4) 

Time 

Start-up and load transient response 

10A 

Diode current during load transient 

(B) sepic-switch.dat 

8A 

6A 

4A 

switching model 

2A 

0A 

averaged model 

-2A 

10.0ms 10.2ms 10.4ms 10.6ms 10.8ms 11.0ms 11.2ms 11.4ms 

I(D1) I(X_U6.Gd) 

Time 

Details of the diode current waveform around the load transient

ccm-dcm2 

Vg 

48V 

+ 

T1 

1 1 

Lm=50u 

n=0.25 Lm 

AC=1 

0.25 

+ 

- 

1:n 

** 

- 2 

4 

R2 transformer 

3 

0.2 

U1 

D 

2 1 4 A 

L=50u 

fs=100K 

ccm-dcm2 

n=0.25 2 3 

S 5 K 

duty 

Vd 

3 

4 

PARAMETERS: 

Rload 2 

V 

C1 

500uF 

R1 

{Rload} 

CCM for Rload=1 Ohm, DCM for Rload=2 Ohm 

ccm-dcm2 

(C) flyback-ccm-dcm2.dat 

50 

Magnitude response, control-to-output v/d 

R load = 1, CCM 

0 

R load = 2, DCM 

-50 

0d 

DB(V(4)) 

R load = 1, CCM 

-100d 

R load = 2, DCM 

Phase response, control-to-output v/d 

-200d 


P(V(4)) 

Frequency 

Frequency responses generated by PSpice AC analyses

transformer 

+ 

- 

Vg 

2 

Lm 

1 

1:n 

** 

Watkins-Johnson converter 

3 

4 

transformer 

+ 

- 

Vg 

2 

4 

Lm 

1 

1:n 

** 

3 

1 D 

2 S 

ccm-dcm2 

A 

4 

5 

3 

K 

duty 

+ 

- 

Vd 

Pspice averaged circuit model 

using ccm-dcm2 

averaged-switch subcircuit 

1 1:n 3 

Vg ** 

+ 

- 

Lm 

2 

4 

transformer 

1 1:n 3 

Vg ** 

+ 

- 

Lm 

2 

4 

transformer 

U2 

D 

1 4 A 

ccm-dcm2 

2 

S 

5 

duty 

3 K 

Cuk converter with 

isolation transformer 

PSpice averaged circuit model 

using ccm-dcm2 

averaged-switch subcircuit

• Averaged switch model for current-programmed mode (CPM) in 

CCM 

• Steady-state and simple AC model in CCM 

• Averaged switch model for CPM in DCM 

• Steady-state and small-signal AC model in DCM 

• Large-signal averaged CCM/DCM model for current-mode 

controller 

• PSpice implementation of the averaged CPM controller model 

• Application examples 

- Buck converter with current-programmed mode controller 

v g (t) 

Buck converter 

i s (t) 

Q 1 

+ 

– D 1 

L 

i L (t) 

C 

+ 

v(t) 

R 

The peak transistor current 

replaces the duty cycle as the 

converter control input. 

– 

Measure 

switch 

current 

i s (t)R f 

i c (t)R f 

R f 

i s (t) 

Clock 

+ 

– 

Analog 

comparator 

0 

T s 

S Q 

R 

Latch 

m 1 

Switch 

current 

i s (t) 

Control signal 

i c (t) 

Control 

input 

Current-programmed controller 

0 dT s T s 

Transistor 

status: on 

off 

t 

Compensator 

– + 

v(t) 

Clock turns 

transistor on 

Comparator turns 

transistor off 

v ref 

Conventional output voltage controller

i L (t) Ts 

= i c (t) 

• Neglects switching ripple and artificial ramp (slope compensation) 

• Yields physical insight and simple first-order model 

• Accurate when converter operates well into CCM (so that switching 

ripple is small) and when the magnitude of the artificial ramp is not 

too large 

• Well-accepted by practicing engineers 

• Resulting small-signal relation: 

i L (s) 

i c (s) 

Buck converter example 

v g 

(t) 

i 1 

(t) 

i 2 

(t) 

L 

+ 

– 

v 1 

(t) 

v 2 

(t) 

+ 

+ 

i L 

(t) 

C 

R 

+ 

v(t) 

– 

– 

– 


Averaged terminal waveforms, 

CCM: 

The simple approximation: 

v 2 (t) Ts 

= d(t) v 1 (t) Ts 

i 2 (t) Ts 

i c (t) Ts 

i 1 (t) Ts 

= d(t) i 2 (t) Ts

v 2 (t) Ts 

= d(t) v 1 (t) Ts i 2 (t) Ts 

i c (t) Ts 

i 1 (t) Ts 

= d(t) i 2 (t) Ts 

Eliminate duty cycle: 

i 1 (t) Ts 

= d(t) i c (t) Ts 

= v 2(t) Ts 

v 1 (t) Ts 

i c (t) Ts 

i 1 (t) Ts 

v 1 (t) Ts 

= i c (t) Ts 

v 2 (t) Ts 

= p(t) Ts 

So: 

• Output port is a current source 

• Input port is a dependent power sink 

v g 

(t) Ts 

i 1 

(t) Ts 

i 2 

(t) Ts 

L 

+ 

– 

v 1 

(t) Ts 

i c 

(t) Ts 

v 2 

(t) Ts 

+ 

+ 

p(t) Ts 

C 

i L 

(t) Ts 

R 

+ 

v(t) Ts 

– 


– 

–

Boost 

+ 

– 

L 

v g 

(t) Ts 

i L 

(t) Ts 


i c 

(t) Ts 

p(t) Ts 

C 

R 

+ 

v(t) Ts 

– 


Buck-boost 

p(t) Ts 

i c 

(t) Ts 

+ 

v g 

(t) Ts 

C 

R 

v(t) Ts 

+ 

– 

L 

– 

i L 

(t) Ts 

Let 

v 1 (t) Ts 

= V 1 + v 1 (t) 

i 1 (t) Ts 

= I 1 + i 1 (t) 

v 2 (t) Ts 

= V 2 + v 2 (t) 

i 2 (t) Ts 

= I 2 + i 2 (t) 

i c (t) Ts 

= I c + i c (t) 

Resulting input port equation: 

V 1 + v 1 (t) I 1 + i 1 (t) = I c + i c (t) V 2 + v 2 (t) 

Small-signal result: 

i 1 (t)=i c (t) V 2 

V 1 

+ v 2 (t) I c 

V 1 

– v 1 (t) I 1 

V 1 

Output port equation: 

î 2 

= î c

i 1 i L 

2 

+ 

+ 

+ 

v + v V 

g 

i 2 

C R 

– – V I 

1 1 

c 

v c 

2 i v 

V c 

2 v 

1 

V 1 

I 1 

– 

Switch network small-signal ac model 

– 

– 

i 1 (t)=i c (t) V 2 

V 1 

+ v 2 (t) I c 

V 1 

– v 1 (t) I 1 

V 1 

L 

i g 

i L 

v g 

+ 

– i – D 2 

D 

c D 1+ sL v i 

R R R c 

C R 

+ 

v 

G vc (s)= v(s) = R || 1 

i c (s) sC 

vg =0 

G vg (s)= v(s) =0 

v g (s) 

i c =0 

–

v g 

+ 

– 

i g 

+ 

r 1 

f 1 (s) i c g 1 v g 2 v g 

f 2 (s) i c r 2 C R v 

– 

Converter g 1 f 1 r 1 g 2 f 2 r 2 

Buck 

D 

R 

D 1+ sL R 

– R D 2 0 1 

Boost 0 1 

1 

D'R D' 1 – sL 

D' 2 R 

R 

Buck-boost – D R D 1+ sL 

D'R 

– D'R 

D 2 

– D2 

D'R 

– D' 1 – sDL 

D' 2 R 

R 

D 

• Again, use averaged switch modeling approach 

• Result: simply replace 

Transistor by power sink 

Diode by power source 

• Inductor dynamics appear at high frequency, near to or greater 

than the switching frequency 

• Small-signal transfer functions contain a single low frequency pole 

• DCM CPM boost and buck-boost are stable without artificial ramp 

• DCM CPM buck without artificial ramp is stable for D < 2/3. A 

small artificial ramp m a 

0.086m 2 

leads to stability for all D.

i L 

(t) 

i 1 

(t) 

+ 

v 1 

(t) 


i 2 

(t) 

– 

v 2 

(t) 

+ 

i pk 

v g 

(t) 

+ 

– 

– 

L 

i L 

(t) 

+ 

C 

R 

v(t) 

– 

v L 

(t) 

m 1 

= v 1 T s 

L 

v 1 (t) Ts 

m 2 = v 2 T s 

L 

0 

t 

i c 

– m a 

m 1 

0 

v 2 (t) Ts 

i pk = m 1 d 1 T s 

i L 

(t) 

m 1 = v 1(t) Ts 

L 

i c 

– m a 

i pk 

i c = i pk + m a d 1 T s 

= m 1 + m a d 1 T s 

v L 

(t) 

= v 1 T s 

L 

v 1 (t) Ts 

m 2 = v 2 T s 

L 

0 

t 

d 1 (t)= 

i c (t) 

0 

m 1 + m a 

T s 

v 2 (t) Ts

i 1 (t) Ts 

= 1 t + T s 

i 1 ( )d = q 1 

T s t 

T s 

i 1 (t) Ts 

= 1 2 i pk(t)d 1 (t) 

i 1 

(t) 

Area q1 

i pk 

i 1 (t) Ts 

i 1 (t) Ts 

= 1 2 m 1d 1 2 (t)T s 

i 1 (t) Ts 

= 

v 1 (t) Ts 

1 

2 Li 2 c f s 

1+ m a 

m 1 

2 

i 2 

(t) 

i 2 (t) Ts 

i pk Area q 2 

i 1 (t) Ts 

v 1 (t) Ts 

= 

1 

2 Li 2 c f s 

1+ m a 

m 1 

2 = p(t) T s 

t 

d 1 

T s 

d 2 

T s 

d 3 

T s 

T s 

• Averaged transistor waveforms obey a power sink characteristic 

• During first subinterval, energy is transferred from input voltage 

source, through transistor, to inductor, equal to 

W = 1 2 Li 2 

pk 

This energy transfer process accounts for power flow equal to 

p(t) Ts 

= Wf s = 1 2 Li 2 pk f s 

which is equal to the power sink expression of the previous slide.

i 2 (t) Ts 

= 1 t + T s 

i 

T 

2 ( )d = q 2 

s t 

T s 

i 1 

(t) 

Area q1 

i pk 

q 2 = 1 2 i pkd 2 T s 

d 2 (t)=d 1 (t) 

v 1 (t) Ts 

i 1 (t) Ts 

v 2 (t) Ts 

i 2 

(t) 

i 2 (t) Ts 

= 

p(t) T s 

v 2 (t) Ts 

i pk Area q 2 

i 2 (t) Ts 

v 2 (t) Ts 

= 

1 

2 Li 2 c(t) f s 

1+ m a 

m 1 

2 = p(t) T s 

T s 

i 2 (t) Ts 

d 1 

T s 

d 2 

T s 

d 3 

T s 

t 

• Averaged diode waveforms obey a power sink characteristic 

• During second subinterval, all stored energy in inductor is 

transferred, through diode, to load 

• Hence, in averaged model, diode becomes a power source, 

having value equal to the power consumed by the transistor 

power sink element

i 1 (t) Ts 

i 2 (t) Ts 

+ 

v 1 (t) Ts 

p(t) Ts 

– 

v 2 (t) Ts 

+ 

v g (t) 

Ts 

+ 

– 

– 

L 

+ C R v(t) Ts 

– 

P 

+ 

V g 

+ 

– R 

V 

– 

Solution 

V 2 

R = P 

P = 

1 

2 LI 2 c(t) f s 

1+ M 2 

a 

M 1 

V= PR = I c 

RLf s 

2 1+ M a 

M 1 

2 

for a resistive load

Buck 

v g (t) 

Ts 

L 

+ p(t) 

– 

Ts 

C 

R 

+ 

v(t) Ts 

– 

Boost 

v g (t) 

Ts 

+ 

– 

L 

p(t) Ts 

C 

R 

+ 

v(t) Ts 

– 

Converter M I crit 

Stability range 

when m a = 0 

Buck 

P load – P 

P load 

1 

2 I c – Mm a T s 

0 M < 2 3 

Boost P load 

P load – P 

I c – M M 

–1m 

a T s 

2 M 

0 D 1 

Buck-boost 

Depends on load characteristic: 

P load = P 

I c – 

M 

M –1 

m a T s 

2 M –1 

0 D 1 

I > I crit 

for CCM 

I 

for DCM

Buck 

+ 

+ 

L 

i L 

+ 

v g 

i 1 

g 2 v 1 f 2 i c r 2 

i 2 

v 2 

+ 

– 

v 1 r 1 f 1 i c 

g 1 v 2 

C 

R 

v 

– 

– 

– 

Boost 

i 

L 

L 

+ 

+ 

+ 

v g 

i 1 

g 2 v 1 f 2 i c r 2 

i 2 

v 2 

+ 

– 

v 1 r 1 f 1 i c g 1 v 2 

C 

R 

v 

– 

– 

– 

i 1 

g 2 v 1 f 2 i c r 2 

i 2 

v 2 

+ 

– 

v g 

v 1 r 1 f 1 i c g 1 v 2 

+ – 

– 

+ 

C 

R 

+ 

v 

L 

– 

i L

Converter g 1 f 1 r 1 

Buck 

1 

R 

M 2 

1–M 

1– m a 

m 1 

2 I 1 

I c – R 1–M 

1+ m a 

m 1 

M 2 

1+ m a 

m 1 

1– m a 

m 1 

Boost 

– 1 R 

M 

M –1 

2 I I c 

R 

M 2 2–M 

M –1 + 

2 m a 

m 1 

1+ m a 

m 1 

Buck-boost 0 2 I 1 

I c 

– R 

M 2 

1+ m a 

m 1 

1– m a 

m 1 

Converter g 2 f 2 r 2 

Buck 

1 

R 

M 

1–M 

m a 

m 1 

2–M – M 

2 I I 

1–M 1+ m a 

c 

m 1 

R 

1+ m a 

1–2M + m a 

m 1 

m 1 

Boost 

1 

R 

M 

M –1 

2 I 2 

R M –1 

I c 

M 

Buck-boost 

2M 

R 

m a 

m 2 I 2 

1 

1+ m I c 

a 

m 1 

R

Buck, boost, buck-boost all become 

+ 

v g 

+ 

– 

r 1 f 1 i c 

g 1 v g 2 v g f 2 i c r 2 C R 

v 

– 

G vc (s)= v i c v g =0= G c0 

1+ s p 

G vg (s)= v v g ic =0 

= G g0 

1+ s p 

G c0 = f 2 R || r 2 

p = 

1 

R || r 2 C 

G g0 = g 2 R || r 2 

i 

pk 

i 

c 

m 

a 

dT 

s 

i c 

-m a 

i pk 

i 

m L 

(t) 

-m 2 

1 

t 

0 dT s 

T s 

d 2 

T s 

=(1-d)T s 

i c 

-m a 

i pk 

i L 

(t) 

m 1 

-m 2 

t 

0 dT s 

(d+d 2 

)T s 

T s 

d 2 

T s 

i 

L 

T 

s 

d 

i 

pk 

m dT 

2 

d 

i 

m2d2T 

2 

1 s 

s 

2 pk 

d 

2 

1 d 

i 

pk 

m T 

2 

s 

CCM 

DCM 

CCM/DCM: 

d 

MIN 

d 

2 

1 , 

i 

pk 

m T 

2 

s

Inputs: 

ic 

m1 

m2 

i L 

T s 

d 

MIN 

d 

2 

1 , 

i 

c 

madT 

m T 

2 

s 

s 

Model: 

d 2 

d 

2i 

c 

d 

d 

m dT 

1 

s 

2 

2 i 

2m 

a 

L 

d 

T 

s 

d 

m d 

2 

2 

T 

s 

2 

2 

T 

s 

Output: duty ratio 

d 

********************************************************** 

* MODEL: CPM 

* Current-Programmed-Mode CCM/DCM controller model. 

* All parameters and inputs are referred to 

* the primary side. 

********************************************************** 

* Parameters: 

* L=equivalent inductance, referred to primary 


* va=amplitude of the artificial ramp, va=Rf*ma/fs 

* Rf=equivalent current-sense resistance 

********************************************************** 

* Nodes: 

* ctr: control input, v(ctr)=Rf*ic 

* current: sensed average inductor current v(current)=Rf*iL 

* 1: voltage across L in interval 1, slope m1=v(1)/L 

* 2: (-) voltage across L in interval 2, slope m2=v(2)/L 

* d: duty ratio (output of the controller) 

********************************************************** 

.subckt CPM ctr current 1 2 d 

+params: L=100e-6 fs=1e5 va=0.5 Rf=0.1 

* 

* generate d2 for CCM/DCM 

Ed2 d2 0 table 

+ {MIN( 

+ L*fs*(v(ctr)-va*v(d))/Rf/(v(2)), 

+ 1-v(d) 

+ )} (0,0) (1,1) 

* 

Em1 m1 0 value={Rf*v(1)/L/fs} 

Em2 m2 0 value={Rf*v(2)/L/fs} 

* 

* generate duty-ratio d (valid CCM and DCM operation) 

* 

Eduty d 0 table 

+ { 

+ 2*(v(ctr)*(v(d)+v(d2)) 

+ -v(current)-v(m2)*v(d2)*v(d2)/2) 

+ /(v(m1)*v(d)+2*va*(v(d)+v(d2))) 

+ } (0.01,0.01) (0.99,0.99) 

* 

.ends ; end of subcircuit CPM 

**********************************************************

• Demonstrate how CCM/DCM averaged-switch model can be used 

together with CCM/DCM averaged model of the current-mode controller 

• Use DC sweep simulation to show steady-state characteristics 

including operation in DCM or CCM 

• Use AC simulation to show control-to-output responses compared for 

duty-ratio control and current-mode control, in DCM or CCM 

• Use parametric sweep simulation to find the amplitude of the artificial 

ramp to minimize input-to-output audio-susceptibility 

• Specifications: 

• Input V g 

= 28V, output V = 5-20V, 0.5-2A 

• Switching frequency f s 

=100kHz, inductance L = 35uH 

• Equivalent current-sense resistance R f 

= 1 

• Artificial-ramp amplitude V a 

= 0-3V 

U2 

L1 R1 

D 

1 4 A 

2x 3 

1 

35uH 0.05 

L=35uH 

ccm-dcm1 

VDB 

5.315V 

fs=100K 2 

S 

DC=28V Vg 

5 

3 K 

+ 

- 

C1 R2 

100u 10 

duty 

d 

177.09mV 

DC=2V 

Vc 

+ 

- 

ctr 

E2 

IN+ OUT+ 

IN- 

OUT- 

Vc 

Rf iL 

CTR 

CURRENT 

1 

U1 

CPM 

2 

D duty L=35uH 

fs=100kHz 

va={Va} 

Rf=1 

PARAMETERS: 

Va 1 

531.52mV 

E3 

V1 

EVALUE 

i(L1) 

IN+ OUT+ 

IN- OUT- 

V2 

IN+ OUT+ 

IN- OUT- 

E4 

EVALUE 

V(1)-V(2x) 

EVALUE 

V(2x) 

Example: Cpm-buck

1.0V 

(E) cpm-buck.dat 

1-d 

0.8V 

d2 

DCM 

CCM 

0.6V 

0.4V 

0.2V 

u 

d 

0V 

0.5V 1.0V 1.5V 2.0V 2.5V 3.0V 

V(d) 1-V(d) V(Xs.u) V(Xcpm.d2) Vc 

Duty ratio d, equivalent duty ratio u, and diode conduction 

interval d 2 

as functions of the control input V c 

3.0 

(F) cpm-buck.dat 

2.5 

2.0 

Vc=Rf*Ic 

1.5 

1.0 

iL 

0.5 

0 

0.5V 1.0V 1.5V 2.0V 2.5V 3.0V 

I(L1) v(ctr) 

Vc 

Average inductor current iL as a function of the control input V c

100 

(H) cpm-buck.dat 

50 

0 

MAGNITUDE 

PHASE 

v/d 

v/vc 

-50 

-100 

Vc=2.0, CCM 

v/vc 

-150 

v/d 

-200 


DB(V(3)) DB(V(3)/v(d)) P(V(3)) P(V(3)/v(d)) Frequency 

Control-to-output frequency responses for duty-ratio control (v/d) 

and current-mode control (v/v c 

). The converter operates in CCM. 

50 

(H) cpm-buck.dat 

MAGNITUDE 

v/d 

0 

PHASE 

v/vc 

-50 

Vc=1.5, DCM 

v/vc 

-100 

v/d 

-150 


DB(V(3)) DB(V(3)/v(d)) P(V(3)) P(V(3)/v(d)) Frequency 

Control-to-output frequency responses for duty-ratio control (v/d) 

and current-mode control (v/v c 

). The converter operates in DCM.

-20 

(A) cpm-buck.dat 

Audio-susceptibility v/v g as a function of the artificial-ramp amplitude V a 

-30 

-40 

-50 

-60 

Va=0.8, v/vg(0) = -62.848dB 

-70 

0 0.5 1.0 1.5 2.0 

VDB(3) 

Va 

Parametric sweep used to determine amplitude of the artificial ramp 

V a 

to minimize input-to-output response (audio-susceptibility) v/v g 

. 

• Ideal rectifier 

• Averaged model obtained by averaging over switching period 

• Averaged model obtained by averaging over line period 


- Power factor corrector based on boost converter operating in DCM 

- Power factor corrector based on SEPIC with nonlinear-carrier control

It is desired that the rectifier present a resistive load to the ac power 

system. This leads to 

• unity power factor 

• ac line current has same waveshape as voltage 

i ac (t)= v ac(t) 

R e 

+ 

i ac 

(t) 

R e 

is called the emulated resistance 

v ac 

(t) 

R e 

– 

P av = 

V 2 

ac,rms 

R e (v control ) 

+ 

i ac 

(t) 

Power apparently “consumed” by R e 

is actually transferred to rectifier dc 

output port. To control the amount 

of output power, it must be possible 

to adjust the value of R e 

. 

v ac 

(t) 

– 

R e 

(v control 

) 

v control

The ideal rectifier is 

lossless and contains no 

internal energy storage. 

Hence, the 

instantaneous input 

power equals the 

instantaneous output 

power. Since the 

instantaneous power is 

independent of the dc 

load characteristics, the 

output port obeys a 

power source 

characteristic. 

+ 

v ac 

(t) 

– 

i ac 

(t) 

ac 

input 

p(t)= 

R e 

(v control 

) 

v control 

v 2 

ac (t) 

R e (v control (t)) 

Ideal rectifier (LFR) 

p(t) = v ac 2 /R e 

i(t) 

+ 

v(t) 

– 

dc 

output 

v(t)i(t)=p(t)= v 2 

ac(t) 

R e 

Defining equations of the 

ideal rectifier: 

i ac (t)= 

v(t)i(t)=p(t) 

p(t)= 

v ac (t) 

R e (v control ) 

v 2 

ac (t) 


When connected to a 

resistive load of value R, the 

input and output rms voltages 

and currents are related as 

follows: 

V rms 

V ac,rms 

= 

R 

Re 

I ac,rms 

I rms 

= R 

Re 

A switch network that is capable of satisfying the above (averaged) 

equations can be employed in low-harmonic rectifier applications

i g 

(t) 


i 2 

(t) 

p load 

(t) = VI = P load 

v ac 

(t) 

i ac 

(t) 

+ 

v g 

(t) 

R e 

p ac 

(t) Ts 

C 

+ 

v C 

(t) 

Dc–dc 

converter 

+ 

v(t) 

i(t) 

load 

Energy storage capacitor 

voltage v C 

(t) must be 

independent of input and 

output voltage waveforms, so 

that it can vary according to 

= d 1 2 Cv 2 

C(t) 

dt 

– 

= p ac (t)–p load (t) 

– 

Energy storage 

capacitor 

This system is capable of 

• Wide-bandwidth control of 

output voltage 

• Wide-bandwidth control of 

input current waveform 

• Internal independent energy 

storage 

– 

i g 

(t) Ts 

i 2 

(t) Ts 

p(t) + 

Ts 

v g 

(t) + 

Ts – 

R e 

(v control 

) 

C v(t) Ts 

v control 

Load 


ac 

input 

dc 

output 

– 

Ideal rectifier model, assuming that inner wide-bandwidth loop 

operates ideally 

High-frequency switching harmonics are removed via averaging 

Ac line-frequency harmonics are included in model 

Nonlinear and time-varying

If the input voltage is 

v g (t)= 2v g,rms sin t 

v control 

i g 

(t) Ts 

Ideal rectifier (LFR) i 2 

(t) Ts 

v g 

(t) + 

Ts – 

R e 

(v control 

) 

C v(t) Ts 

p(t) Ts 

+ 

Load 

Then the 

instantaneous power 

is: 

p(t) Ts 

= 

2 

v g (t) 2 

Ts 

R e (v control (t)) = v g,rms 


ac 

input 

1–cos 2 t 

which contains a constant term plus a secondharmonic 

term 

dc 

output 

– 

i 2 

(t) Ts 

+ 

– V 2 

g,rms 

cos 

R 2 2 t 

e 

2 

V g,rms 

R e 

C 

v(t) Ts 

Load 

– 

Rectifier output port 

The second-harmonic variation in power leads to second-harmonic 

variations in the output voltage and current

v(t) 

v(t) Ts 

v(t) T2L 

t 

T 2L = 1 2 

2 = 

+ 

i 2 

(t) T2L 

2 

V g,rms 

R e 

C 

v(t) T2L 

Load 

– 


Time invariant model 

Power source is nonlinear

The averaged model predicts that the rectifier output current is 

i 2 (t) T2L 

= 

p(t) T 2L 

v(t) T2L 

= 

2 

v g,rms (t) 

R e (v control (t)) v(t) T2L 

= f v g,rms (t), v(t) T2L 

, v control (t)) 

Let 

v(t) T2L 

= V + v(t) 

i 2 (t) T2L 

= I 2 + i 2 (t) 

v g,rms = V g,rms + v g,rms (t) 

v control (t)=V control + v control (t) 

with 

V >> v(t) 

I 2 >> i 2 (t) 

V g,rms >> v g,rms (t) 

V control >> v control (t) 

where 

I 2 + i 2 (t)=g 2 v g,rms (t)+j 2 v(t)– v control(t) 

r 2 

g 2 = 

df v g,rms , V, V control ) 

dv g,rms 

v g,rms = V g,rms 

= 2 

R e (V control ) 

V g,rms 

V 

– 1 r 2 

= 

df V g,rms , v T2L 

, V control ) 

dv T2L 

v T2L 

= V 

=– I 2 

V 

j 2 = 

df V g,rms , V, v control ) 

2 

V g,rms 

=– 

dv control VR 2 e (V control ) 

v control = V control 

dR e (v control ) 

dv control 

v control = V control

i 2 

+ 

g 2 v g,rms 

j 2 v control C v R 

r 2 


Predicted transfer functions 

Control-to-output 

v(s) 

v control (s) = j 2 R||r 2 

1 

1+sC R||r 2 

– 

Line-to-output 

v(s) 

v g,rms (s) = g 2 R||r 2 

1 

1+sC R||r 2 

i g 

(t) 

i 2 

(t) 

p load 

(t) = VI = P load 

i ac 

(t) 

+ 

p ac 

(t) Ts 

+ 

+ 

i(t) 

v ac 

(t) 

v g 

(t) 

R e 

C 

v C 

(t) 

P load 

V 

+ 

– 

v(t) 

load 

– 

– 

– 


Energy storage 

capacitor 

Dc-dc 

converter 

Rectifier and dc-dc converter operate with same average power 

Incremental resistance R of constant power load is negative, and is 

R =– V 2 

P av 

which is equal in magnitude and opposite in polarity to rectifier 

incremental output resistance r 2 

for all controllers except NLC

When r 2 

= –R, the parallel combination r 2 

|| R becomes equal to zero. 

The small-signal transfer functions then reduce to 

v(s) 

v control (s) = j 2 

sC 

v(s) 

v g,rms (s) = g 2 

sC 

Objectives: 

• Example of how large-signal averaged-switch model can be used for 

analysis and simulation of a power-factor corrector 

• Show examples of averaged pulse-width modulator model, and 

implementation of closed-loop control 

• Use transient simulation to study start-up transient response of the PFC 

and harmonic distortion of the AC line current in steady state 

Specifications: 

• Input: 120Vrms, 50Hz. Output: 300VDC, 100W 

• Switching frequency: 100kHz

- 

L 

L 

 

v line 

i line 

+ 

i i line + 

i + + 

+ + 

g = 

d 

i i 

v g = 

s 

 

line 

v g v V v co 

o 

g R e p(t) v co V 

C o 

C o 

_ 

_ _ 

_ 

_ _ 

Switching circuit model 

Averaged circuit model (in DCM) 

Boost converter operates in DCM at constant duty ratio, constant frequency 

i 

g 

i 

s 

T 

s 

i 

d 

T 

s 

v 

R 

g 

e 

p 

V v 

g 

v 

R 

g 

e 

R ( V 

e 

v 

2 

g 

v 

g 

) 

i 

g 

v 

R 

g 

e 

1 

1 

v 

g 

V 

2L 

D T 

Re 

2 

s 

Line current distrortion due 

to this term 

R2 

L1 

output 

PARAMETERS: 

Rload 900 

Vac 

VAMPL=170 

FREQ=50 

D1 

+ 

- 

diode 

D2 

0.2 

diode 

200uH U1 

D 

1 4 A 

fs=100KHz ccm-dcm1 

L=200uH 

2 3 

S 5 K 

duty 

C1 

150uF 

R1 

{Rload} 

V 

Averaged 

model of 

the boost 

rectifier 

D3 

diode 

D4 

diode 

d 

0.9 

0.1 

0.5 

Voffset 

+ 

2V 

PWM 

m 

12V 

+ 

VCC - 

1 

R6 

4 

U2A + 3 

V+ 

LM324 

V- 

11 

- 2 

R5 3.3K C2 1u 

10K 

5V 

Vref 

+ 

- 

R3 

600K 

R4 

10K 

Averaged PWM model: d=v m 

/V M 

=0.5v m 

, 

D min 

=0.1, D max 

=0.9 limits 

Closed-loop output 

voltage control

(A) dcm-boost-rectifier-closed-loop.dat 

0.8 

Duty ratio d 

0.4 

100W load 

50W load 

0 

400V 

V(d) 

50W load 

200V 

100W load 

0V 

0s 50ms 100ms 150ms 200ms 

V(output) 

Time 

Start-up transient response for full load and 50% load 

1.5A 

1.0A 


100W load 

1st harmonic: 0.87A 

3rd harmonic: 0.14A (16.4%) 

THD: 16.4% 

0.5A 

0A 

-0.5A 

50W load 

1st harmonic: 0.48A 

3rd harmonic: 0.08A (16.2%) 

THD: 16.2% 

-1.0A 

-1.5A 

180ms 185ms 190ms 195ms 200ms 

I(Vac) 

Time 

AC line current waveforms at full load and 50% load

2.0A 


0A 

-2.0A 

50W load 

100W load 

150W load 

-4.0A 

-6.0A 

Converter operates in CCM 

-8.0A 

500ms 505ms 510ms 515ms 520ms 

I(Vac) 

Time 

AC line current waveforms at full load (100W), 

50% load, and 150% load 

136 turns #18 

i s 

1uF 

2400uF 

IRF840 

53 turns 53 turns 

#18 #18 

AC line 

voltage 

120V, 60Hz 

R s i s 

Nonlinear-Carrier 

Controller 

Magnetics 1F19 UU 

v m 

voltage-loop 

– 

+ 

V ref 

error amplifier 

• Active current shaping using Nonlinear Carrier Control method 

• Sepic converter has integrated magnetics designed for zero switching 

ripple in the AC line current 

• Specifications: 

• Input: 90-120Vrms, 60Hz. Output: 48VDC, 200W 

• Switching frequency: 90kHz

Objectives: 

• Show application of the CCM/DCM averaged-switch model in powerfactor 

correctors with active current shaping and closed-loop output 

voltage control 

• Show average model implementation of a nonlinear pulse-width 

modulator (NLC controller) 

• Compare average model predictions to experimental results: 

• AC line current waveshapes 

• Start-up and load transient responses 

switch 

drive 

d 

switch 

current sensor 

Q 

Q 

R 

S 

+ 

– 

vc (t) 

v q (t) = R s 

NLC generator 

v c (t) = v m f(t/T s ) 

v m 

i s [5A/div] 

clock 

T 

t 

s 

f ( t / Ts 

) vm 

1 

t 

T 

s 

R 

s 

i 

s 

T 

s 

v 

m 

1 

d 

d 

v c 

v q 

1 

d 

d 

i g 

i s 

v 

g 

V 

T s 

Ideal current shaping 

i 

g 

vm 

R V 

s 

v 

g 

c(t) 

d 

R 

s 

v 

i 

s 

m 

T 

s 

v 

m 

NLC Controller Model

- 

- 

Coupledinductor 

model 

D3 

diode 

+ 

Vac 

- 

VAMPL=170 

D1 

diode 

n=0.94 

D4 

diode 

D2 

diode 

0 

0 

2 1:n 4 

EVALUE 

V(m)/(Rs*I(Vsense)+V(m)) 

NLC controller 

950uH 

L-13-23 n=1 

TX1 

C1 T1 Lm=180uH 

1 1:n 3 

** 

1uF 

+ 

Lm 

- Vsense 

2 

4 

0 transformer 

1 

* * 

3 

U1 

D 

1 4 A 

L=180uH ccm-dcm1 

fs=90kHz 

2 3 

S 5 K 

0 

OUT+ 

E1 

IN+ 

OUT- 

IN- 

duty 

0 0 

m 

1 

Vcc 0 

12V 

4 

+ 3 

Vref 

U2A 

V+ 

LM324 10.4V 

V- 

11 

- 

2 

+ 

+ 

0 

R4 15k C4 1uF 

0 

2400uF 

C3 

0 

68K 

R2 

0 

18K 

R3 

Rload 

17 

0 

0 

NLC controller model 

Closed-loop output 

voltage control 

1A 

0.5A 

2A 

i line 

0 A 

0A 

-0.5A 

-1A 

i line 

AC line current waveform and spectrum at 50W load (left) and 

Simulation 

-2A 

Simulation 

i line [1A/div] 


0 

0 

Line current harmonics [2.4%/div] 

Line current harmonics [1.6%/div] 

3 5 7 9 11 13 15 17 

Experiment 

3 5 7 9 11 13 15 17 

Experiment 

170W load (right)

v o 

50V 

v o 

v m 

30V 

10V 

v m 


0V 

3A 

0A 

i line 

-3A 

Experiment 

Simulation 

50W to 125W load transient in the Sepic PFC 

v g 

200V 

v g 

0V 


3A 

i line 

0A 

-3A 

10V 

v m 

v m 

v o 

0V 

100V 

v o 

0V 

Experiment 

Simulation 

Start-up transient in the Sepic PFC at 50W load

• The averaged switch modeling approach: replace switch network with 

an equivalent circuit that correctly predicts the low-frequency 

components of the switch network terminal waveforms 

• Seminar addressed: 

- PWM converters in continuous and discontinuous conduction modes 

- PWM converters with current-programmed mode (CPM) control 

- Single-phase low-harmonic rectifiers (power-factor correctors) 

• In each case, the large-signal averaged switch model can be used: 

- to develop steady-state and (by linearization) small-signal circuit 

models suitable for analysis 

- to construct Spice-compatible model implementations suitable for 

DC, Transient and AC simulations 

• A number of PSpice model implementation examples and converter 

application examples were presented 

Selected books: 

R.W. Erickson, Fundamentals of Power Electronics, Chpman & Hal, 1997. 

Web page: http://ece-www.colorado.edu/~pwrelect/book/bookdir.html 

J.G.Kassakian, M.F.Schlecht, G.C.Verghese, Principles of Power Electronics, Addison-Wesley, 1991. 

A.Kislovski, R.Redl, N.Sokal, Dynamic Analysis of Switched-Mode DC/DC Converters, New York: Van 

Nostrand Reinhold, 1994. 

P.T. Krein, Elements of Power Electronics, Oxford University Press, 1998. 

Daniel M. Mitchel, DC-DC Switching Regulator Analysis, New York: McGraw-Hill, 1988. 

N.Mohan, T.Undeland, W.Robbins, Power Electronics: Converters, Applications and Design, Second Edition, 

John Wiley & Sons, 1995. 

S.M. Sandler, SMPS Simulation with Spice 3, McGraw Hill, 199.

Selected papers on averaged modeling of switching power converters 

R. M. Bass, J. Sun, “Averaging under large-signal conditions,” IEEE PESC 1998, pp. 630-632. 

R.Erickson, M.Madigan, S.Singer, “Design of a simple high power factor rectifier based on the flyback 

converter,” IEEE APEC, 1990, pp.792-801. 

P. Krein, et al, "On the Use of Averaging for the Analysis of Power Electronic Systems," IEEE Transactions on 

Power Electronics, Vol. 5, No. 2, pp 182-190, April 

1990. 

K.Mahabir, G.Verghese, J.Thottuvelil, A.Heyman, “Linear averaged and sampled data models for large signal 

control of high power factor AC-DC converters,” IEEE PESC, 1990, pp. 372-381. 

D.Maksimovic, S.Cuk, ``A unified analysis of PWM converters in discontinuous modes,'' IEEE Trans. on Power 

Electronics, Vol.6, No.3, July 1991. 

D.~Maksimovic, Y.Jang and R.Erickson, ``Nonlinear-carrier control for high power factor boost rectifiers,'' IEEE 

Transactions on Power Electronics, Vol.11, No.4, July 1996, pp.578-584. 

R.D.Middlebrook and Slobodan Cuk, “A general unified approach to modeling switching-converter power 

stages, International Journal of Electronics, Vol.42, No.6, pp.521-550, June 1977. 

R.D.Middlebrook, “Topics in multiple-loop regulators and current-mode programming,” IEEE PESC, 1985, pp. 

716-732. 

Selected papers on averaged modeling of switching power converter (continued) 

R.D.Middlebrook, “Modeling current programmed buck and boost regulators,” IEEE Trans. On Power 

Electronics, Vol.4, No.1, January 1989, pp.36-52. 

S.R.Sanders, G.C.Verghese, “Synthesis of averaged circuit models for switched power converters,” IEEE 

Transactions on Circuits and Systems, Vol.38, No.8, pp.905-915, August 1991. 

S.Singer, R.W. Erickson, “Power source element and its properties,” IEE Proceedings - Circuits Devices 

Systems, Vol.141, Np.3, pp.220-226, June 1994. 

J.Sun, D.M.Mitchel, M.Greuel, P.T.Krain, R.M.Bass, “Averaged modeling of PWM converters in discontinuous 

conduction mode: a reexamination,” IEEE PESC 1998, pp.615-622. 

J.Sun, D.M.Mitchel, M.Greuel, P.T.Krain, R.M.Bass, “Averaged models for PWM converters in discontinuous 

conduction mode,” HFPC 1998. 

J.Sun, R.M.Bass, “Modeling and practical design issues for average current control,” IEEE APEC 1999. 

R. Tymerski and V. Vorperian, “Generation, classification and analysis of switched-mode DC-to-Dcconverters 

by the use of converter cells,” INTELEC 1986, pp.181-195. 

E. Van Dijk, H.J.N.Spruijt, D.M.O’Sullivan, J.B.Klaassens, “PWM switch modeling of DC/DC converters,” IEEE 

Transactions on Power Electronics, Vol.10, No.6, November 1995, pp. 659-665.

Selected papers on averaged modeling of switching power converter (continued) 

G. Verghese, C. Bruzos, K. Mahabir, “Averaged and sampled-data models for current mode control: a 

reexamination,” IEEE PESC, 1989, pp.484-491. 

V.Vorperian, R.Tymerski, F.C.Lee, “Equivalent circuit models for resonant and PWM switches,” IEEE 

Transactions on Power Electronics, Vol.4, No.2, pp.205-214. 

V.Vorperian, “Simplified analysis of PWM converters using the model of the PWM switch: Parts I and II,” IEEE 

Transactions on Aerospace and Electronic Systems, Vol.AES-26, pp.490-505, May 1990. 

G.W.Wester and R.D.Middlebrook, “Low-frequency characterization of switched Dc-Dc converters,” IEEE 

Transactions on Aerospace and Electronic Systems, Vol.AES-9, pp.376-385, May 1973. 

R.~Zane, D.~Maksimovic, ``Nonlinear-carrier control for high-power-factor rectifiers based on flyback, Cuk or 

Sepic converters,'’ Proc. IEEE APEC, March 3-7, 1996, San Jose, CA, pp.814-820. 

Selected papers on averaged model implementation for computer simulation 

V. Bello, "Computer Aided Analysis of Switching Regulators Using SPICE2," IEEE PESC, 1980 Record, pp 3- 

11. 

V. Bello, "Using The SPICE2 CAD Package for Easy Simulation of Switching Regulators in Both Continuous 

and Discontinuous Conduction Modes," Powercon 8, April, 1981, pp H3-1-14. 

V. Bello, "Using the SPICE2 CAD Package to Simulate and Design the Current Mode Converter," Powercon 

11, April 1984. 

Y. Amran, F. Huliehel, S. Ben-Yaakov, “A unified SPICE compatible average model of PWM converters,” IEEE 

Transactions on Power Electronics, Vol. 6, No. 4, pp. 585-594, 1991. 

S. Ben-Yaakov, “Average simulation of PWM converters by direct implementation of behavioral relationships,” 

IEEE APEC, pp.510-516, 1993. 

S.Ben-Yaakov, D.Adar, “Average models as tools for studying dynamics of switch mode DC-DC converters,” 

IEEE PESC 1994, pp.1369-1376 

S. Ben-Yaakov, Z. Gaaton, “Generic SPICE compatible model of current feedback in switch mode converters, 

Electronics Letters, Vol. 28, No. 14, 2nd July 1992. 

V.M.Canalli, J.A.Cobos, J.A.Oliver, J.Uceda, “Bihavioral large signal averaged model for DC/DC switching 

power converters,” IEEE PESC 1996.

Selected papers on averaged model implementation for computer simulation 

D. Edry, M. Hadar, O. Mor, S. Ben-Yaakov, “A SPICE compatible model of tapped inductor PWM converter,” 

IEEE APEC 1994, pp.1035-1041. 

S. Hageman, "Behavioral Modeling and PSPICE Simulate SMPS Control Loops,” PCIM, April 1990, pp 13-24 

and May 1990, pp 47-50. 

N. Jayaram, D. Maksimovic, “Power factor correctors based on coupled-inductor Sepic and Cuk converters 

with nonlinear-carrier control,” IEEE APEC 1998. 

D. Kimhi, S. Ben-Yaakov, “A SPICE model for current mode PWM converters operating under continuous 

inductor current conditions,” IEEE Transactions on Power Electronics, Vol.6, No.2, pp.281-286, 1991. 

R. Michelet and W. Roehr, "Evaluating Power Supply Designs with CAE Models” APEC 89, pp 323-334. 

D. Monteith and D. Salcedo, "Modeling Feedforward PWM Circuits Using the Nonlinear Function Capabilities 

of SPICE II," Powercon 10,March 1983.

ON Semiconductor 

The “PWM Switch” in mode 

transitioning SPICE models 

PCIM Germany 2005 

Christophe Basso - Application Manager 


Agenda 

Why average simulations? 

What techniques already exist? 

The PWM Switch concept 

The voltage-mode case 

The current-mode case 

Checking averaged model’s validity 

Conclusion 

www.onsemi.com 

Christophe Basso – PCIM 2005 

November 2001 

2


Why average simulations? 

Unveil open-loop ac response for stabilization purposes 

Helps to assess impact of stray elements variations on stability 

Can predict transient response with large-signal models 

Simulation time is quick as frequency component fades away 



November 2001 

3 



State-Space Space Averaging (SSA) 

Introduced by Slobodan uk in the 80’ 

Long and painful process 

Fails to predict sub-harmonic oscillations 

u1 

x1 

L 

on 

x2 

C 

R 

Vout 

dx 

dt 

dx 

dt 

x 

L 

x 

Cout 

u 

L 

x 

Rload Cout 

x1 

L 

off 

x2 

C 

R 

Vout 

dx 

dt 

dx 

dt 

x 

L 

x 

Cout 

Rload Cout 

x 



November 2001 

4



The GSIM concept 

Introduced by Sam Ben-Yaakov in the 90’ 

Easy to derive but not fully invariant (dual inductors converters?) 

Fully auto-toggling mode models 


b 

Ib 

Ic 

c 

V(a,b) 

b 

on 

off 

Fsw 

a 

Lf 

V(a,c) 

Fsw 

on 

off 

c 

Vin 

V(a,b) 

Lf 

Ia 

a 

V(a,c) 

C 

R 



November 2001 

5 



The CoPEC model 

Introduced by the Colorado Power Electronic Center in the 90’ 

Easy to derive and fully invariant 

Fully auto-toggling mode models 


i1(t) 

i1(t) 

v1(t) 

Q1 

D1 

v2(t) 

v1(t) 

Q1 

D1 

v2(t) 

CCM 

d(t) 

i12(t) 

DCM 

d1(t) 

i12(t) 

i1(t) 

i1(t) 

v1(t) 

v2(t) 

v1(t) 

Re(d1) 

I2 

v2(t) 

i12(t) 

i12(t) 

D':D 

I2=(Re x i1^2) / v2 



November 2001 

6



The Ridley models 

Introduced by Raymond Ridley from VPEC in the 90’ 

Use z-transform method 

No auto-toggling mode models 

Can only work in ac 

Can predict sub-harmonic oscillations in CCM 

AC model 

Vin 

Vout 

Vout 

0 

2 

Vg 

AC = 0 

D 

Duty 

0.458 

4 

Gnd 

Ctrl 

0 

3 

V2 

AC = 1 

RS = 20m 

FS = 50k 

VOUT = 5 

RL = 3 

VIN = 11 

X1 

RI = 0.33 

L = 37.5u 

0 

5 

Resr 

100m 

Cout 

220uF 

0 

1 

Rload 

3 



November 2001 

7 



The PWM Switch 

Introduced by Vatché Vorpérian in the mid-80’ 

Easy to derive and fully invariant 

No auto-toggling mode models 

Can predict sub-harmonic oscillations in CCM 

DCM model was never published! 

a 

d 

c 

L 

a 

Ia(t) 

d 

d' 

Ic(t) 

c 

Vin 

PWM switch 

d' 

p 

C 

R 

Vout 

Vap(t) 

p 

Vcp(t) 



November 2001 

8



Linear network 

L 

on 

Vin 

a c 

d 

d' 

PWM switch p 

C 

R 

Vout 

off 

Linear network 

What do 

you plead? 

diode + transistor = guilty for non-linearity! 



November 2001 

9 



Rb_upper 

1Meg 

5 

1 

Rc 

10k 

Vout 

Vin 

ib b 

h11 

7 

e 

c ic 

8 

3 

Beta.Ib 

Vout 

Vg 

Vin 

4 

Q1 

Req 

Rb_upper//Rb_lower 

ie 

Rc 

10k 

2 

Rb_lower 

100k 

Re 

150 

Ce 

1nF 

Re 

150 

Ce 

1nF 

Ve 

Remember the bipolars 

Ebers-Moll model… 

Replace Q 1 by its small-signal model 



November 2001 

10


An invariant association 

L 

Vin 

c 

a 

d 

L 

d' 

PWM switch 

p 

C 

R 

Vout 

Vin 

a c 

d 

d' 

PWM switch p 

C 

R 

Vout 

a 

Ia(t) 

d 

d' 

Ic(t) 

c 

Vin 

a 

d 

d' 

PWM switch 

p 

c 

L 

C 

R 

Vout 

Vap(t) 

p 

Vcp(t) 



November 2001 

11 


Observe waveforms and average them 

Vin 

a 

Vap(t) 

Ia(t) 

d 

p 

d' 

Ic(t) 

c 

Vcp(t) 

L 

C 

R 

Vout 

Tsw 

I t I I t dt d I t dI 

a T a a c c 

sw 

Tsw 

Tsw 

Tsw 

V t V V t dt d V t dV 

cp 

T 

cp cp ap ap 

sw T 

Tsw 

sw 



November 2001 

12


PWM Switch model in CCM: a 1:D transformer! 

a 

Ia(t) 

I=d.Ic 

c 

Ic(t) 

V=d.V(a,p) 

Vap 

a 

Ia(t) 

1 d 

Ic(t) 

c 

Vcp 

p 

p 

p 

Large-signal (non-linear) model 



November 2001 

13 


Use it immediately, SPICE linearizes it for you! 

L 

10.0 10.0 

100uH 

c 

a 

p 

d 

0.400 

16.7 

Vout 

Vin 

10 

Vbias 

0.4 

AC = 1 

C1 

100u 

R1 

10 

Always verify the dc operating point! 



November 2001 

14


The original CCM/DCM PWM Switch models 

a 

d 1-d 

c 

CCM: common « passive » 

vap 

t vcp 

t 

a 

d1 

p 

d2 

p 

DCM: common « common » 

Looks like 

auto-toggling 

is impossible… 

d3 

vac 

t 

vcp 

t 

c 



November 2001 

15 


Deriving the DCM PWM Switch in common « passive » 

I a 

V ap 

I peak 

t 

Vin 

a 

Vap(t) 

Ia(t) 

d1 

p 

d2 

Ic(t) 

d3 

c 

Vcp(t) 

L 

C 

R 

Vout 

I c 

I peak 

t 

t 

I 

I 

a 

c 

I 

peak 

d 

I d I d I d d 

peak peak peak 

V cp V ap V cp 

t 

d 1 T sw d 2 T sw d 3 T sw 

I 

c 

I 

d 

a 

d d d d 

I 

a 

d 



November 2001 

16


An auto-toggling version: clamp the equation! 

a 

Ia(t) 

Ic(t) 

c 

Clamp 

Vap 

1 N 

Vcp 

p 

N=d1/(d1+d2) 

d 

IL V d T LF I 

V dT d V 

c ac sw sw c 

ac sw ac 

d 



November 2001 

17 


In voltage mode, add the PWM modulator gain 

a 

X4 

PWMCCMVM 

c 

5.00 

4 

L1 

75u 

10.0 

3 

V4 

10 

0.500 

17 

GAIN 

d 

PWM switch VM 

XPWM 

GAIN 

K = 0.5 

p 

5.0 

K 

PWM 

V 

peak 



November 2001 

18

, 

- 


Testing the auto-toggling model 

a 

4.99 c 

L1 

75u 

4 17 

R5 

20m 

vout 

4.99 

Vout 

X2 

PSW1 

L1 

75u 

IC = 

1 4 

R4 

20m 

vout 

Vout 

10.0 

3 

V4 

10 

0.499 

5 

GAIN 

d 

PWM switch VM p 

X10 4.99 

XPWM 

PWMVM2 

GAIN 

L = 75u 

K = 0.5 

Fs = 100k 

Resr 

70m 

2 

Cout 

100u 

IC = 0 

Xstep 

PSW1 

19 

Vstep 

10 

V4 

10 

7 

D2 

N = 0.01 

Resr 

70m 

Cout 

100u 

IC = 

16 

Xstep 

PSW1 

20 

Vstep 

vout 

vout 

C2 

{C2} 

R2 C1 

{R2} {C1} 

14 

0.329 

Rupper 

{Rupper} 

2.50 

7 

R3 

{R3} 

5.00 

13 

C3 

{C3} 

6 

+ 

3 

X8 

COMPAR 

C2 

{C2} 

R2 C1 

{R2} {C1} 

19 

Rupper 

{Rupper} 

13 

R3 

{R3} 

18 

C3 

{C3} 

6 

Verr 

2.50 

8 

X2 

V2 

AMPSIMP 2.5 

VHIGH = 1.9 

Rlower 

10k 

Vsaw 

Tran Generators = PULSE 

Verr 

8 

X1 

AMPSIMP 

VHIGH = 1.9 

V2 

2.5 

Rlower 

10k 


Cycle-by-cycle 



November 2001 

19 


Comparing results with a stepload… 

5.40 

5.20 

5.00 

4.80 

4.60 

1.10 

900m 


I can’t believe 

this result… 

700m 

500m 

300m 

9.75m 11.2m 12.7m 14.2m 15.7m 

time in seconds 



November 2001 

20


Current-mode PWM switch 



November 2001 

21 


CCM operation, current expression 

I t R V t d t T S 

c i c sw e 

Sd tT 

f 

sw 

V T S T 

I c 

d V d 

R R L 

c sw e sw 

cp 

i 

i 

a 

c 

Ia(t) 

Ic(t) 

I=d.Ic 

I=Vc/Ri 

I=Iu 

Cs 

p 

p 



November 2001 

22

- 


DCM operation, current expression 

I 

I 

I 

peak 

Vc dTsw Se 

Ri 

Vc dTswSe 

d T S 

Ri 

I d I d I d d 

c sw f 

c 

peak peak peak 

d Tsw Se V c p d d 

I d Tsw 

Ri 

L 

a 

Ia(t) 

c 

Ic(t) 

I=(d1/(d1+d2)).Ic 

I=Vc/Ri 

I=Iu 

p 

p 



November 2001 

23 


The PWM Switch, the final encapsulation 

duty_cycle 

a 

2 

duty-cycle 

c 

L1 

75u 

1 4 

R4 

20m 

vout 

Vout 

X2 

PSW1 

L1 

75u 

IC = 250m 

1 4 

R4 

1 

vout 

Vout 

V4 

25 

d 

PWM switch CM p 

X1 

PWMDCMCM 

Resr 

70m 

16 

Cout 

220uF 

10 

V4 

25 

12 

D1 

1n5818 

Resr 

70m 

16 

Cout 

220uF 

IC = 4.6 

20 

V2 

V2 

X5 

PSW1 

C2 

470p 

vout 

X5 

PSW1 

2 

V1 

S 

Q 

R1 

20k 

C1 

10n 

12 

R7 

10k 

Q 

R 

10 

L4 

1p 

6 

13 

C1x 

100p 

9 

C3 

1p 

11 

8 

Y4 

X4 

AMPSIMP 

7 

V6 

2.5 

R8 

10k 

X3 

COMPAR 

+ 

14 6 

C2 

470p 

R3 

470 

B1 

Voltage 

17 

V(4,vout) 

vout 

V7 

AC = 1 

R1 

20k 

C1 

10n 

24 

R7 

10k 

18 

Verr 

X4 

AMPSIMP 

19 

V6 

2.5 

R8 

10k 



November 2001 

24


Good matching between both models 



November 2001 

25 


Testing the ac response 

0.649 

18 

0.408 

dc 

a 

duty-cycle 

vc 

PWM switch CM 

X1x 

XFMR 

-127RATIO = -0.1 

Vout 

D1 

L1 

Rs 

MBR140P out1 2.2uH 

12.2 12.2 10m12.2 

out2 

126 

2 

Vin 

126 

c 

p 

0 

3 

PWMCM 

X1 

L = 1.8m 

L3 Fs = 66k 

1.8m Ri = 1.5 

1 4 

12.7 

R4 

R5 

100m 

100m 

12.2 12.2 

15 7 

C1 

C5 

470uF 

470uF 

6 

R17 

300m 

12.2 

9 

C2 

10uF 

Rload 

14 

V3 

4.8 

4.80 

11 

out1 

out2 

0.649 

14 

R7 

8k 

R15 

LoL 

1.5k 

1kH0.649 

10.6 

VFB 

16 

5 

CoL 

1kF 

0 

12 

9.88 

10 

Cf 

100nF 

Rupp 

3.9k 

Vstim 

AC = 1 

X3 

TL431 

2.50 

13 

A dcm current-mode flyback 

Rlow 

1k 



November 2001 

26


Ac simulation results of the flyback converter 

0 

10 100 1K 10K 100K 



November 2001 

27 


If the load increases… 

plot1 

vdbfb in db(volts) 

60.0 

40.0 

20.0 

0 

-20.0 

gain 

CCM operation 

Sub-harmonic oscillations! 

1 

Plot2 

ph_vfb in degrees 

220 

180 

140 

100 

phase 

2 

60.0 

10 100 1k 10k 100k 

frequency in hertz 



November 2001 

28


Testing on a multi-output forward 

L2 

12.2 {L2} 12.2 

4 5 

R2x 

70m 

12.0 

9 Vout2 

X1 

XFMR 

RATIO = N2 

Resr2 

100m 

12.0 

2 

Cout2 

100u 

Rload2 

6 

X7 

XFMR 

RATIO = N1/N2 

dc 

0.356 

duty-cycle 

160 56.6 

a 

c 

10 8 

L1 

28.3 {L1} 28.3 

11 3 

R9 

70m 

vout 

28.0 

Vout1 

V6 

parameters 

160 

Rsense=0.35 

Vout=28 

L1=130u 

L2=130u 

N1=0.5 

N2=0.215 

Rupper=(Vout-2.5)/250u 

fc=5k 

pm=50 

Gfc=8.84 

pfc=-66 

G=10^(-Gfc/20) 

boost=pm-(pfc)-90 

pi=3.14159 

K=tan((boost/2+45)*pi/180) 

C2=1/(2*pi*fc*G*k*Rupper) 

C1=C2*(K^2-1) 

R2=k/(2*pi*fc*C1) 

0.861 

1 

vc 

PWM switch CM p 

X5 

PWMCM2 

L = L1/N1^2+L2/N2^2 

Fs = 200k 

Ri = Rsense 

Se = 0 

C2 

{C2} 

R2 C1 

{R2} {C1} 

20 

0.861 

LoL 

1kH 

19 

0.861 

2.50 

CoL Verrx 

X4 

1kF 

0 

AMPSIMP 

7 

V1 

AC = 1 

X6 

XFMR 

RATIO = N1 

vout 

Rupper 

{Rupper} 

2.50 

13 

18 

Rlower 

V3 

10k 

2.5 

Resr1 

245m 

28.0 

6 

Cout1 

48u 

Rload1 

7 

A multi-output forward 



November 2001 

29 


Output voltage bang on the 28 V output… 

28.8 

Plot1 

vout, vout1 in volts 

28.4 

28.0 

27.6 

3 

1 

27.2 

Averaged 


12.4 

12.5 

Plot2 

vout2 in volts 

12.2 

12.0 

11.8 

vout2#a in volts 

12.3 

12.1 

11.9 

24 

11.6 

11.7 

3.93m 4.83m 5.74m 6.64m 7.55m 




November 2001 

30


Output voltage bang on the 28 V output… 

28.8 

plot1 

vout, vout1 in volts 

28.4 

28.0 

27.6 

4 

1 

27.2 

Averaged 


12.8 

Plot2 

vout2, vout2#a in volts 

12.4 

12.0 

11.6 

3 

2 

11.2 

3.83m 4.75m 5.68m 6.61m 7.54m 




November 2001 

31 


Instability in the buck DCM current-mode 

> 20 dB increase 

Plot1 

vphout, vphout#1, vphout#2 in degrees 

180 

90.0 

0 

-90.0 

vdbout, vdbout#1, vdbout#2 in db(volts) 

80.0 

40.0 

0 

-40.0 

Gain 

V in 

R load 

Phase 

V in 

R load 

Gain 

V in 

R load 

Phase 

V in 

R load 

V in M 

V in M 

V in M 

Gain 

V in 

3 

5 

1 

2 

46 

The DCM buck 

shows instability 

as M > 0.66 

without ramp 

Phase jumps 

to –180° 

-180 

-80.0 

Phase 

V in 

R load 

1 10 100 1k 10k 100k 1Meg 




November 2001 

32


Instability in the buck DCM current-mode 

40.0 

180 

Gain 

V in 

R load 

Adding 0.086 x S off 

cures the problem 

Plot1 

vdbout, vdbout#2 in db(volts) 

20.0 

0 

vphout, vphout#2 in degrees 

90.0 

0 

Gain 

V in 

R load 

S a 

Phase 

V in 

R load 

S a 

2 

4 

-20.0 

-90.0 

-40.0 

-180 

Phase 

V in 

R load 

3 

1 

1 10 100 1k 10k 100k 1Meg 




November 2001 

33 


The conclusion 

The CM PWM Switch DCM was derived 

Two auto-toggling models developed 

Good matching of average vs reality 

Models also exist in BCM (PFC simulations) 

Exist in both IsSpice and PSpice 



November 2001 

34

8 PWM switching dc-to-dc converters 

Introducing the PWM switch 

8.1 Introduction 

An electronic circuit which transforms the dc level of a voltage or current source in 

a controllable manner without dissipating power is called an ideal dc-to-dc 

converter or simply a converter. This is shown in Fig. 8.1 in which α is a control 

parameter on which the output voltage or current depends. When feedback is used 

as shown in Fig. 8.2,either the output voltage or output current can be regulated 

against variations in the input voltage or load current. A vast majority of applications,such 

as logic and sensitive instrumentation circuits,require a converter 

whose output voltage,rather than the output current,is tightly regulated. A 

converter may also have more than one control parameter so that α can be taken 

as a control vector. 

Figure 8.1 

Figure 8.2 

365 

In the following sections we shall determine the basic characteristics of dc-to-dc 

converters,determine their equivalent circuits using a model of the PWM switch, 

and analyze their dynamics using the techniques developed in this book.


8.2 Basic characteristics of dc-to-dc converters 

The voltage conversion ratio of a converter is defined as the ratio of the dc output 

voltage to the dc input voltage: 

M 

V 

V 

(8.1) 

In a similar manner,the current conversion ratio is defined as the ratio of the dc 

output current to the dc input current: 

M 

I 

I 

(8.2) 

Since in an ideal converter there can be no power dissipation,the input and output 

powers must be equal: 

P 

P 

V 

I 

V 

I 

M 

M 

1 (8.3) 

No practical converter can satisfy the condition in Eq. (8.3) because of losses 

associated with nonideal components. In designing a converter,every effort is 

made to keep these losses to a minimum in order to maximize the efficiency,which 

is defined as the ratio of the output power to the input power: 

η P 

P 

M 

M 

(8.4) 

One may wonder what kind of ideal components go into an ideal converter. 

Resistors,which may be arranged as a voltage divider to achieve down conversion, 

are precluded because they dissipate power and lack controllability. A bipolar 

transistor connected between a voltage source and a load can achieve controllability 

by adjusting V 

,but such a circuit,known as a series regulator (see Problem 

8.1),dissipates power by an amount given by: 

P 

V 

I 

(V 

V 

)I 

(8.5) 

Hence,the series regulator and its dual,the shunt regulator (see Problem 8.2),are 

not classified as converters. In fact,these circuits are nothing more than linear dc 

amplifiers. 

The two mechanisms required for nondissipative power conversion are switching 

and filtering. Switching is achieved by a minimum of two switches while filtering 

is achieved by inductors and capacitors arranged in an effective low-pass filter 

configuration. The purpose of the filters is to attenuate the pulsating currents,

367 8.2 Basic characteristics of dc-to-dc converters 

generated by the switches,down to a specified level at the input and output ports 

of the converter. Since ideal switches,inductors and capacitors do not dissipate 

any power,the ideal conversion efficiency is 100%. In reality,all practical inductors 

and capacitors dissipate a very small percentage of the peak energy stored in 

them owing to dielectric,conductive and magnetic losses. Also,all practical 

semiconductor switches have finite conductive and switching losses. The switching 

frequency is one of the most critical parameters in the design of a switching 

converter. Increasing the switching frequency results in smaller inductors and 

capacitors but higher switching losses and lower efficiency. The tradeoff between 

size,cost,weight and efficiency has never been an exact science and is usually 

driven by market requirements. For example,a commercially available 48 V to 

5 V,100-W converter may have an efficiency of 80% at full load with linear 

dimensions 3.0 1.5 0.38,whereas a similar custom-designed converter may 

in comparison have an efficiency of 93% and twice the linear dimensions. 

We consider now the input and output port characteristics of an ideal converter 

with and without feedback. In what follows we shall assume that a converter is 

made of linear inductors and capacitors. For a converter without feedback,the 

output voltage is linearly related to the input voltage by the conversion ratio M 

: 

No feedback V 

M 

V 

; M 

M 

(V 

) (8.6) 

The reason for this is that the switching action in any dc-to-dc converter,as we 

shall see,produces a periodic sequence of linear networks. The conversion ratio is 

obtained by piecing together the solutions of the individual switched linear networks 

which are linear functions of the input voltage. Hence,the piecewise 

composite solution is also a linear function of the input voltage. Following the 

same argument we conclude that M 

is also independent of the input voltage. 

Hence,the ideal voltage converter in Fig. 8.1a can be modeled by an ideal 

transformer with turns ratio M 

as shown in Fig. 8.3. In general M 

is a function of 

the control parameter, α,the output voltage,V 

,and the output current,I 

: 

M 

M 

(α, V 

, I 

) (8.7) 

Also,a converter can in general have several modes of operation so that a unique 

M 

may not be sufficient for modeling purposes. In the very important class of 

converters discussed in this chapter, M 

is only a function of α. 

Figure 8.3


The input and output characteristics of an ideal converter can now be ascertained 

using the equivalent circuit in Fig. 8.3. For an unregulated converter feeding 

a resistive load R 

,the incremental input resistance seen by the source according 

to Fig. 8.3 is: 

R 

R 

M 

(8.8) 

For an ideal converter in which the output voltage is regulated by the feedback 

arrangement shown in Fig. 8.4,the output voltage is equal to the reference voltage: 

V 

V 

(8.9) 

Hence,when the load is fixed,the input power of a regulated converter is fixed and 

independent of the source voltage. It follows that any increase in the source voltage 

is accompanied by a decrease in the source current,which implies that the 

incremental input resistance of a regulated converter is negative. Proceeding as 

follows,we obtain: 

P 

V 

0 V 

I 

V 

I 

0 I 

V 

I 

V 

(8.10) 

Substituting Eqs. (8.1),(8.2) and (8.3) in Eq. (8.10) we obtain several useful expressions 

for the incremental input resistance: 

R V P 

(V /I ) 

M 

⎫ 

⎬⎭ 

(8.11a—c) 

R 

M 

In Eq. (8.11c) we have made use of the fact that R V /I whenever the load 

 

actually consists of a resistor as shown in Fig. 8.4. 

Figure 8.4

369 8.2 Basic characteristics of dc-to-dc converters 

The incremental output resistance of regulated and unregulated ideal converters 

can be determined in a similar manner (see Problem 8.3). 

Example 8.1 An ideal battery charging circuit is shown in Fig. 8.5. This circuit is 

somewhat tricky because it has two voltage sources connected in parallel with zero 

resistance between them. If it were not for the control circuit,it would not have 

been clear which of the two voltage sources was charging or being charged and the 

charging current would have been undetermined. In this ideal case,the feedback 

circuit adjusts the control parameter α,and hence the conversion ratio M ,by 

monitoring the charging current I to ensure I I . The value of α determined by 

 

the control circuit is given by: 

α M 

V 

V 

 

(8.12) 

If α were to deviate by the slightest amount from the value in Eq. (8.12),the 

charging current would become infinite,causing an infinite error signal,which 

would be instantaneously corrected by the negative feedback circuit. The current 

drawn from the source,when α is set exactly to the value in Eq. (8.12),is determined 

from the current conversion ratio: 

I 

I 

M 

I 

M 

I 

V 

V 

(8.13) 

where we have made use of the fact that M 

M 

1 for an ideal converter. 

The incremental input impedance is determined next following the procedure in 

Eq. (8.10): 

I 

V 

I 

V 

I V 

V 

(8.14) 

Figure 8.5 

It follows that: 

R 

V 

I 

V 

(8.15)


The same result could have been obtained directly from Eq. (8.11a). 

 

8.3 The buck converter 

Consider the task of converting an unregulated dc voltage source, V 

,to a 

regulated dc voltage source V 

V 

which supplies power to a load R 

.One 

simple and efficient way of doing this is to chop the source and generate a unipolar 

voltage pulse train with an amplitude V 

,a fixed period T 

,and a variable width,or 

on-time T 

,as shown in Fig. 8.6. Such a waveform is known as a pulse-widthmodulated 

(PWM) waveform. It is relatively easy to see that the dc component of 

the PWM waveform in Fig. 8.6 can be controlled by varying the pulse width, T 

. 

To make use of this dc component,the high-frequency components must be 

filtered out by a nondissipative low-pass filter. A simple converter which can chop 

and filter as described above is the buck converter shown in Fig. 8.7. 

Figure 8.6 

Figure 8.7 

The chopper section of the buck converter consists of two switches S and S 

which are driven by the complementary switching functions D 

(t) and D (t) 

1 D (t),respectively. The switching function is a unit pulse train defined: 

 

D 

(t) 

1 nT t nT T 

(8.16) 

0 nT T t (n 1)T 

⎫ 

⎬ 

⎭

371 8.3 The buck converter 

Looking back into the chopper circuit from the terminals of S ,we see an effective 

 

voltage source V (t) given by: 

 

V 

(t) V D (t) (8.17) 

 

The dc component of V (t) is given by: 

 

1 

T 

 

V 

(t)dt 1 T 

 

 

 

V D (t)dt DV (8.18) 

 

 

in which D is defined as the duty-ratio function,or duty cycle,and is given by: 

D 1 T 

 

D 

(t)dt T 

(8.19) 

T 

 

 

The LC filter following the chopper is the simplest,lossless,low-pass filter that can 

extract the dc component of V 

(t) and generate a dc output voltage V given by: 

 

V DV (8.20) 

 

It is clear from Eq. (8.20) that the dc output voltage can be regulated by varying the 

duty cycle, D,so that the duty cycle serves as the control parameter,i.e. α D. It 

follows from Eq. (8.20) that the voltage conversion ratio, M 

,of the buck converter 

is given by: 

M 

V 

V 

D (8.21) 

In order to determine the steady-state voltages and currents of the buck converter,we 

need to study the response of the low-pass LC filter to V (t). The following 

 

transfer function can be easily verified (see Problem 8.4): 

H(s) v (s) 

v 

(s) 1 

1 s 

ω 

Q s 

ω 

(8.22) 

in which: 

ω 

1 

LC 

Q 

R 

L/C 

⎫ 

⎬ 

⎭ 

(8.23a, b) 

The magnitude and phase response of H(s) is shown in Fig. 8.8. In order to study 

the interaction of V 

(t) with H(s),we write V (t) as: 

 

V 

(t) DV V (t) (8.24)


in which V (t) is a periodic waveform which contains only the fundamental and 

harmonics of V (t). From the magnitude response of H(s),it can be seen that the dc 

 

component, DV ,of V (t) will pass through and become the dc component of the 

 

output voltage. It can also be seen from the same figure that if the corner frequency 

of the filter, f ,is chosen well below the switching frequency of the converter, 

 

F 1/T ,then all the harmonics of V 

(t) atnF will fall on the 40 dB/dec 

 

asymptote so that the ac components of V (t) will be attenuated and integrated 

 

twice. Therefore,the actual output voltage consists of the dc component V DV 

and a small periodic waveform, V (t),known as the output ripple voltage: 

 

V 

(t) V V (t); V (t) V (8.25) 

 

Figure 8.8 

Since the output ripple voltage is given by the high-frequency response of H(s) to 

V(t),we can approximate H(s) as: 

H(s) ω 

s 

(8.26) 

Equation (8.26) corresponds to a double integration so that we have: 

V 

(t) ω V (t)dt (8.27) 

in which V (t),according to Eqs. (8.16),(8.17) and (8.24),is given by: 

V (t) 

⎫ 

⎬ 

⎭ 

V V nT t nT T 

(8.28) 

V nT T t (n 1)T 

Since V (t) is a constant in each subinterval,the double integration in Eq. (8.27) 

yields a parabolic segment in each subinterval as shown in Fig. 8.9. Note that the 

ripple voltage, V (t),and V (t) are inverted with respect to each other because all the


frequency components of V (t) are phase shifted by 180° owing to the phase 

response of H(s) at high frequencies. Each parabolic segment of the voltage ripple 

is given by: 

V 

(t) V ω (V V ) t 2 

V 

(t) V ω V t 

2 

⎫ 

⎬ 

⎭ 

(8.29a, b) 

in which the time origin of each segment is taken at its peak. The peak-to-peak 

output voltage ripple follows from Eqs. (8.29a, b) which,when normalized with 

respect to the output voltage (see Problem 8.5),is given by: 

δV 

V 

V 

π 

2 (1 D) f 

F 

 

(8.30a) 

For a regulating converter,the worse case normalized ripple,δ 

,occurs at D 

or 

M 

so that we have: 

δ 

π 

2 (1 M ) f 

F 

 

Hence,the LC filter is designed with a resonant frequency f 

given by: 

(8.30b) 

f 

F 

π 2δ 

1 M 

(8.31) 

Note that f 

is expressed in terms of the design specifications (δ 

, M 

) and a design 

parameter F 

which the designer chooses. 

Figure 8.9 

Example 8.2 A 100-kHz buck converter is to be used in the design of a regulated 

converter which operates from an unregulated bus voltage of 28 4 V and


delivers an output of 12 V at 2.3 A. The maximum output ripple voltage is specified 

to be 150 mV. Determine the range of the duty ratio and f 

of the output filter. 

According to the given variation in the bus voltage the specified range of the 

duty cycle and the conversion is: 

M D 

V 12 

V ῀V 28 4 0.375 ⎫ 

 

⎬⎭ 

(8.32a, b) 

M D 

V 12 

V ῀V 28 4 0.5 

According to Eq. (8.31),the worse case,or the lowest corner frequency,requirement 

is dictated by M 


f 1 F 

π 2δ 1 1 M 

π 2(0.15/12) 0.064 (8.33) 

1 0.375 

Hence,the corner frequency of the filter must be selected less than or equal to 

6.4 kHz to have an output ripple voltage of 150 mV or less. 

Determination of the corner frequency of the filter in the example above does 

not uniquely determine the inductor and the capacitor. We shall now determine 

the current in the inductor and show that its ripple component provides another 

design equation for the selection of L and C. The current in the inductor consists of 

a dc and a ripple component. The dc component of the inductor current is the 

same as the dc component of the output current because the capacitor does not 

carry any dc current. Hence,the inductor current can be written as: 

I 

(t) I I (t) (8.34) 

 

in which I V /R. 

The ripple current in the inductor is determined by integrating the voltage 

across it,which is given by: 

V 

(t) V (t) V (t) 

V V (t) V V 

 

V (t) 

(t) (8.35) 

 

In the last step we have ignored the output ripple voltage because it is much 

smaller in comparison with V (t). Since V (t) has a constant value in each subinterval,the 

ripple current consists of two linear segments as shown in Fig. 8.10. The 

first segment of the inductor current is given by: 

I 

(t) L 1 (V V )dt I V V t (8.36) 

L


in which the time origin has been taken at I 

. For the second segment we have: 

I 

(t) L 1 (V )dt I V 

L t (8.37) 

 

in which the time origin has been taken at I . Since the ripple current is linear,the 

 

average value of the inductor current is midway between I and I and the 

 

peak-to-peak ripple current can be determined from either segment. Hence,letting 

t DT in Eq. (8.37),we obtain: 

 

I 

I 

V DT 

L 

(8.38) 

It follows that the peak-to-peak ripple current is given by: 

I 

 

I 

I 

V DT 

L 

(8.39) 

Figure 8.10 

It can be seen from Eq. (8.39) that for a buck converter with a regulated output 

voltage,the maximum ripple current occurs when D is a maximum,which occurs 

when the input voltage is a maximum. When the ripple current is normalized with 

respect to the average inductor current, I 

I 

,we obtain: 

δI I V DT 

I I L 

RDT 

L 

 

(8.40) 

The amount of ripple current determines the peak current in the inductor and 

the switches S 

and S 

. This peak is given by: 

I 

I 

I δI 

2 

(8.41) 

The maximum value of the peak current in Eq. (8.41) occurs at the specified


maximum load current so that we have: 

I 

 

I 

 

(1 δ 

) (8.42) 

in which δ 

is the worst case value of δI 

/2 and is given by: 

δ 

V (1 M )T 

2LI 

 

(8.43) 

It follows that,for a design choice of δ 

, L is determined uniquely according to: 

L 1 

F 

δ 

V 

(1 M 

) 

2I 

 

(8.44a) 

The value of C follows from the resonant frequency given in Eq. (8.31): 

C δ I 

 

F 4V δ 

(8.44b) 

Note that Eqs. (8.44a, b),just like Eq. (8.31),express L and C in terms of the design 

specifications (V 

, M 

, I 

 

, δ 

) and the design parameters (F 

, δ 

). 

The maximum peak current is an important design consideration and is expressed 

in terms of δ 

. For example,it can be seen that designing with a larger 

value of δ 

results in a smaller inductor,a larger capacitor and a larger peak 

current. There are many design tradeoff considerations which we will not discuss 

here and which result in practical values of δ 

in the range 0.1—1.0. 

Although not necessary,the design equations of the filter elements can be 

expressed in terms of the resonant frequency f 

given by Eq. (8.31) and the Q-factor, 

which we shall determine next. Hence,after performing the necessary substitutions,we 

can rewrite Eq. (8.43) as: 

δ 

π(1 M 

)Q 

f 

F 

(8.45) 

in which Q 

is given by: 

Q 

(V /I ) 

ω 

L 

ω 

C(V 

/I 

 

) 

⎫ 

⎬ 

⎭ 

(8.46a, b) 

If the load is a simple resistor R,then V 

/I 

R and Q 

is the same as the Q-factor 

of the LC filter. If the load,on the other hand,is a current source,another 

regulated converter,or a battery as in Example 8.1,then Q 

and the actual Q-factor 

are different. Performing the necessary substitutions for Q 

,we obtain an alternate 

set of design equations for the LC filter:


⎫ 

f F π 2δ 

1 M (8.47a, b) 

δ 

⎬ 

Q 

2δ (1 M ) ⎭ 

 

Example 8.3 If the maximum peak current in the buck converter of Example 8.2 

is to be 3 A,determine the values of L and C. 

The value of δ 

,given by Eq. (8.42),is computed first: 

δ I 1 3 1 0.3 (8.48) 

I 2.3 

 

Next we compute Q 

given by Eq. (8.47): 

0.3 

Q 

2.4 (8.49) 

2(1 0.375)(0.15/12) 

The values of L and C are obtained from Eqs. (8.46a, b): 

L (12/2.3) 

(2π6400)2.4 54 μH ⎫ 

⎬ 

(8.50a, b) 

2.4 

C 

(2π6400)(12/2.3) 11.14 μF ⎭ 

These are exact values,which may or may not be available. Typically,the tolerances 

on power inductors and large capacitors can be of the order 5—10%. Hence, 

when the actual components are chosen,the nearest available values are selected 

such that their worst case values are greater or equal to those determined 

above. 

 

The currents and voltages of the switches S 

and S 

are examined next. These 

are shown in Fig. 8.11 and can be verified easily. Switch S 

is called the active 

switch and it carries the inductor current during DT 

. Switch S 

is called the passive 

switch and it carries the inductive current during DT 

. Two practical realizations 

of the switches are shown in Figs. 8.12a and b. The difference between these two 

realizations is in their modes of operation at low-output currents as shown in Fig. 

8.13. When a MOSFET is turned on,it can conduct in both directions whereas a 

diode can conduct only in one direction. Hence,in Fig. 8.12a,when Q 

is turned 

off,the current in the inductor turns on the diode to initiate the DT 

subinterval. 

The diode will conduct as long as the inductor current is positive,which is 

expressed quantitatively: 

I 

 

2 I 

(8.51)


Figure 8.11 

If this condition is not satisfied,then the diode will stop conducting before the end 

of DT 

and a third interval of operation will occur during which both switches will 

be in the off state and the output capacitor will discharge into the load. This is 

called the discontinuous conduction mode (DCM),which we shall not discuss 

here. In DCM,the conversion ratio is no longer the same as in the continuous 

conduction mode (CCM) and depends on the output current and the switching 

frequency in addition to the duty-cycle D. The current waveforms in DCM are 

shown in Fig. 8.13a. 

When a MOSFET is used instead of a diode,as shown in Fig. 8.12b,the 

converter is capable of operating in CCM down to zero load current,because 

when a MOSFET is turned on it can conduct in both directions allowing the 

current in the inductor to reverse direction. The currents in both MOSFETs at 

low-output currents,when the condition in Eq. (8.51) is not satisfied,are shown in 

Fig. 8.13b. 

Figure 8.12 

For the buck converter discussed above,the input current is pulsating and is the 

same as the current in S 

. The input current of an ideal converter,however,must 

be smooth and only follow the variations in the output current as required by the


equivalent circuit model of an ideal converter shown in Fig. 8.3. Hence,another 

filter must be added on the input side to reduce the input ripple current down to an 

acceptable level. It is interesting to point out that the end-user of a converter 

usually does not care how much ripple current the converter generates on the 

input power bus. But,high frequency ripple currents on power lines,called 

conduction emissions,create serious interference problems for other users. Hence, 

for commercial applications,conducted emissions are specified and enforced by 

regulatory agencies such as the FCC in the USA,the CSA in Canada and the VDE 

in Germany. (For military and aerospace applications,conducted emissions must 

Figure 8.13 

comply with US Military Standards 461.) The simplest type of input filter,with 

series or shunt damping,is shown in Figs. 8.14a and b in which R L and R C 

are the series and shunt damping networks,respectively. The purpose of the 

damping networks is to prevent oscillations or ringing,and these will be discussed 

shortly. 

The input ripple current is calculated by determining the transfer function H (s) 

shown in Fig. 8.15,in which the current source I (s) is the pulsating current drawn 

 

by the converter. In this figure,we have assumed that the ripple voltage across C is 

small in comparison with the dc voltage across it so that the shape of I (t) is 

 

essentially the same with or without the input filter. In determining this transfer 

function,the effect of the damping network can be ignored so that we have from 

Fig. 8.15: 

I 

(s) 

I 

(s) 1 

1 s/ω 

(8.52) 

in which: 

ω 

1 

L 

C 

(8.53)


Figure 8.14 

According to Eq. (8.52),the dc component of I (t) will pass through the input 

 

circuit,while its ac component,I (t),will be attenuated,if its frequency spectrum 

 

falls above ω . Hence,as in the design of the output filter,we choose the corner 

 

frequency of the input filter to be much lower than the switching frequency so that 

I (t) will be attenuated and integrated twice. Hence,the input ripple current is 

 

given by: 

I (s) 

I (s) ω 

s I (t) ω 

I (t)dt (8.54) 

 

The exact calculation of the peak-to-peak ripple from the double integral in Eq. 

(8.54) is somewhat tedious because of the cubic term that arises from the current 

Figure 8.15 

slope during DT 

. This calculation can be simplified if the trapezoidal pulse is 

replaced with a rectangular pulse of the same area and duration. The height of this


equivalent rectangular pulse,of course,is equal to the output current. This 

simplification is justified because the maximum input ripple current occurs at 

maximum load current; which,in most designs,corresponds to an I (t) that is close 

 

to rectangular. The resulting expression of the peak-to-peak input ripple current is 

given (see Problem 8.6) by: 

I 

 

I 

πDD 

2 f 

F 

(8.55) 

It is clear from Eq. (8.55) that the worst case value of the input ripple current occurs 

at maximum load. The maximum value of the term DD,however,depends on the 

specified range of D 

D D 

. Hence,we have from Eq. (8.55): 

I 

 

I 

 

π(max[DD]) 

2 f 

F 

(8.56) 

in which 

max[DD] 

⎫ 

⎬ 

⎭ 

D 

(1 D 

); D 

1/2 

1/4; D 

1/2D 

1/2 

D 

(1 D 

); D 

1/2 

(8.57) 

With these design equations we can only determine the resonant frequency of the 

input filter but not C 

and L 

individually. We could derive another design 

equation in terms of the voltage ripple on the input capacitor, C 

,so that C 

and L 

could be determined uniquely,but the input voltage ripple is hardly a design 

consideration. Hence,typically,once f 

is determined, L 

and C 

are usually 

determined such that their combined volume is as small as possible. 

Example 8.4 Determine the resonant frequency of the input filter for the buck 

converter in Example 8.3 so that I 10 mA. Since D 0.5,we have from 

 

Eqs. (8.56) and (8.57); 

0.01 2.3 π 

2 

1 

4 f 

F 

f 0.059 (8.58) 

F 

Hence,the input filter is designated with f 

5.9 kHz. 

Since the input impedance of a regulating converter is negative,the addition of 

an LC input filter can easily result in an instability because of the negative 

damping effect. Hence,it is always a good idea to damp the input filter of a 

regulating converter by adding either a series or shunt damping branch as shown 

in Figs. 8.14a and b. The design of the damping network can be optimized if the 

frequency response of the input impedance of the converter is known. We shall be 

brief and present a much simpler technique that assumes that the input impedance


is real and negative. In Fig. 8.14a,if C 

is chosen to be much larger than C 

,then at 

resonance the capacitive reactance of C 

will be much higher than that of C 

so 

that the damping resistor, R 

,will appear effectively in parallel with the negative 

resistance of the input converter resulting in a Q given by: 

Q 

R R 

L 

/C 

(8.59) 

in which: 

R 

V 

I 

1 

M 

(8.60) 

Typically, R 

is chosen such that Q 

1. Note that Q 

cannot be chosen to be 

very small simply because as R 

gets smaller,then C 

begins to appear effectively 

in parallel with C 

,which in turn gives rise to a new,lower,undamped resonance 

formed by C 

C 

and L 

(see Problem 8.7). 

Example 8.5 For the buck converter discussed in the previous examples,we 

select the input filter inductor to be 86 μH. With the resonant frequency determined 

to be f 5.9 kHz,the value of the input filter capacitor is given by: 

 

1 

C 

8.46 μF (8.61) 

(2π5900)86 10 

The smallest value of the negative input resistance of the converter occurs at M 

, 


R 12 V 1 

20.9 Ω (8.62) 

2.3 A (0.5) 

The value of the damping resistor for the shunt branch is determined from Eq. 

(8.59) in which we select Q 

1. This yields: 

1 R (20.9) 

86/8.46 R 2.8 Ω (8.63) 

 

The value of C 

is chosen to be about ten times that of C 

: 

C 

10C 

84 μF (8.64) 

An OrCAD/Pspice simulation of the actual filter and its frequency response is 

shown in Figs. 8.16a and b. The response is seen to be properly damped so that any 

transient disturbance in the input voltage will not generate any ringing in the input 

filter. 

A simulation of the actual input ripple current is shown in Figs 8.17a and b in


Li 

86uH 

Vin 

Rid 

2.8 

Cid 

84.6uF 

Ci 

8.46uF 

Rin 

-20.9 

0 

Figure 8.16 

Figure 8.17 

which we see that the peak-to-peak ripple current is 10.11 mA,which is very close 

to the specified design value of 10 mA. 

In this example we have shown that the approximate design equations for the 

damping network and for the determination of the input ripple current yield very 

accurate results when compared with actual simulations. 

 

For the series damping branch in Fig. 8.14b,if L 

is chosen much larger than L 

,


Figure 8.17 (cont.) 

then,at resonance,R 

will effectively appear in series with L 

and will counteract 

the negative input resistance of the converter. In this case (see Problem 8.8) the 

overall Q is given by: 

Q 

L /C 

R 

 

R 

(8.65) 

L /C 

As in the case of the shunt damping, R 

is chosen such that Q 

1. Observe that 

in this case too it is not possible to design with a much lower Q 

by making R 

very large because that would effectively create a new,lower,undamped resonance 

formed by L 

and C 

. 

Example 8.6 In this example we shall design a series damping branch for the 

input filter of the buck converter in Example 8.5. In this case,we chose L about 

ten times larger than L so that we have: 

 

L 

10L 

860 μH (8.66) 

The value of the damping resistor is determined from Eq. (8.65): 

1 86/8.46 

R 

20.9 

86/8.46 R 3.67 Ω (8.67) 

 

An OrCAD/Pspice simulation of this circuit and its frequency response are 

shown in Figs. 8.18a and b. In comparison to the response of the shunt damping 

network,the peaking seems to be a little higher because this transfer function has a 

zero at about 617 Hz and a pole at about 824 Hz,whereas the shunt network has


Li 

86uH 

Rid 

3.67 

Lid 

860uH 

Vin 

Ci 

8.46uF 

Rin 

-20.9 

0 

Figure 8.18 

essentially a pole-zero cancellation at about 676 Hz (see Problems 8.7 and 8.8). 

A simulation run of the input ripple current yields a peak-to-peak ripple current 

of 11.14 mA,which is about 10% higher than the parallel-damped filter in the 

previous example. The reason for this slight increase is that,at the switching 

frequency,the pulsating current is divided between C and L L instead of C and 

 

L . (Here we have ignored the resistance of R with respect to the reactance of L at 

 

the switching frequency.) Since L 10L ,the reactance of their parallel combination 

is about 10% smaller than the reactance of L ,which is what accounts for the 

 

 

10% reduction in the ripple attenuation. Since L carries the dc input current,it 

 

may not be as economical as the shunt damping element for high input currents. 

The size and cost of an inductor increases with its inductance and its current 

handling capacity.


8.4 The boost converter 

By rearranging the filter elements around the switches in the buck converter we 

obtain different converters with different conversion ratio characteristics. All of 

these converters operate on the same basic principle of commutating the inductor 

current between the input and output circuits. When the elements of the buck 

converter are rearranged as shown in Fig. 8.19,we obtain the boost converter. The 

voltage and current waveforms of this converter are shown in Fig. 8.20. In this 

Figure 8.19 

circuit when S 

is turned on during T 

,while S 

is turned off,the inductor charges 

linearly from I 

to I 

and the output filter capacitor discharges into the load with 

a time constant much longer than T 

. When S 

is turned off and S 

is turned on 

during T 

,the current in the inductor discharges linearly from I 

to I 

into R 

and C. Since the capacitive reactance of C at the switching frequency is much lower 

than the load resistance,the ac component of the pulsating current in S 

is almost 

entirely absorbed by C while the dc component is absorbed by the load R 

. From 

the current waveforms in Fig. 8.20 we obtain the current conversion ratio: 

I 

DI 

M 

I 

I 

D (8.68) 

The voltage conversion ratio for the ideal boost converter follows immediately and 

is given by: 

M 

1 D 1 (8.69) 

Hence,in contrast to the buck converter,the output voltage of the boost converter 

is always larger than its input voltage. 

During the on-time,the inductor current charges up linearly with a slope V 

/L 

so that the peak-to-peak ripple current shown in Fig. 8.21 is given by:

387 8.4 The boost converter 

Figure 8.20 

I V 

L DT V DD 

F L 

(8.70) 

When I 

 

is normalized with respect to the average inductor current, I 

I 

,we 

obtain: 

δI I V DD 

 

I I F L V DD 

 

I F L 

 

(8.71) 

The peak value of the inductor current is given by: 

I 

I 

I 

2 

(8.72) 

Substituting Eqs. (8.68) and (8.70) in Eq. (8.72) we obtain: 

I 

V 

2LF 

DD I 

D 

(8.73) 

Hence,for a regulating converter in which V 

is a constant, I 

depends on I 

and D. 

In order to design the inductor,we need to know the operating conditions for 

which I 

is a maximum. Clearly,one of the operating conditions,according to Eq. 

Figure 8.21


(8.73),is that the load current be at its maximum value. To determine the value of 

D which causes I 

to be a maximum,we set its derivative with respect to D to zero 

and obtain: 

I 

D 0 (1 2D) 2LF I 

 

V D 0 (8.74) 

 

For typical designs,the average inductor current at maximum load is always larger 

than half the ripple current through it,so that according to Eqs. (8.72) and (8.73) 

we have: 

I 

V DD I 2LF 

D (8.75) 

D 2LF D V 

It follows that,for typical designs,there is no value of D which satisfies Eq. (8.74), 

and the maximum value of I 

occurs at D 

. Hence,the worst case value of the 

design parameter for the inductor,according to Eq. (8.71),is given by: 

δ 

δI 

2 

V 

2LF 

I 

 

D 

(1 D 

) (8.76) 

Practical values of δ 

range from 0.1 to 1.0. Expressing the duty cycle in terms of 

the conversion ratio in Eq. (8.76),we obtain the design equation for the inductor: 

L V M 1 1 

(8.77) 

2I M δ F 

 

The output voltage ripple can be easily determined from the on-time when the 

capacitor is discharging into the load as shown in Fig. 8.22. Since the output time 

constant is much shorter than the on-time,we can assume the capacitor discharges 

linearly and write: 

C ῀v 

῀t C V 

DT 

I 

(8.78) 

The normalized output voltage ripple follows: 

V 

I DT 

 

V V C 

(8.79) 

Clearly,the capacitor now must be chosen in such a way as to meet the specified 

output ripple voltage under worst case conditions which correspond to maximum 

load current and maximum duty cycle. Hence we have: 

δ V 

V 

I D 

 

V F C 

 

(8.80)


Figure 8.22 

Hence the design equation for the capacitor is given by: 

C I M 1 1 

(8.81) 

V M δ F 

Equation (8.79) is not very accurate at very light load currents as the current in the 

switches (assuming MOSFETs are used for both S and S ) begins to reverse. At 

 

zero load current Eq. (8.79) suggests that the output ripple voltage is zero,which 

certainly is not accurate (see Problem 8.9). 

Example 8.7 An OrCAD/Pspice simulation of a practical boost converter is 

shown in Fig. 8.23. The converter operates at 100 kHz and has a duty cycle of 

D 7/12. The inductor current and the output ripple voltage are shown in Fig. 

8.24 at I 0 A,1 A. The ideal output voltage is given by: 

 

V 5 12 V (8.82) 

1 7/12 

Since the MOSFETs have a finite resistance when turned on,the output voltage is 

slightly less than 12 V at I 

1A. 

According to Eq. (8.79),the output ripple voltage at full load is given by: 

V 

 

1 

(7/12)(10 10) 

117 mV (8.83) 

50 10 

which is in exact agreement with the ripple in Fig. 8.24a. At zero load current,we 

need to use the result derived in Problem 8.9: 

V 

 

V 

DDT 

8LC 

(1 7/12)(7/12)(10 10) 

12 

8(10 10)(50 10) 

(8.84) 

30 mV


L 

10uH 

M2 

IRF045 

PARAMETERS: 

R_load = 12 

5V 

Vin 

M1 

IRF045 

V_Dp 

C1 

50uF 

RL 

{R_load} 

V_D 

0 

Figure 8.23 

Figure 8.24


which is in exact agreement with the ripple in Fig. 8.24a. 

 

Example 8.8 If a feedback loop is added to the boost converter in the previous 

example to maintain the output voltage at 12 V as the input voltage varies from 

5 V to 10 V,then the maximum value of the peak current would occur at D and 

I 1 A (assuming the specified maximum load current is 1 A). The maximum 

 

and minimum values of D are given by: 

D 1 V 1 5 

V 12 0.5833 ⎫ 

 

⎬ 

(8.85a, b) 

D 1 V 1 10 

V 12 0.1666 

⎭ 

According to Eq. (8.73),the maximum peak current is given by: 

I V D (1 D ) 

2LF 

I 

12(7/12)(1 7/12) 

 

2(10 10)(100 10) 1 

1 7/12 

1 D 

(8.86) 

This is in agreement with the waveforms shown in Fig. 8.25 in which the 

inductor current is shown at D 

and D 

. 

Figure 8.25 

If this were an unconventional design,then the maximum specified load current 

would have been fairly low,say 60 mA. Also,if the converter had to operate from 

an input voltage range 3.5 V V 

10 V,then the range of D would have been


given by: 

0.1666 D 0.708 (8.87) 

In this case,Eq. (8.74) would yield the value of D at which the maximum value of I 

would occur: 

(1 2D) 2LF 

V 

I 

 

(1 D) 0 (8.88) 

A numerical solution of Eq. (8.88) yields D 0.483. The peak inductor current at 

D 0.483 is equal to 1.614 A,whereas at D 

0.708 it is equal to 1.445 A,as can 

be seen in Fig. 8.26 in which the inductor currents at D 

, D 

and D 0.483 are 

shown. 

Figure 8.26 

The purpose of this exercise was to demonstrate the use of Eq. (8.74) even 

though the difference in the peak currents between the two operating points is not 

significant. 

 

8.5 The buck-boost converter 

The converter shown in Fig. 8.27 is called the buck-boost because it is capable of 

either stepping up or down the input voltage. When S 

is closed and S 

is opened 

during the on-time,the inductor charges up linearly from I 

to I 

with a slope 

V 

/L,while the output capacitor discharges into the load with a slope I 

/C. When 

S 

is opened and S 

is closed during T 

,the inductor discharges into the output 

circuit with a slope V 

/L.

393 8.5 The buck-boost converter 

Figure 8.27 

The voltages and currents of the switches are shown in Fig. 8.28 whence we can 

immediately determine: 

I 

DI 

(8.89a, b) 

I 

DI 

⎫ 

⎬⎭ 

Figure 8.28 

Hence the current conversion ratio is given by: 

M 

I 

I 

D 

D 

(8.90) 

The ideal voltage conversion ratio follows immediately: 

M 

1 M 

D D 

(8.91) 

The output ripple voltage is determined in the same manner as the output ripple 

voltage of the boost converter and is given by Eq. (8.79). Substituting Eq. (8.91) in 

(8.79),we obtain:


V 

 

I 1 M 

 

(8.92) 

V V F C 1 M 

As in the case of the boost converter,this expression is not accurate at very light 

load currents (see Problem 8.10). 

The output filter capacitor must be chosen to meet the output ripple voltage 

specification, δ 

,under worst case conditions which,for a converter with a 

regulated output voltage,occurs when the load current and the conversion ratio 

are at a maximum. Hence,we have from Eq. (8.92): 

δ V 

V 

I 1 M 

 

(8.93) 

V F C 1 M 

The peak-to-peak ripple current in the inductor is determined from the on-time 

and is given by: 

I 

 

V 

DT 

L 

V 

F 

L 

1 

M 

1 

⎫ 

⎬ 

⎭ 

(8.94a, b) 

The average inductor current can be seen to be given by the sum of the average 

input and output currents so that when Eq. (8.94) is normalized with respect to the 

average inductor current,we obtain: 

δI I V 1 1 

 

I I F L (M 1) 

 

(8.95) 

The peak value of the inductor current is given by: 

I 

I 

I 

2 

I 

(1 M 

) V 

2F 

L 

1 

M 

1 

⎫ 

⎬ 

⎭ 

(8.96a, b) 

Clearly,one of the operating conditions which maximizes the peak current is the 

maximum load current. The other condition is the duty cycle,which can be 

determined by setting the derivative of I 

with respect to D to zero. This yields: 

I 

D 0 1 D 2F L 

V 

/I 

 

(8.97) 

For most typical designs,no value of D satisfies this condition so that the 

maximum value of the peak occurs at M 

 

. Hence we have:

395 8.5 The buck-boost converter 

I I (1 M ) V 1 

 

2F L M 1 

 

(8.98) 

It follows that the worst case design parameter for the inductor is given by: 

δ δI 

2 V 1 1 

 

I 2F L (M 1) 

 

(8.99) 

Typical values of δ 

range from 0.1 to 1.0. Hence,the design equations for the 

values of L and C of the buck-boost converter are given by: 

L V 

I 

 

1 

2F 

δ 

1 

(M 

 

1) 

C I 

V 

1 

F 

δ 

⎫ 

M ⎬⎭ 

 

1 M 

 

(8.100a, b) 

The input current of the buck-boost converter in Fig. 8.27 is pulsating and must 

be filtered as shown in Fig. 8.29. The design procedure of the input filter and its 

damping elements is the same as that of the buck converter. 

Figure 8.29 

Example 8.9 The buck-boost converter in Fig. 8.30 generates a 12-V output 

from a 5-V source. The load current varies from 0 to 1 A. The output ripple 

voltage and the inductor current at three different load currents are shown in Figs. 

8.31a and b below. 

The peak-to-peak ripple voltage according to Eq. (8.92) is given by: 

1 M 

V I 

F C 1 M 

1 

I 

(100 10)(50 10) 

12/5 

1 12/5 

(8.101) 

0.141I 

At I 

1 A,the peak-to-peak ripple voltage is computed to be 141 mV,which is 

very close to the observed value of 143 mV in Fig. 8.31a.AtI 

0.5 A,we compute


M1 

IRF045 

M2 

IRF045 

PARAMETERS: 

R_load = 12 

V_D 

V_Dp 

5V 

Vin 

L 

10uH 

C1 

50uF 

RL 

{R_load} 

0 

Figure 8.30 

Figure 8.31 

V 

 

70 mV,while the observed value is 76 mV. At no load current,we can no 

longer use Eq. (8.92) and we must use Eq. (8.278b),see Problem 8.10,instead. This 

yields: 

V V T 

 

8LC 

 

1 M

397 8.6 The Cuk converter 

12 10 10 

 

8(10 10)(50 10)1 12/5 (8.102) 

26 mV 

which is in close agreement with the 25 mV seen in Fig. 8.31a. 

Note that the output voltage in Fig. 8.31a changes slightly as a function of the 

load current because the converter is not regulated and the MOSFETs have a 

resistance of 15 mΩ when turned on with an 8-V gate-drive signal. 

 

8.6 The Cuk converter 

This converter,named after its inventor Slobodan Cuk — (pronounced chook),is 

shown in Fig. 8.32. The input loop,consisting of V 

, L 

and S 

,looks like a boost 

converter while its output loop,consisting of S 

, L 

and V 

,looks like a buck 

converter. The switching voltage and current waveforms are shown in Fig. 8.33. 

Since the dc current in the capacitor C 

must be zero,we have: 

I 

D I 

D (8.103) 

It follows that the current conversion ratio is given by: 

M D 

D 

The ideal voltage conversion ratio follows: 

M D D 

(8.104) 

(8.105) 

The output voltage,as in the case of the buck-boost converter,is inverted with 

respect to the input. An isolated output can be easily obtained by introducing a 

transformer between S 

and S 

(see Problem 8.11). 

Figure 8.32


Since the dc voltage across each of L 

and L 

is zero,as we go around the outer 

loop containing V 

, V 

, L 

, L 

and C 

,we find that the dc voltage across C 

is equal 

to V 

V 

. It follows that the voltage waveforms across L 

and L 

,excluding the 

ripple component of the voltages across C and C 

,are essentially identical,as 

shown in Fig. 8.33. The peak-to-peak ripple current in L 

and L 

can be determined 

from the on-time, DT 

: 

I 

 

V 

DT 

L 

; i 1,2 

V 

F 

L 

1 

M 

1 

⎫ 

⎬ 

⎭ 

(8.106a, b) 

An important feature of this converter is that L 

and L 

can be coupled as shown 

in Fig. 8.34 and the ripple current in either inductor can essentially be reduced to 

zero by adjusting the coupling coefficient. This can be shown by writing the 

equations for v 

(t) and v 

(t) in Fig. 8.34: 

Figure 8.33

399 8.6 The Cuk converter 

v 

(t) L 

di 

dt M di 

dt 

di 

v (t) L 

dt M di 

dt 

⎫ 

⎬ 

⎭ 

(8.107a, b) 

in which M is the mutual inductance between the windings. In the Cuk converter, 

if we ignore the ripple voltages on C 

and C,then v 

and v 

are identical so that we 

have from Eq. (8.107): 

(L 

M) di 

dt (L M) di 

dt 0 (8.108) 

We can deduce from this equation that: 

L 

M 0 di 

dt 0 (8.109a, b) 

L 

M 0 di 

dt 0 ⎫ 

⎬⎭ 

Figure 8.34 

The disappearance of the derivative of the current implies that the current ripple is 

reduced to zero. Hence,if the mutual inductance is set according to Eq. (8.109a), 

then the ripple current in L 

is reduced to zero. This can be expressed in terms of 

the coupling coefficient: 

L 

M 0 L 

kL 

L 

0 k L 

L 

1 (8.110) 

This result states that if we want to null the ripple current in L 

,we must make L 

smaller than L 

so that we can adjust k to be equal to L 

/L 

. The coupling 

coefficient can be set by adjusting the air gap between the two cores. Similarly,we 

see from Eq. (8.109) that the ripple current in L 

can be reduced to zero if we set


k L 

/L 

,in which case L 

has to be made smaller than L 

. 

In an isolated Cuk converter, it is possible to reduce the ripple currents in both 

inductors to zero by coupling them to the isolation transformer. In reality,the 

ripple current is not exactly reduced to zero but is highly reduced. The reason for 

this is that the voltage across the inductors are not exactly identical because of the 

ripple voltage across the capacitors. 

8.7 The PWM switch and its invariant terminal characteristics 

The active and passive switches in the four converters discussed earlier can be 

lumped together in a single-pole—double-throw switch called the PWM switch, as 

shown in Fig. 8.35. The terminals designations a, p and c refer to active, passive and 

common,respectively. The common terminal is designated as such simply because 

it is common to both switches. All of the four converters discussed earlier are 

redrawn in Fig. 8.36 with the PWM switch identified as a three-terminal switching 

device. The important thing to see in this figure is that all the elements outside the 

PWM switch are linear passive elements which provide filtering,whereas the 

PWM switch is the only nonlinear element which performs the dc-to-dc conversion 

process. We shall capitalize on this point and show that the conversion 

process in the PWM switch is independent of the particular converter in which it 

occurs and can be described by a set of invariant equations. This invariance will 

lead to a very simple model of the PWM switch which can be used towards the 

determination of the dynamics of any (two switched-state) PWM converter. 

Figure 8.35 

We begin with a qualitative study of the invariance of the terminal voltages and 

currents of the PWM switch. The active terminal current is the current in the 

active switch S 

which has the invariant shape shown in Fig. 8.37a. By invariance 

we simply mean that one cannot tell which converter the active switch is in by 

looking at its current waveform. The common terminal current is the same as the 

total switched inductive current in the converter and has the invariant shape shown 

in Fig. 8.37b. For example in the Cuk converter,the current in the common 

terminal is the sum of the currents in the two switched inductors L 

and L 

. The 

inductor in the input filter of a buck converter is an example of an inductor which is

401 8.7 The PWM switch: invariant terminal characteristics 

Figure 8.36 

not switched. Hence,in the buck converter with an input filter,the common 

terminal current is the same as the current in the output filter inductor only and 

not the sum of the currents in the input and output filter inductors. Next we 

examine the port voltages of the PWM switch. Ignoring ripple voltages,the 

voltage across port ap in all the converters is a dc voltage while the voltage across 

port cp is a pulsating voltage,as shown in Figs. 8.37c and d. We can now write the 

following set of invariant equations for the terminal currents and port voltages of 

the PWM switch: 

i 

(t) d (t)i 

(t) (8.111a, b) 

v 

(t) d (t)v (t) ⎫ 

⎬⎭ 

Figure 8.37 

in which d (t) is the switching function defined in Eq. (8.16). These equations 

 

describe the entire switching action responsible for the dc-to-dc conversion process 

in a converter. By taking the time average of Eqs. (8.111a,b) we obtain the


following invariant average equations for the PWM switch: 

i 

di 

(8.112a, b) 

v 

dv 

⎫ 

⎬⎭ 

These are the invariant equations that describe the dc-to-dc conversion function of 

any two switched-state PWM converter in continuous conduction mode. 

If we allow for small-signal variations in the duty-ratio function and other 

voltages and currents in the converter about a steady-state operating point,then 

the propagation of these variations through the PWM switch can be determined 

by taking the differentials in Eqs. (8.112a, b): 

î Diˆ I d ⎫ 

⎬⎭ 

(8.113a, b) 

vˆ 

Dvˆ V d 

in which D, I 

and V 

are the steady-state dc operating points of the PWM switch 

which satisfy Eqs. (8.112a, b),i.e. I 

DI 

and V 

DV 

. 

8.8 Average large-signal and small-signal equivalent circuit models of 

the PWM switch 

An equivalent circuit model for Eqs. (8.112a, b) can most easily be constructed 

using dependent sources,as shown in Fig. 8.38. This is a nonlinear average model 

because it involves products of the time functions d(t)i (t) and d(t)v (t). This is also 

 

a large-signal model because it places no restriction on the magnitude of variations 

in the time functions. For small-signal variations,we can use the linearized 

small-signal equations in (8.113a, b) to construct the equivalent circuit model in 

Fig. 8.39a or b. In Fig. 8.39b the dependent sources Dî and Dvˆ have been replaced 

 

with a 1: D transformer and the control source d V has been moved from the 

 

common terminal side to the active terminal side. Note that the small-signal 

sources are evaluated at the dc operating point. Under steady-state conditions,the 

large- and small-signal models reduce to the same transformer model shown in 

Fig. 8.40. 

The model of the PWM switch is used very much in the same way as the 

Figure 8.38

403 8.8 Large- and small-signal equivalent circuit models 

Figure 8.39 

Figure 8.40 

equivalent circuit model of a transistor or a vacuum tube. First,the device is 

replaced point-by-point with its equivalent circuit model and a dc analysis is 

carried out to determine the operating point (D, I , V ). As usual,in a dc analysis 

 

all reactive elements and small-signal sources vanish. Second,the small-signal 

analysis is carried out using the small-signal model of the PWM switch evaluated 

at the dc operating point. As usual,in an ac analysis,all dc sources vanish. In a 

small-signal analysis,one of the most commonly determined transfer functions is 

the control-to-output transfer function: 

H (s) vˆ (s) 

(8.114) 

d (s) 

This transfer function is necessary for the design of a stable feedback loop for a 

converter whose output voltage is regulated. Other transfer functions of interest 

are the line-to-output transfer function and the input and output impedances. The 

line-to-output transfer function relates variations in the output voltage to variations 

in the input voltage: 

H (s) vˆ (s) 

vˆ 

(s) (8.115)


Ideally,for a regulating converter H 

(s) must be zero because the input voltage is 

simply a disturbance in the closed-loop system which the feedback circuit must 

attenuate and prevent from reaching the output. 

Example 8.10 

For the buck-boost converter in Fig. 8.41,determine: 

(i) The voltage conversion ratio. 

(ii) The control-to-output transfer function. 

(iii) The line-to-output transfer function. 

(iv) The input admittance. 

(v) The output impedance. 

Figure 8.41 

The complete dc and small-signal equivalent circuit model of the buck-boost 

converter is obtained by replacing the PWM switch with its equivalent circuit 

model as shown in Fig. 8.42. To determine the conversion ratio,we perform a dc 

analysis by setting all the small-signal sources to zero,shorting the inductors and 

opening all the capacitors,as shown in Fig. 8.43. 

In Fig. 8.43,we can see that the voltage across port ap is simply V 

/D so that 

writing KVL around the outer loop we obtain: 

V V D V V 1 D 

D 

V D 

D 

(8.116) 

The voltage conversion ratio follows immediately: 

M 

V 

V 

D D 

(8.117) 

Hence,we see how the invariant conversion function 1: D of the PWM switch can 

produce the conversion ratio D/D of the buck-boost converter by a simple 

rotation of the PWM switch. Before going to the small-signal analysis,we should 

determine the dc operating point of the PWM switch. The quiescent commonterminal 

current is given by: 

I 

I 

I 

I 1 1 M 

I 1 D D I 

D 

(8.118)


Figure 8.42 

Figure 8.43 

This establishes I 

in terms of the output current of the converter,which can be 

expressed in several different convenient forms using the results of the dc analysis: 

I I D V /R 

D 

V 

R 

D 

D 

(8.119) 

The quiescent port voltage V 

is readily seen to be V 

/D,which can be expressed in 

terms of the input voltage: 

V V D V 

(8.120) 

D 

All of the small-signal transfer functions have the same denominator which can 

be determined by setting all the independent excitations in Fig. 8.42 to zero as 

shown in Fig. 8.44a. The 2-EET can now be applied by taking out the inductor and 

the capacitor as shown in the reference circuit in Fig. 8.44b. The following port 

resistances required for the 2-EET are determined in reference to Fig. 8.45: 

R DR 

R 0 

(8.121a—c) 

R 

R 

⎫ 

⎬⎭


Hence,the denominator is given by: 

D(s) 1 sL 

sL 

sCR 

R R sCR 

L LC 

1 s s 

DR D 

(8.122) 

Figure 8.44 

Figure 8.45


The line-to-output transfer function and the input admittance are determined 

by retaining only the small-signal source vˆ in the complete equivalent circuit 

 

model in Fig. 8.42 and examining the transform circuit for nulls in the response of 

the particular transfer function. For the line-to-output transfer function we see in 

Fig. 8.46 that there are no conditions in the transform circuit which result in a null 

in the response vˆ (s) so that the line-to-output transfer function is given by: 

 

H (s) vˆ (s) 

vˆ 

(s) M 1 

D(s) D 1 

(8.123) 

D L LC 

1 s s 

DR D 

in which M 

is clearly the low-frequency asymptote of H 

(s). 

The input admittance function is given by: 

G (s) iˆ (s) 

vˆ 

(s) G N (s) (8.124) 

D(s) 

in which G is the low-frequency asymptote of the input conductance discussed 

 

earlier and shown in Fig. 8.3. Hence we have: 

G 

M 

R D D 1 R 

(8.125) 

The numerator N (s) corresponds to conditions of the transform circuit that 

 

results in a null in the response î (s). Referring to Fig. 8.46,we see that a null in 

 

either iˆ 

(s) orî (s) would result in a null in î (s) simply because when one of the 

 

terminal currents of the 1: D transformer vanishes,the other two vanish as well. 

The impedance encountered by î (s) is: 

R 

1 sCR 

(8.126) 

Figure 8.46


The pole at s 1/RC corresponds to an ‘‘open-circuit’’ in the transform domain,which 

results in a null in î (s) and,hence,in iˆ 

(s). It follows that s 1/RC 

is a zero of G (s) and that N (s) 1 sCR. Hence,the input admittance is given 

 

 

by: 

G (s) D 1 1 sCR 

D R L LC 

1 s s 

DR D 

(8.127) 

The impedance encountered by iˆ (s) issL,which has no poles and hence does not 

 

contribute a zero to iˆ 

(s). 

The output impedance is determined from the equivalent circuit shown in Fig. 

8.47,whence we see that a zero of the impedance in the common terminal branch 

would cause the terminals a and c to be at the same potential,which in turn would 

require that the voltages on both sides of the 1: D transformer be the same,which 

could only happen if vˆ (s) 0. The impedance connected to terminal c is sL,which 

 

has a zero at the origin,so that the output impedance must have a zero at the 

origin too. Hence we have: 

Z 

(s) vˆ (s) 

î 

(s) sLk 

D(s) 

(8.128) 

in which k is a constant,which can be determined by examining the circuit. It can 

be seen from Fig. 8.47 that at high frequencies we have: 

lim Z (s) 1 

(8.129) 

sC 

 

Substituting this result in Eq. (8.128),we obtain k 1/D,and the output impedance 

can be written as: 

sL/D 

Z (s) L LC 

1 s S 

DR D 

(8.130) 

Figure 8.47


Finally,we determine the control-to-control transfer function by retaining the 

control sources as shown in Fig. 8.48. This transfer function can be written as: 

H (s) vˆ (s) 

d (s) H N (s) 

D(s) 

(8.131) 

The low-frequency asymptote, H 

,is simply the derivative of the output voltage 

with respect to the duty ratio and is given by: 

H 

dV 

dD V 

D (D) 

D 

V 

D 

(8.132) 

The numerator, N (s),is determined by examining the transform circuit for a null 

 

in the output voltage. This is shown in Fig. 8.49 in which we see that the only way 

to have a null in vˆ (s) is to have a null in iˆ 

(s). With vˆ (s) î (s) 0,from Fig. 8.49 

 

we have: 

î (s) iˆ (s) ⎫ 

⎬⎭ 

(8.133a, b) 

vˆ 

(s) 0 

Figure 8.48 

Figure 8.49


Hence: 

î (s)sL 

D 

V 

D d ⎬ 

(8.134a, b) 

Dî I d î ⎫ 

Solving these we obtain: 

1 s L D 

⎭ 

I 0 N (s) 1 s L I 

(8.135) 

V D V 

Substituting for I 

and V 

from the operating point determined earlier in Eqs. 

(8.119) and (8.120),we obtain: 

N 

(s) 1 s L D 

I 

D 

D 

V 

(8.136a, b) 

1 s L R 

D 

D 

Hence,the control-to-output transfer function has a RHP zero and is given by: 

H 

(s) V 

D 

1 s L R 

D 

D 

(8.137) 

L LC 

1 s s 

DR D 

The presence of the RHP zero in H (s) above implies that the output voltage 

 

momentarily dips before rising when the duty cycle is increased abruptly (step 

function). The physical explanation for this is that an abrupt increase in the duty 

cycle d causes an abrupt decrease in d,which in turn causes an initial decrease in 

the average terminal current i (t) because the average inductor current cannot 

 

reach its higher steady-state value instantaneously. It is this momentary decrease 

in i (t) that causes the initial dip in the output voltage. In fact,we can use this 

 

physical explanation to determine the RHP zero as follows. Let us assume that the 

RHP zero in Eq. (8.137) is ω so that its high-frequency response is given by: 

 

H 

(s) V 

D 

s/ω 

s LC 

D 

 

V 

sω LC 

(8.138) 

The initial response to a step increase, ῀,in the duty cycle is then given by: 

vˆ 

 

(s) d (s) 

V 

 

sω LC ῀ V 

s sω LC 

 

(8.139)

411 8.9 The PWM switch in other converter topologies 

Taking the inverse Laplace transform,we have: 

vˆ 

(t) ῀ V 

ω 

LC t (8.140) 

Next,we look at the circuit to determine the initial response to a sudden increase 

in the duty cycle by an amount We can see from Fig. 8.50 that the passive 

῀. 

terminal current i (t) for the first few cycles experiences a step reduction in its 

 

average value by an amount: 

I 

δi 

῀ D 

(8.141) 

Figure 8.50 

This sudden reduction in the average current is absorbed by the output capacitor 

so that the change in the output voltage is given by: 

C dv 

dt ῀ 

I 

D vˆ I 

(t) ῀ 

C D t (8.142) 

Comparing Eqs. (8.140) and (8.142),we determine the RHP zero: 

ω 

DV 

I 

L DV 

DI 

L DR 

DL 

which is the same as the RHP in Eq. (8.137). 

(8.143) 

 

8.9 The PWM switch in other converter topologies 

The three different types of conversion ratios we have seen so far, D,1/D and D/D, 

were generated by the three possible orientations of the PWM switch. It is possible 

to generate other types of conversion ratios by arranging the switches differently, 

using tapped inductors or inverting transformers,and using more switches. In all 

such converters,the PWM switch can be identified after a few simple circuit 

manipulations. In this section,we shall consider four such converters which cover 

most known types of basic topological variations.


Any of the basic converters discussed earlier can be modified by tapping the 

inductor and connecting one of the two switches to the tap point. The two 

variations of the tapped buck converter are shown in Figs. 8.51a, b. 

Figure 8.51 

The PWM switch cannot be identified directly in these converters because the 

common terminal,through which the inductive current flows,is lost. Since S and 

V are in series,one may interchange their positions and establish a common point 

 

between S and S and incorrectly identify the PWM switch. The mistake here is 

 

that the current through this common point is i (t),which is not a purely inductive 

 

current and has the shape shown in Figs. 8.51a,b. Immediately we recognize that 

the tapped inductor in these converters is actually acting as an auto-transformer so 

that the current i is actually a winding current rather than a magnetizing or 

 

inductive current. In order to recover the inductive current,we replace the tapped 

inductor with an untapped inductor L and an ideal transformer with the same 

turn-ratio as the tapped inductor as shown in Fig. 8.52a. The energy stored in L is 

the inductive energy of the converter and the current in L is the inductive current 

in the converter. The PWM switch can now be identified by moving S to the 

opposite side of the ideal transformer as shown in Fig. 8.52b. Now,the common 

terminal between S and S clearly carries a purely inductive current. The dc and 

 

small-signal characteristics can be determined by replacing the PWM switch with 

its equivalent circuit model as explained in the following example. 

Example 8.11 The voltage conversion ratio of the tapped buck converter is 

determined by replacing the PWM switch with its dc model as shown in Fig. 8.53. 

By applying KVL around the loop shown,we obtain:


Figure 8.52 

V 

V 

nD V 

n V 

(8.144) 

from which the voltage conversion ratio is obtained: 

M 1 

 

1 D 

nD 

(8.145) 

The operating point of the PWM switch is given by: 

V V nD V 

nD D 

I I D M I 

D 

⎫ 

⎬ 

⎭ 

(8.146a, b) 

The advantage of tapping the inductor can be immediately seen from Eq. (8.145) 

in which we see that by letting n 1 we can obtain large step-down conversion 

Figure 8.53


ratios without making the duty cycle too small. For example,we can convert 120 

to 5 V by making D 0.25 and n 3/23. 

The control-to-output transfer is obtained by replacing the PWM switch with 

its small-signal equivalent circuit model as shown in Fig. 8.54,in which the input 

dc voltage is set to signal ground. This transfer function is given (see Problem 8.12) 

by: 

1 s ω 

H (s) H 

 

1 s 

ω Q s 

(8.147) 

ω 

in which: 

H 

V (nD D) 

ω DR 1 

ML 

n 1 

ω 

D M 

1 

LC 

Q R 

ω 

L D M 

 

⎫ 

⎬ 

⎭ 

(8.148) 

Figure 8.54 

Note that for n 1,the zero is in the LHP,while for n 1,zero is the RHP. The 

reason for this is the same as that for the buck-boost converter given earlier (see 

Problem 8.12). 

 

Another topological variation is shown in Fig. 8.55,in which an inverting 

transformer is used. This converter,sometimes referred to as the Watkins— 

Johnson converter,is analyzed in the same way as the tapped buck converter. 

This is shown in Fig. 8.56,in which the inverting transformer is replaced with its


equivalent circuit model and S 

is moved to the N 

-side of the transformer in order 

to identify the PWM switch. 

The complete equivalent circuit is the same as that of the tapped buck converter 

except for the 1: n transformer,which in this case is inverting. It follows that the 

voltage conversion ratio is the same as that of the tapped buck converter given in 

Eq. (8.145) with n replaced by n: 

M 

1 

1 D 

nD 

(8.149) 

Figure 8.55 

Figure 8.56 

A plot of M 

for n 1 is shown in Fig. 8.57,in which we notice that not only the 

conversion ratio becomes singular at D 0.5 but also the polarity of the output 

voltage changes. It is relatively easy to show that M 

becomes zero,and not 

infinite,at D 0.5,if the slightest parasitic resistance is included in the circuit (see 

Problem 8.13). By interchanging the source and load,another variation of this 

converter can be obtained,as shown in Fig. 8.58,whose conversion ratio monotonically 

increases from negative to positive values passing through zero at 

D 0.5 (see Problem 8.14). 

By rearranging the switches in a fourth-order converter,such as the Cuk 

converter,one can obtain new converters such as the one shown in Fig. 8.59a. In 

such a converter,the PWM switch cannot be identified immediately,but a simple 

circuit transformation can do the trick. The idea,of course,is to move one of the 

switches without altering the operation of the circuit. This is shown in Fig. 8.59b in


Figure 8.57 

Figure 8.58 

Figure 8.59


which S 

is lifted from the input side and brought to its new position while 

maintaining the same potential difference across it with the help of the dependent 

source V 

. To preserve the input current,the dependent current source I 

is 

introduced. The PWM switch is identified in Fig. 8.59c simply by interchanging 

the positions of S 

and v 

. The voltage conversion ratio is determined by replacing 

the PWM switch with its dc model as shown in Fig. 8.60 in which,going around 

the outer loop,we have: 

V V V V V (8.150) 

D 

It follows that the conversion ratio is given by: 

M 

1 2D 

D 

(8.151) 

A plot of M 

is shown in Fig. 8.61,which shows that the polarity of the output 

voltage changes as the duty cycle is increased beyond 0.5. 


Figure 8.60 

It is possible to cascade any two basic converters to obtain an ideal conversion 

ratio which has a quadratic dependence on the duty cycle. Furthermore,it is 

possible to rearrange the switches in a cascaded converter in such a way to drive 

only a single active switch instead of two. The formal synthesis procedure of such 

converters has been reported by Maksimovich and Cuk and one such converter is 

shown in Fig. 8.62. In this converter, D 

turns on in synchronism with the main 

active switch S 

during T 

,while D 

and D 

are turned off. During T off 

, D 

turns


Figure 8.61 

off in synchronism with S 

,while D 

and D 

are turned on together. For purposes 

of analysis in continuous conduction mode,the nature of these switches is immaterial. 

Our aim is to analyze this converter using the model of the PWM switch, 

which clearly cannot be identified directly. Since the PWM switch is applicable to 

all converters that are switched between two states,all we need to know are the 

two states of the converter during T 

and T off 

. These are shown in Fig. 8.63a. In 

Figure 8.62 

Fig. 8.63b,the on-state is redrawn by separating the L 

and L 

loops using the 

dependent sources V 

and I 

. The purpose of I 

in shunt with V 

is to preserve 

the input current I 

. The off-state is redrawn simply by interchanging the positions 

of L 

and C 

. We can now see that the on- and off-states in Fig. 8.63b correspond 

to the operation of two buck converters connected in cascode as shown in Fig. 

8.63c. The PWM switch in each converter is clearly identified and the complete dc 

and small-signal equivalent circuit model is shown in Fig. 8.64. 

Example 8.12 To determine the voltage conversion ratio of the converter in Fig. 

8.62 we set all the small-signal sources to zero,short the inductors,and open the 

capacitors in the equivalent circuit in Fig. 8.64. This yields the circuit in Fig. 8.65, 

whence we have for the first PWM switch:


Figure 8.63 

Figure 8.64


V DV (8.152) 

 

For the second PWM switch we have: 

V V V V (DV ) V (1 D) (8.153) 

 

The output voltage is given by: 

V V V DV V (8.154) 

 

Substituting Eqs. (8.152) and (8.153) in (8.154),we obtain: 

V DV (1 D) DV DV (8.155) 

 

Hence,the voltage conversion ratio is given by: 

M D (8.156) 

 

Figure 8.65 

The dc operating point of each PWM switch is determined before performing 

the small-signal analysis. For the first and second PWM switches we have: 

V V 

I I DI DI 

V V (1 D) 

 

I 

V 

R DV 

R 

⎫ 

⎬ 

⎭ 

The control-to-output transfer function has the following form: 

(8.157a—d) 

H (s) vˆ (s) 

d (s) H N (s) 

D(s) 

(8.158) 

in which H 

is the low-frequency asymptote and is given by:


H 

dV 

dD 2DV 

(8.159) 

The denominator is obtained by the application of the 4-EET to the reference 

circuit in Fig. 8.66,whence we have by inspection: 

R R 0 ⎫ 

⎬ 

R R ⎭ 

(8.160a, b) 

Figure 8.66 

From Fig. 8.67 we have: 

R R D 

(8.160c) 

Since L 

is connected across port (4) and L 

is connected across port (3),we shall 

renumber them after their port numbers to make the writing of the terms in the 

4-EET easier. Hence,we shall temporarily reassign L 

and L 

: 

L 

L 

; L 

L 

The fourth-order denominator is given by: 

D(s) 1 a 

s a 

sa 

sa 

s (8.161) 

Figure 8.67


Substituting for R in the coefficient a 

,we obtain: 

a 

RC 

RC 

L 

R L 

R 

L DL 

R 

(8.162) 

Since the reference circuit is almost purely reactive,we should expect indeterminate 

forms in the higher-order coefficients. We shall remove these indeterminate 

forms by changing the order of the ports. The coefficient a 

is given by: 

a RC R 

C RC L L RC 

R R 

 

L L 

RC RC 

R R 

 

By inspection of Fig. 8.66,we have: 

L 

R 

L 

R 

 

(8.163) 

R 

R R R 0 

⎫ 

R 

 

⎬⎭ 

(8.164a—c) 

R 

R 

It follows that the first two terms and the last term in the expression of a are all 

zero and the remaining terms in the middle have an indeterminacy of the form 0/0, 

which can easily be removed by changing the order in which the ports are taken: 

a 

L 

R R C L 

R R C L 

R R C 

(8.165) 

Once again by inspecting Fig. 8.66,we have: 

⎫ 

⎬⎭ 

R 

R 

R 

R 

R 

R 

Substituting these in Eq. (8.165),we obtain: 

(8.166a—c) 

a 

L 

C 

(L 

DL 

)C 

(8.167) 

The coefficient a 

is given by: 

a RC R 

C L RC R 

R C L 

R


RC 

L 

R 

 

L 

R 

 

RC 

L 

R 

 

L 

R 

 

in which we can determine the following by inspection: 

(8.168) 

R 

R R 0 

R 

(8.169) 

 

The indeterminacy in the first term of a is removed by changing the order of the 

 

ports from 1,2,3 to 1,3,2. Using the fact that R 0,we obtain: 

 

RC R C L L RC R 

R R C 0 (8.170) 

 

The indeterminacy in the second term of a is removed by changing the order of 

 

the ports from 1,2,4 to 4,1,2. Using the fact that R 

0: 

RC R C L L 

R R R C R C 0 (8.171) 

 

In the third term of a ,the indeterminacy is removed by changing the order from 1, 

 

3,4 to 4,1,3. Using the fact that R R,we obtain: 

 

L L 

RC L 

R R R R 

 

C 

L L L C 

R R 

 

(8.172) 

In the last term of a ,the indeterminacy is removed by changing the order from 2, 

 

3,4 to 3,2,4. Using the fact that R 

: 

L L 

RC L 

R R R R C L 0 (8.173) 

R 

 

 

Hence, a is given by: 

 

a 

L 

C 

L 

R 

(8.174) 

Finally,we obtain a 

by continuing the order in a 

: 

a 

L 

R R 

C 

L R 

R C L C L 

R RC 

 

(8.175) 

Substituting for a 

in Eq. (8.161) and reverting the notation to L 

and L 

from L 

and L 

,we obtain the denominator: 

D(s) 1 s L DL s[L C (C DC )L ] 

R


sL 

C 

L 

R sL L C C 

(8.176) 

This denominator can be factored into the product of two quadratics: 

D(s) 1 s s 

ω Q ω 

1 s s 

(8.177) 

ω Q ω 

 

whose frequencies and damping factors are approximately given by: 

1 

ω L C (C DC )L 

R 

Q ω (L DL ) 

 

ω 1 1 

 

L C L C C 

D 

Q 

RC ω C L 

ω 1 ω 

(8.178) 

The approximations for ω and ω are fairly good when they are separated by a 

 

factor of 2.5 or better. The second Q-factor, Q ,generally is very high and the 

 

accuracy of its approximation above is only moderate. In a real converter, Q is a 

strong function of parasitic resistances,so that the accuracy of Eq. (8.178d) is not 

very relevant. 

The numerator is determined by studying the nulls of vˆ (s) as shown in Fig. 8.68 

 

in which we see that a null in vˆ 

(s) requires a null in î (s) which in turn requires 

 

î (s) I d (s). It follows that the transform voltage across C is given by: 

 

vˆ 

(s) V d 1/sC 

sL 

1/sC 

I 

d [sL 

(1/sC 

)] 

d 

V 1 

sL 

I 

1 sL C 1 sL C 

 

(8.179) 

This transform voltage must be the same as the transform voltage across the 

D-side of the second PWM switch so that we have: 

vˆ 

(s) V 

D d vˆ (s) D (8.180) 

Equations (8.179) and (8.180) yield:


DV 

1 

1 sL 

C 

DI 

sL 

1 sL 

C 

V 

0 (8.181) 

Multiplying out and substituting for V 

, V 

and I 

in Eq. (8.157),we obtain the 

numerator: 

DD 

N (s) 1 sL 2R sL C 1 D 

2D 

(8.182) 

Figure 8.68 

We can rewrite this in standard quadratic form: 

N (s) 1 

s s 

(8.183) 

ω Q ω 

in which: 

ω 

1 

L 

C 

2 

1 1/D 

Q 

R 1 

L /C 

DD 1 D 

2D 

⎫ 

⎬ 

⎭ 

(8.184a, b) 

To summarize,the control-to-output transfer function is given by: 

1 s s 

ω Q ω 

H (s) H 

 

1 

s s 

ω Q ω 

1 s s 

ω Q ω 

 

(8.185)


A plot of H 

(s) using numerical values is discussed in Problem 8.15. 

 

8.10 The effect of parasitic elements on the model of the PWM switch 

The four important parasitic elements in a converter that affect the average model 

of the PWM switch are: 

(a) the high-frequency resistance across port a—p 

(b) the on-resistance of the switches 

(c) the storage-time modulation in bipolar transistors 

(d) the general saturation characteristics of the switches. 

These parasitic elements affect only the relationship between the average port 

voltages of the PWM switch but not its average terminal currents. In this section, 

we shall formulate their effect in an invariant way and model them by a resistor in 

series with the common terminal of the PWM switch. The first of these parasitic 

elements is the most subtle because it concerns the general problem of modeling 

the nonlinear part of a system (in our case the PWM switch) by separating it from 

its linear part. Naturally,the accuracy of such a modeling technique depends on 

how carefully the quantitative interaction between the linear and nonlinear parts 

is accounted for when separating both parts. In the absence of parasitic elements 

and in continuous conduction mode there is no quantitative interaction between 

the linear elements of the filter and the average voltages and currents of the PWM 

switch,so that the switch can easily be separated from the rest of the circuit and 

modeled accurately. In the presence of certain parasitic elements,a small amount 

of interaction between these elements and the average voltages and currents of the 

PWM switch exists which warrants a refinement of the ideal models in Figs. 8.38 

and 8.39. 

(a) The high-frequencyresistance across port a–p The pulsating active terminal 

current, i (t),in a converter is absorbed entirely by those elements which lie 

 

between terminals a and p of the PWM switch. All other elements lying between 

terminals c and p absorb the continuous inductive current in the common terminal. 

Hence,if i 

(t) encounters a resistance r it will give rise to a pulsating voltage 

 

ripple, r i (t),which will be superimposed on top of the smooth voltage across port 

 

a—p. To determine r ,one simply shorts the capacitive and input voltage ports, 

 

opens the inductive ports and determines the resistance between terminals a and p. 

This is best illustrated by examples. For the buck converter with an input filter 

shown in Fig. 8.69a, r is equal to the parasitic equivalent series resistance (ESR) of 

 

the input filter capacitor,i.e. r r . For the buck-boost converter with an input 

 

filter shown in Fig. 8.69b, r r R r . For the converter in Fig. 8.59 and for

427 8.10 The effect of parasitic elements on the model of the PWM switch 

the Cuk converter in Fig. 8.32, r r . For other converters, r is determined in a 

 

similar manner (see Problem 8.16). 

In all cases,we see that the high-frequency parasitic resistance across port a—p is 

due to the ESR of the filter capacitors connected effectively across that port. Since 

the pulsating current is absorbed by the filter capacitors,the ripple voltage it 

generates is balanced about the average value of the port voltage V as shown in 

 

Fig. 8.70. There is of course another ripple component in the port voltage v 

(t) 

(not shown in Fig. 8.70) which is essentially a triangular one and due to the 

capacitance,as explained earlier and shown in Fig. 8.22. The main difference 

between these two ripple components is that the average value of the capacitive 

ripple component in Fig. 8.22 is zero in each subinterval, T and T ,whereas the 

 

average value of the ripple due to the ESR in Fig. 8.70 is zero only over the entire 

switching interval, T ,and not over each subinterval. Hence,the average value of 

 

v 

(t) during T is not equal to the average value of v (t) over T ,which is simply 

 

the average value v 

(t). According to Fig. 8.70,the average value of v (t) during 

 

T is given by: 

 

Figure 8.69


v 

(t) v di r 

(8.186) 

All we have to do now is fix the relationship between the average values of the 

voltages across ports a—p and c—p: 

v dv (t) 

dv ddi r 

(8.187) 

The relationship between the average terminal currents i 

and i 

remains unaffected 

and is still given by i 

di 

. The interaction term, ddi 

r 

,can now be easily 

modeled by a parasitic resistance ddr 

in series with the common terminal in the 

large-signal average model of the PWM switch,as shown in Fig. 8.71. The 

small-signal model is obtained by perturbing Eq. (8.187): 

vˆ 

Dvˆ V d iˆ 

r DD (8.188) 

 

in which: 

V 

V 

I 

r 

(D D) V 

(8.189) 

The relationship between î and iˆ remains unaffected and is still given by Eq. 

 

(8.116a). The dc and small-signal model corresponding to Eqs. (8.188) and (8.116) 

now follows and is shown in Fig. 8.72. 

(a) 

(b) 

(c) 

Figure 8.70


Figure 8.71 

Figure 8.72 

(b) The on-resistance of the switches When MOSFETS are used to realize the 

active and passive switches,the effect of their finite on-resistance can easily be 

incorporated in the model of the PWM switch. Let r and r be the resistances of 

 

the active and passive switches of the PWM switch,respectively,as shown in Fig. 

8.73. Intuitively,one can see that since the common terminal spends D% of its time 

in series with r and D% of its time in series with r ,the effective resistance 

 

appearing in series with the common terminal must be Dr Dr . We can verify 

 

this by re-examining the relationship between v and v . We can see from Fig. 

 

8.73 that during T the voltage across port c—p is less than v by a factor of i r , 

 

while during T it is less than zero by a factor of i r . It follows that the 

 

relationship between v and v is: 

 

v d(v i r d i r ) di r ⎫ 

⎬ 

(8.190a, b) 

dv i (r dd dr dr ) ⎭ 

 

This result is consistent with our expectation,so that the effect of r 

and r 

can be 

modeled by adding another parasitic resistor, dr 

dr 

,in series with ddr 

in the 

Figure 8.73


average large-signal model of the PWM switch in Fig. 8.71. The small-signal 

model is determined by perturbing Eq. (8.190) and obtaining: 

vˆ 

Dvˆ V d i r 

in which: 

V V I [r (D D) r r ] ⎫ ⎬⎭ 

r 

DDr 

Dr 

Dr 

(8.191) 

(8.192) 

Since the relationship between iˆ 

and iˆ is still given by Eq. (8.116),the small-signal 

 

model corresponding to Eqs. (8.191) and (8.116a) looks the same as in Fig. 8.72 in 

which V is given by Eq. (8.191b) and Dr Dr is added to DDr . 

 

(c) The storage-time modulation of BJTs When a bipolar junction transistor is 

used to realize the active switch,the modulation in the duty ratio at the collector 

generally differs from the modulation in the duty ratio applied to the base of the 

BJT. It has been shown that: 

d d 

in which: 

î 

I 

(8.193) 

d modulation in the duty ratio at the collector of the BJT 

d modulation in the duty ratio applied to the base of the BJT 

(8.194a—c) 

I modulation parameter 

 

⎫ 

⎬ 

⎭ 

The modulation parameter has a negative value for constant base drive and a 

positive value for proportional base drive. More sophisticated types of base drive 

can render the value of I infinite so that d d . Since storage-time modulation 

 

modifies the duty-ratio,the relationships between the port voltages and the 

terminal currents are both affected. The effect of storage-time modulation on the 

port voltages is determined by substituting Eq. (8.193) in (8.191): 

vˆ 

Dvˆ V d î (r r ) (8.195) 

in which: 

r 

V 

I 

Storage-time modulation resistance (8.196) 

The effect of storage-time modulation on the average terminal currents is determined 

by substituting Eq. (8.193) in (8.113a): 

î 

D I 

I 

iˆ d I 

(8.197)


Typically D I 

/I 

,so that Eq. (8.197) reduces back to its original form: 

î Dî d I (8.198) 

 

Equations (8.197) and (8.198) correspond to the small-signal model shown in Fig. 

8.74 in which r is an ac resistance which,unlike r ,vanishes under dc conditions. 

 

Figure 8.74 

Storage-time modulation can have a pronounced effect on the high-frequency 

response of certain converters (see Problem 8.17). 

(d) Simple and general saturation models for the switches When a BJT and a 

diode are used for the active and passive switches,respectively,their simple 

saturation models can be easily included in the model of the PWM switch. If we 

assume that a transistor or a diode in its on-state sustains a fixed voltage across its 

terminals,then we can write the relationship between v and v : 

v 

d(v 

V 

 

) dV 

(8.199) 

in which V 

 

is the saturation voltage of the transistor and V 

is the diode 

voltage. The relationship between the average terminal currents remains unaffected 

and is still given by i 

di 

. Equation (8.199) can be rewritten as: 

v 

dv 

(dV 

 

dV 

) (8.200) 

which,along with i 

di 

,can be incorporated in the large-signal average model of 

the PWM switch,as shown in Fig. 8.75a. It can easily be shown that the smallsignal 

model is still given by Fig. 8.72,in which V 

is given by: 

V 

V 

V 

 

V 

V 

(8.201) 

Figure 8.75


Instead of assuming a fixed on-voltage or an on-resistance when a switch is 

closed,we can assume a general relationship V 

(i 

,. . .) so that: 

v 

d[v 

i 

r 

V 

(i 

,. . .)] dV 

(i 

,...) 

i 

di 

d d(v 

, i 

,...) 

⎫ 

⎬ 

⎭ 

(8.202a—c) 

In these equations, V 

(i 

,. . .) and V 

(i 

,. . .) are the on-voltages of the active and 

passive switches,respectively,which depend on the current i 

and possibly upon 

other parameters which depend on drive mechanisms. The duty ratio is shown to 

be a function of the control voltage, v 

,and possibly the current i 

and other 

parameters which also depend on drive mechanisms. An equivalent circuit model 

corresponding to Eqs. (8.202a—c) is shown in Fig. 8.75b. 


8.11 Feedback control of dc-to-dc converters 

The output voltage or current of a dc-to-dc converter can be regulated using one of 

the feedback schemes shown earlier in Fig. 8.2. With output voltage feedback,an 

optional current feedback loop can also be added to form a two-loop,or two-state, 

feedback system. There are several ways of implementing the current feedback 

loop,all of which require special modeling techniques. We shall discuss only one 

popular method of current feedback,known as peak current-mode control,and 

show two different ways of modeling it. We shall use a buck converter to illustrate 

the use of single-loop and two-loop feedback control circuits. 

Regardless of the type of feedback used,the most common way of converting the 

control signal to a PWM waveform is to compare it to a sawtooth waveform. This 

is shown in Fig. 8.76,in which a pulse with a fixed repetition rate,T 

,is initiated at 

the beginning of the ramp and is terminated when the ramp voltage exceeds the

433 8.11 Feedback control of dc-to-dc converters 

control signal. In this figure we have ignored the small ripple component in control 

voltage. By similar triangles we have,from Fig. 8.76: 

v V t d (8.203) 

V T 

It follows that: 

d vˆ 

V 

K 

vˆ 

 

(8.204) 

in which: 

K 

1 V 

modulator gain (8.205) 

Typical values of V 

range from 1 to 2 V. 

Figure 8.76 

8.11.1 Single-loop voltage feedback control 

The buck converter in Fig. 8.77 operates from a fixed bus voltage of 5 V and 

delivers 0—10 A at 2.5 V. The converter is designed to operate at 100 kHz and uses 

power MOSFET switches. The feedback compensation is designed to yield a 

stable loop which has a very large gain (10) at dc and a crossover frequency of 

17 kHz. The large loop gain at dc ensures excellent regulation against quasi-static 

load and line variations (even though the line in this application is fixed at 5 V). 

The crossover frequency at 17 kHz ensures the smallest deviation in the output 

voltage when the load current changes abruptly from 0 to 10 A,or vice versa. An 

approximate expression of the overshoot (or undershoot) in the output voltage is 

given by: 

῀V 

῀I 

2πf 

C ; r 1 

2πf 

C 

(8.206)


in which f 

is the crossover frequency, ῀I 

is the step load current and C is the 

output capacitor. This expression is valid when the change in the load current 

takes place over one or more switching cycles. For faster changes in the load 

current,other factors need to be considered which will not be discussed here. 

Another restriction on the validity of Eq. (8.206) is that the value of the ESR has to 

be less than the reactance of the output filter capacitor at the crossover frequency. 

Figure 8.77 

The purpose of the relatively large value of the output capacitor is to ensure that 

the output voltage ripple stays within 0.3% of the output voltage (7.5 mV) under 

worst case conditions. Such a large capacitance is typically obtained by paralleling 

several capacitors made of solid tantalum which have significant equivalent series 

resistance (ESR). The capacitor in this converter has an ESR of 2 mΩ and is 

obtained by paralleling twenty 250-μF solid tantalum capacitors each with an 

ESR of 40 mΩ. When the capacitive reactance at the switching frequency is much 

smaller than the ESR,the output ripple voltage,instead of being piecewise 

parabolic as discussed earlier,is triangular and is given by the product of the ripple 

current in the inductor and the value of the ESR. In this converter,the reactance of 

C at 100 kHz is 3.2 10 Ω,which is much less than 2 10 Ω. 

The control-to-output transfer function is determined from the equivalent 

circuit diagram shown in Fig. 8.78,where: 

r Dr Dr r ⎫ 

⎬⎭ 

(8.207a, b) 

V V 

In Eq. (8.207b), r is the on-resistance of the MOSFETs and has a typical value


of 28 mΩ at a gate-drive voltage of 10 V. The transfer function relating the output 

voltage to the control voltage is given by: 

G (s) vˆ (s) d vˆ 

K G (s) (8.208) 

vˆ (s) vˆ d 

 

in which G (s) is given by: 

 

1 s/ω 

G (s) V 

1 s/(ω Q) (s/ω ) 

 

(8.209) 

Figure 8.78 

Using the numerical values shown,we compute the following values for the 

zero,the resonant frequency and the characteristic impedance: 

ω 1 (2π)15.9 10 rad/s 

r C 

ω 1 (2π)1.24 10 rad/s 

LC (8.210a—c) 

⎬⎭ 

⎫ 

Z L 25.7 mΩ 

C 

The Q-factor is computed for the cases of resistive and current loading: 

1 

Q 

Z 

r r R r (r r ) R 

Z 

⎫ 

⎬ 

⎭ 

0.83; R 

0.85; R 250 mΩ 

(8.211) 

The compensation network has a transfer function H(s) of the form: 

H(s) K ω 

s 

(1 s/ω 

) 

[1 s/(ω 

/2)] 

(8.212) 

An asymptotic construction of H(s) is shown in Fig. 8.79. The pole at the origin


provides infinite gain at dc for excellent dc regulation. The double zero at ω 

is 

placed on top of ω 

of the power stage in Eqs. (8.209) and (8.210) to compensate for 

the 180° phase shift due to ω 

. The double pole at ω 

/2 provides 20 dB/dec 

attenuation for the switching ripple. In terms of the circuit elements in Fig. 8.77, 

H(s) is given by: 

1 

H(s) 

sR (C C ) 

 

(1 sC 

R 

)[1 sC 

(R 

R 

)] 

(1 sC 

C 

R 

)(1 sC 

R 

) 

(8.213) 

Since ω 

ω 

/2,we can deduce from the expressions of ω 

and ω 

/2 that C 

C 

and R 

R 

,so that Eq. (8.213) can be simplified to: 

H(s) 1 

sR 

C 

(1 sC 

R 

)(1 sC 

R 

) 

(1 sC 

R 

)(1 sC 

R 

) 

(8.214) 

Figure 8.79 

The loop gain is given by: 

T (s) G 

(s)H(s) (8.8.215) 

An asymptotic construction of the magnitude of the loop gain,with ω 

placed 

on top of ω 

,is shown in Fig. 8.80. The closed-loop model can be simulated using 

Figure 8.80


OrCAD/Pspice in which the large-signal average model of the PWM switch in 

continuous conduction mode is available as a subcircuit called VMLSCCM 

(voltage-mode large-signal continuous conduction mode). The simulation circuit 

is shown in Fig. 8.81a,and a magnitude and phase plot of T ( jω) is shown in Fig. 

8.81b. The phase margin and the crossover frequency are seen to be 96° and 

17.6 kHz,respectively. Note that the simulation program uses the large-signal 

average model of the PWM switch to determine the dc operating point automatically. 

Subsequently,the simulation program expands the large-signal model numerically 

at the dc operating point to determine the small-signal response. 

U1 

rL1 

29m 

L1 

3.3uH 

VMLSCCM 

3 

Vg 

5Vdc 

1 

A 

C 

4 

VC 

P 

2 

rC1 

2m 

C1 

5000uF 

I1 

10Adc 

0 

0 

0 

0 

Vinj 

1mV 

C1c 

31pf 

C2c 

2.58nF 

R2c 

1.23k 

R3c 

105k 

C3c 

1.24nF 

R1c 

50k 

0 

- 

+ 

+ 

- 

E_amp 

0 

Vref 

2.5Vdc 

Figure 8.81 

To complete the design,a properly damped input filter is added to reduce the 

input ripple current to about 170 mA,as shown in Fig. 8.82. The effect of the input 

filter on loop gain is shown in Fig. 8.83,in which the crossover frequency is seen to 

remain the same as before. 

The time-domain response of the converter in Fig. 8.82,to a 0—10-A step change 

in the load current,is shown in Fig. 8.84. In this figure,the predicted response of 

the output voltage obtained by the large-signal average model of the PWM switch



Figure 8.82 

and the actual response obtained by cycle-by-cycle simulation of the actual circuit 

are compared. The agreement between the average and the actual response is quite 

satisfactory considering the fact that the simulation run time of the average model 

is much shorter than that of the cycle-by-cycle simulation. If we substitute the


Figure 8.83 

value of the crossover frequency from Fig. 8.83 in Eq. (8.206),we obtain the 

estimated undershoot in the output voltage: 

῀V ῀I 2πf C 

10A 

19 mV (8.216) 

2π(16.6 10)(5000 10) 

which is about 4 mV away from the average value of 23 mV observed in Fig. 8.84. 

The reason for this discrepancy is that Eq. (8.206) is at the limit of its validity 

because the reactance of the output capacitor at the crossover frequency is 

1.92 mΩ,which is larger than the value of its ESR. 

Figure 8.84


8.11.2 Current feedback control 

A very popular type of current feedback control,known as peak current-mode 

control, is shown in Fig. 8.85. In this type of control,the positive ramp of the 

active switch current during the on-time serves as the sawtooth waveform in the 

pulse-width-modulating circuit. When the peak current reaches a specified threshold, 

V 

,the comparator resets a flip—flop terminating the on-time. A clock with a 

fixed period, T 

,always sets the flip—flop to initiate the on-time. It is not hard to see 

that it is the common terminal current that is effectively being fedback,since the 

active and common terminal currents of the PWM switch are coincident during 

the on-time. Therefore,it should be possible to derive an invariant model for peak 

current mode control similar to that of the PWM switch. This is shown in Fig. 8.86 

in which the PWM switch and the current feedback loop are combined in a new 

invariant structure called the current-controlled PWM switch (CC-PWM 

switch). The sawtooth waveform which is added to the current waveform is called 

the external ramp and its purpose is to provide stability,as we shall see presently. 

The steady-state current waveform for D 0.5 is shown in Fig. 8.87a. It is fairly 

easy to see by a simple geometric construction that a steady-state duty cycle 

greater than 0.5 cannot be sustained as shown in Fig. 8.87b. Here we see that peak 

Figure 8.85 

current control becomes unstable for D 0.5 where it breaks into subharmonic 

instability,i.e. the duty cycle increases with a subharmonic periodicity resulting in 

a periodic waveform at half the switching frequency. In Fig. 8.87a we see how an 

initial disturbance in the current waveform settles down for D 0.5. The addition 

of an external sawtooth waveform,or ramp,as shown in Fig. 8.88 extends the 

stable operation of peak current control to D 0.5. It can be seen from these 

figures that the dynamics of peak current mode control is independent of any 

particular converter so that it should be possible to derive an invariant model of 

the CC-PWM switch. Such a model should contribute to the characteristic equation 

of a converter,a quadratic factor whose frequency is at half the switching


Figure 8.86 

frequency and whose damping becomes negative for D 0.5 in the absence of an 

external ramp. 

In order to describe the action of peak current control in invariant terms,all we 

need to do is describe the slopes of the common terminal current in terms of the 

terminal quantities of the PWM switch. It is not hard to verify that the slopes of 

the current signal during the on-time and off-time for any converter are given by: 

Figure 8.87


Figure 8.88 

S V L R V D 

L 

R 

S 

V 

L R 

⎫ 

⎬ 

⎭ 

(8.217a, b) 

in which R 

is a scaling constant which transforms the current signal into a voltage 

signal and L is the effective inductance which dictates the slope of the current. In a 

single inductor converter, L is the same as the switched inductor in that converter. 

For example,in the buck converter with an input filter,shown earlier in Fig. 8.69a, 

L L; whereas in the Cuk converter, L L 

L 

. According to Fig. 8.88,the 

following dc equation holds at the switching instants: 

I R S DT S DT V (8.218) 

2 

When time variations in the duty cycle are considered,all quantities in Eq. (8.218) 

must be replaced with their instantaneous values resulting in a sampled-data 

equation. If,for the moment,we ignore the effects of sampling,then we can replace 

all the quantities in Eq. (8.218) with their average values to determine the effect of 

the control law on these quantities. Hence,Eq. (8.218) together with the invariant 

equation of the PWM switch yield: 

i 

v 

R 

S 

dT 

R 

s (1 d)T 

2R 

i 

di 

v 

dv 

⎫ 

⎬ 

⎭ 

(8.219a—c) 

If we substitute d v 

/v 

and s 

v 

R 

/L in Eqs. (8.219a, b),we obtain:


i 

v 

R 

v 

v 

T 

S 

R 

v 1 v 

v 

T 

2L 

⎫ 

⎬⎭ 

(8.220a, b) 

i 

i 

v 

v 

These two equations correspond to the large-signal average model of the CC- 

PWM switch shown in Fig. 8.89. The capacitance C 

in this figure does not follow 

from Eqs. (8.220a, b) and has been added to predict the subharmonic instability of 

the current loop,as will be discussed shortly. Equations (8.220a, b) were written 

assuming positive i 

flowing out of the common terminal. If positive i 

flows into 

the common terminal,then the direction of the control and external ramp sources 

should be reversed. Although we can always identify the PWM switch with 

positive i 

flowing out of the common terminal,we can allow,in general,for i 

to 

flow in either direction and automatically reverse the control and ramp control 

sources by multiplying these sources by i 

/ i 

(with positive i 

defined flowing out 

of the common terminal). This is particularly useful in creating a user-defined 

subcircuit for simulation purposes. The dc model of the CC-PWM switch is 

essentially the same as the large-signal average model without C 

. Generally,it is 

not possible to solve for the dc operating point in terms of V 

in closed form 

because the solution is generally given by the roots of a cubic equation,as we shall 

see in Example 8.13. 

Figure 8.89 

The equivalent small-signal circuit model of the CC-PWM switch is obtained by 

perturbing the large-signal average equations in Eqs. (8.220): 

î 

vˆ 

k vˆ g g vˆ 

î 

Dî 

g 

vˆ 

g vˆ 

⎫ 

⎬ 

⎭ 

(8.221a, b) 

in which the reader can verify:


k 1 I R I 

g T L D S 1 S 2 D 

 

g 

Dg 

DDT 

2L 

g 

I 

V 

⎫ 

⎬ 

⎭ 

(8.222a—e) 

g 

I 

V 

These equations correspond to the circuit model shown in Fig. 8.90. Clearly,there 

are many different ways of expressing the small-signal parameters in Eqs. (8.222). 

For example,we have expressed g 

explicitly in terms of S 

/S 

because it is typical 

to specify the amount of the external ramp by its ratio to the natural current ramp 

during the on-time. 

The capacitance C 

in the model of the CC-PWM switch is determined quite 

easily by examining the dynamics of peak current control in the vicinity of half the 

switching frequency,as shown in fig. 8.87b. As mentioned earlier,the dynamics 

Figure 8.90 

shown in Fig. 8.87b is independent of the type of converter and is characteristic of 

peak current control only. This observation is verified by examining the equivalent 

circuit of any converter with peak current control using the model of CC-PWM 

switch in Fig. 8.90. Hence,with the control voltage and input held constant and the 

output voltage essentially at signal ground in the vicinity of half the switching 

frequency,the equivalent circuit model of any converter in peak current control 

reduces to the parallel resonant circuit shown in Fig. 8.91b. To see this,we use the 

buck-boost converter in Fig. 8.91a as an example and write: 

V 

constant vˆ 

0 (8.223) 

V 

, V 

constant V 

constant vˆ 

0 

We could have started with any other converter and arrived at the same circuit in


Fig. 8.91b using the conditions in Eq. (8.223). This is the circuit which contributes 

to the characteristic equation a quadratic factor at half the switching frequency 

which becomes unstable for D 0.5 when S 

0. In fact,the characteristic 

equation for this parallel resonant circuit is: 

῀(s) 1 sLg 

s 

LC 

(8.224) 

If this circuit were to resonate at half the switching frequency,the value of C 

would have to be such that: 

ω 

2 1 

LC 

C 

4 

Lω 

(8.225) 

According to Eq. (8.222b),the value of g 

in the absence of an external ramp is 

given by: 

g T L 1 2 D (8.226) 

 

which for D 0.5 becomes negative and the parallel resonant circuit oscillates at 

half the switching frequency. The addition of an external ramp allows g 

to remain 

Figure 8.91 

positive for D 0.5,as can be seen from Eq. (8.222),thereby stabilizing the current 

loop. Hence,the predictions of the model of the CC-PWM switch in Fig. 8.90 and 

the behavior of peak current control are consistent. In the following example we


shall determine the dynamics of a boost converter with peak current control. 

The quadratic factor in Eq. (8.224) is common to the denominator of the 

small-signal dynamics of PWM converters operating in CCM with peak current 

control. Performing the necessary substitutions,Eq. (8.224) can be written as: 

῀(s) 1 

s s 

(8.227) 

ω Q ω 

in which 

ω 

ω 

2 

1 

Q 

π S D 1 S 2 D 

 

1 

 

π D S 

S 

1 1 2 

⎫ 

⎬ 

⎭ 

(8.228a, b) 

Example 8.13 A boost converter with peak current control is shown in Figs. 

8.92a and b. In Fig. 8.92a the CC-PWM switch is identified with positive i flowing 

into the common terminal and in Fig. 8.92b it is identified with positive i flowing 

out of the common terminal. Using the circuit in Fig. 9.92a,we replace the 

CC-PWM switch with its dc model as shown in Fig. 8.93,in which the arrows of 

the ramp and control source have been reversed. According to Fig. 8.93,we have: 

Figure 8.92


I 

V 

R 

V 

V 

T 

S 

R 

V 1 V 

V 

T 

2L 

V 

I I 

V 

V 

 

V 

V 

V 

V 

V 

⎫ 

⎬ 

⎭ 

(8.229a—d) 

Solving these simultaneously,we obtain the following cubic equation in V 

: 

V 

V 

V T S R 

R 

RT V 

2L 

R V 

R 

T RS V RT V 

R 2L 0 (8.230) 

 

Clearly it is not possible to obtain an analytical answer for V 

for a given control 

voltage V 

. Unfortunately,this is the case with peak current control regardless of 

the type of converter. The best that we can do is get an approximate idea by letting 

L be very large and ignore S 

. This yields: 

R 

V V V V 0 V R V V R 

(8.231) 

R 

The control-to-output transfer function is determined by replacing the CC- 

PWM switch with its small-signal model as shown in Fig. 8.94 and has the form: 

vˆ N (s) 

A 

vˆ D(s) 

 

(8.232) 

Figure 8.93


Figure 8.94 

At dc,the circuit in Fig. 8.94 reduces to the one in Fig. 8.95,whence the lowfrequency 

asymptote can be obtained: 

k D 

A 

g g G D(g g ) 

 

R 1 

R 2M RT 

LM 1 2 S 

S 

 

(8.233a, b) 

in which G 1/R. The same result can be obtained by an implicit differentiation of 

Eq. (8.230) with respect to V 

. 

Figure 8.95 

The demoninator is obtained by setting the control source vˆ in Fig. 8.94 to zero. 

 

We already know that at high frequencies this circuit reduces to the parallel 

resonant circuit in Fig. 8.91b,which contributes the quadratic term at half the 

switching frequency in Eq. (8.224) as discussed earlier. Hence we have: 

D(s) (1 s/ω 

)[1 s/(ω 

Q 

) s/ω 

] (8.234)


in which: 

ω 

ω 

2 

Q 

1 

ω 

Lg 

 

1 

π D S 

S 

1 2 D 

⎫ 

⎬ 

⎭ 

(8.235a, b) 

The dominant pole ω 

is determined by examining the circuit in Fig. 8.94 at low 

frequencies in which the output filter capacitor is seen to dominate the dynamics. 

The conductance looking into the capacitive port is determined from Fig. 8.95, 

which the reader can verify to be: 

1 

R g g G D(g g ) ⎫ 

(8.236) 

⎬ 

2G T 

LM 1 2 S 

S 

⎭ 

Hence,the dominant pole in Eq. (8.234) is given by: 

ω 1 2G T 

 

LM 1 

RC 2 S 

S 

 

C 

(8.237) 

The numerator, N (s),in Eq. (8.232) is determined by examining the null response 

of the circuit as shown in Fig. 8.96. A null in the output voltage implies 

 

vˆ 0,which in turn implies that: 

 

vˆ 

iˆ 

sL (8.238a, b) 

î 

Dî 

g 

vˆ 

 

⎫ 

⎬ 

⎭ 

The simultaneous solution of these equations yields: 

D g 

sL 0 (8.239) 

Substituting g 

1/DR we obtain the numerator: 

L 

N (s) 1 s RD 

(8.240)


Figure 8.96 

This is the same RHP zero in the duty-ratio-to-output transfer function in continuous 

conduction mode as explained earlier in Fig. 8.50 and in Eqs. (8.141— 

8.143). This is expected since a step change in the control voltage v in peak current 

 

control results in a simultaneous step change in the duty cycle. 

 

Another model for peak current control,which actually preceded the model of 

the CC-PWM switch,was developed by R. Ridley and is shown in Fig. 8.97. In 

this figure,the power stage is modeled using the PWM switch with duty ratio 

control,while the current loop is modeled using the blocks k 

, k 

, F 

and H 

(s). The 

blocks k 

and k 

model the effect of the input and output voltages and their 

expressions for certain converters are: 

k 

 

⎫ 

⎬ 

⎭ 

DT R 

L 

T R 

2L 

1 D 2 buck,buck-boost 

boost 

(8.241) 

k 

 

⎫ 

⎬ 

⎭ 

T R 

L 

DT R 

2L 

buck 

boost,buck-boost 

(8.242) 

The modulator gain is modeled by F 

,while the effect of sampling is modeled by 

H 

(s). These are given by: 

1 

F (S S )T 

(8.243a, b) 

H (s) 

sT e 1 1 s π 

ω 2 s ; ω ω 

ω 2 

 

The approximation of H 

(s) by a quadratic is valid up to the neighborhood of half 

the switching frequency. 

⎫ 

⎬ 

⎭


Figure 8.97 

Both modeling techniques yield the same results for the control-to-output 

transfer functions,as shown in the next example. 

Example 8.14 The complete small-signal equivalent circuit of the boost converter 

in peak current control using the model in Fig. 8.97 is shown in Fig. 8.98. The 

denominator D(s) in Eq. (8.232) is determined by setting all the excitations to zero 

in Fig. 8.98 and examining the resulting circuit at low and high frequencies shown 

in Figs. 8.99a, b,respectively. The dominant pole is obtained from Fig. 8.99a and 

can be shown to be given by Eq. (8.237). The roots of the high-frequency factor are 

obtained from Fig. 8.99b: 

[d ] V 

D D [î R H (s)F ] V 

D D sLî 

(8.244) 

Figure 8.98


The quadratic factor follows by canceling î 

in the last two equalities: 

H (s) 

sL 0 (8.245) 

F R V 

Substituting S 

from Eq. (8.217a) in the expression for F 

,we obtain: 

F 

R 

V 

1 

T 

S 

R V L 

1 S /S T D 

1 

1 S 

/S 

(8.246) 

Substituting Eqs. (8.245) and (8.243) in (8.246),we obtain the same quadratic factor 

as in Eq. (8.234). 

The numerator of the control-to-output transfer function is determined by 

examining the null response of the circuit as shown in Fig. 8.101,whence we have: 

Figure 8.99


Figure 8.100 

d V 

D D î sL ⎫ 

(8.247a, b) 

⎬ 

⎭ 

î I d Dî 

The simultaneous solution of these equations yields: 

1 sL I 

V 

D 0 (8.248) 

When the dc operating point, I I /D andV V ,is substituted in the 

 

above,the same RHP zero as in Eq. (8.240) is obtained. 

 

8.11.3 Voltage feedback control with peak current control 

In this section we shall demonstrate one of the advantages of adding a peak 

current feedback loop to a voltage feedback loop. In Eq. (8.215),we saw that the 

loop gain of the regulated buck converter was directly proportional to the input 

voltage because of the dc gain G of G (s) given by Eq. (8.209). Hence,if the input 

 

voltage was to vary significantly,the crossover frequency would vary proportionally,which 

in certain applications could be undesirable. To show how peakcurrent 

control renders the crossover frequency of the loop gain insensitive to the 

input voltage,consider the small-signal equivalent circuit of a simple buck converter 

without an input filter in peak-current mode control,as shown in Fig. 8.101. 

The control-to-output transfer function is obtained after setting vˆ 0 and is given 

 

by: 

vˆ 1 s/ω 1 

G 

vˆ 1 s/ω 1 s/(ω Q ) (s/ω ) 

 

 

(8.249)


in which the quadratic factor is the same as the one discussed earlier in Eqs. (8.234) 

and (8.235a, b). The zero at ω 

is the usual zero due to r 

of the output filter 

capacitor and is given by: 

ω 

1 

r 

C 

(8.250) 

If we let s 0,then the circuit in Fig. 8.101 reduces to the current source k 

vˆ 

 

feeding the parallel combination of the load resistance and g 

. It follows that G 

in 

Eq. (8.249) is given by: 

G 

k 

(8.251) 

g G 

Figure 8.101 

in which g and k are given by Eqs. (8.222a, b). 

 

The low-frequency pole at ω is obtained by examining the circuit in Fig. 8.101 

 

at low frequencies with vˆ 

vˆ 0. At low frequencies, L is ineffective and the 

 

dominant time constant is formed by C C parallel with g and the load 

 

resistance. Hence,the dominant pole is given by: 

ω 

g G 

C 

C 

g G 

C 

(8.252) 

The crossover frequency is normally well above ω 

and well below ω 

ω 

/2. 

Hence,in the vicinity of the crossover,G 

and ω 

combine together in the 

approximate behavior of the control-to-output transfer function: 

1 s/ω 

G (s) G k (1 s/ω ) (8.253) 

s/ω sC 

in which we have made use of Eqs. (8.251) and (8.252). Since k is independent of 

 

the input voltage,it follows that the control-to-output transfer function and, 

hence,the loop gain are both independent of the input voltage near the crossover 

frequency. It follows that the crossover frequency itself is practically independent 

of the input voltage. An asymptotic sketch of G(s) is shown in Fig. 8.102.


Figure 8.102 

The voltage feedback compensation of a dc-to-dc converter with peak-current 

control is somewhat simpler than that of a converter without peak-current control. 

The reason of course is that the power stage in current mode has a dominant 

single pole whereas a power stage without peak-current control and operating in 

CCM has a dominant complex pole-pair. A typical compensation scheme for 

converters in peak-current control is shown in Fig. 8.103. The transfer function 

relating the control voltage to the converter output voltage of the amplifier in Fig. 

8.103 is given by: 

H(s) vˆ (s) 

vˆ 

in which: 

(s) H 

1 ω 

s 

1 s 

ω 

(8.254) 

H R R 

ω 1 

R C 

1 

ω 

1 

R C C 

R 

C 

⎫ 

⎬⎭ 

(8.255a—c) 

The pole at ω 

is optional and is placed at or above half the switching frequency 

mainly to attenuate high-frequency switching noise. The zero at ω 

is placed 

between the dominant pole of the power stage and the desired crossover frequency. 

It should be placed low enough to provide adequate phase margin but not so low 

as to cause a sluggish response. A numerical illustration of a practical voltage 

feedback loop around a power stage with peak-current control is given in the 

following example.


Figure 8.103 

Example 8.15 An OrCAD/Pspice simulation of the equivalent circuit of a buck 

converter with peak-current control and output voltage feedback control is shown 

in Fig. 8.104. The subcircuit CMLSCCM (current-mode large-signal continuous 

conduction mode) is a large-signal model of the current-controlled PWM switch in 

continuous conduction mode. The converter operates at 100 kHz from an input 

voltage range of 13 to 26 V and has an output voltage of 5 V at 0—10 A. The load is 

assumed to behave as a current source so that its incremental resistance is infinite, 

i.e. G 0. 

The reader can verify that the output ripple voltage is dictated by r of the 

output filter capacitor C instead of C and that it has a maximum value of 25 mV, 

 

which occurs when the input voltage is 26 V. 

rL1 

50m 

L1 

16uH 

1 

Vg 

13Vdc 

4 

A 

VC C 

2 

P 

3 

U1 

CMLSCCM 

rC1 

10m 

C1 

1000uF 

0 

I_Load 

10Adc 

0 

V_inj 

10mV 

0 

C2c 

500pF 

C1c 

20pF 

R2c 

160K 

R1c 

10K 

0 

- 

+ 

+ 

- 

E_amp 

V_ref 

5Vdc 

0 

0 

Figure 8.104


The two parameters of peak-current control that must be determined are the 

amount of the external stabilizing ramp, S ,and the current-to-voltage conversion 

 

resistance R ,both of which are shown in the model of the CC-PWM switch in Fig. 

 

8.86. The value of R is dictated by the maximum value of the current-sense voltage 

 

signal which,for most commercially available PWM control chips,is in the range 

of a few volts. In this design,we shall assume the maximum value of the currentsense 

signal to be 2.5 V and that the maximum current to be sensed is about 12 A. 

Hence: 

R 2.5 V 0.2 Ω (8.256) 

12 A 

Also,in this design,the amount of external ramp is chosen to yield Q 

0.5 in the 

subharmonic quadratic factor in Eq. (8.228). Hence,according to Eq. (8.228): 

Q 

 

1 

π D S 

S 

1 1 2 

0.5 (8.257) 

The minimum duty cycle,assuming an efficiency of η 85%,is computed to be: 

D 

V 

5V 0.225 (8.258) 

ηV (0.85)26 V 

 

The slope of the inductor current during the off-time can now be computed: 

S 

V R 

L 

5 V(0.2 Ω) 

6.25 V/μs (8.259) 

16 μH 

Substituting Eqs. (8.258) and (8.259) in Eq. (8.257) yields the amount of external 

ramp: 

S 

10 V/μs (8.260) 

The values of R 

, S 

, L and the switching frequency are the arguments which are 

supplied to the subcircuit CMLSCCM,which in turn computes the value of C 

according to Eq. (8.225). 

The loop gain is given by the product of H(s) and G 

(s): 

1 s 1 ω 

ω s 1 

T (s) T 

1 s 1 s 1 s s 

(8.261) 

ω ω ω Q ω 

in which T 

is given by: 

T 

k 

g 

R 

R 

(8.262)


The numerical values of k 

and g 

are given by: 

k 

1 R 

5 Ω (8.263) 

g 

T 

L 

D S 

S 

1 2 D 

⎫ 

⎬ 

⎭ 

0.416 Ω; V 

13 V 

0.364 Ω; V 

26 V 

(8.264) 

The following values are computed for the numerical determination of the loop 

gain: 

T k R 192; V 13 V 

 

g R 219; V 26 V 

⎫ 

ω 1 

1 

 

(2π)15.9 krad/s 

r C (10 mΩ)(1000 μF) 

ω 1 

1 

 

(2π)1989 rad/s 

R C (160 kΩ)(500 pF) 

ω 1 

1 

 

(2π)50 krad/s (8.265a—g) 

R C (160 kΩ)(20 pF) 

⎬ 

ω ω (2π)50 krad/s 

2 

⎫ 

⎬ 

⎭ 

Q 

 

1 

π D S 

S 

1 1 2 

ω 

g 

C 

 

⎫ 

⎬ 

⎭ 

(2π)66 rad/s; V 

13 V 

(2π)58 rad/s; V 

26 V 

⎫ 

⎬ 

⎭ 

0.5; V 

26 V 

0.4; V 

13 V 

⎭ 

Note that the shape of the loop gain past the dominant pole, ω 

,is practically 

independent of the input voltage for the same reason given earlier in Eq. (8.253). 

In Fig. 8.105,a magnitude and phase plot of the loop gain is obtained using an 

injection signal,as shown in the simulation program in Fig. 8.104. As expected the 

shape of the loop gain and the crossover frequency are independent of the input 

voltage.


Figure 8.105 

Figure 8.106 

The dynamic response of the output voltage to a 0—10 A step change in the 

output load current is shown in Fig. 8.106. The continuous trace shows the 

response obtained using the large-signal average model of the CC-PWM switch 

(CMLSCCM) in Fig. 8.105. Also shown in Fig. 8.106 is the actual response of the 

converter obtained by cycle-by-cycle simulation. The agreement between the 

predictions of the cycle-by-cycle simulation and the large-signal average model 

simulation is generally good.


8.12 Review 

An ideal dc-to-dc converter transforms the dc level of a voltage or a current source 

in a controllable and nondissipative manner using switches,inductors and capacitors. 

The inductors and capacitors form effective low-pass filters which extract the 

dc component of the switching waveforms and provide smooth dc voltages and 

currents at the input and output ports of the converter. A practical converter 

dissipates a relatively small amount of power in comparison with its output power 

because of nonideal components. The ratio of the output voltage to the input 

voltage is defined as the conversion ratio and is controlled by the duty cycle of the 

switches. Although,in principle,a myriad number of switches,driven in myriad 

ways,can be used to generate nonisolated converters ad nauseam,a pair of 

switches,driven in a complementary fashion,is sufficient to generate basic converters 

which accomplish all the necessary functions of dc-to-dc power conversion. 

The buck,the boost,the buck-boost,the Cuk,the Watkins—Johnson and its 

bilateral inverse are among the basic converters discussed in this chapter. The 

buck converter steps down the input voltage and the boost converter steps up the 

input voltage. The sign of the output voltage in both of these converters follows the 

sign of the input voltage. The Cuk and the buck-boost converters can either step 

up or step down the input voltage and the sign of their output voltage is always 

opposite that of the input voltage. The Watkins—Johnson and its bilateral inverse 

can either step up or step down the input voltage while the sign of their output 

voltage can either be the same or opposite that of the input voltage. Other 

converters,some of which use four switches,are also discussed. 

Like amplifiers,dc-to-dc converters are nonlinear circuits whose exact solutions 

can only be determined numerically using circuit simulation programs. Nevertheless,the 

vast amount of design-oriented analytical techniques available for amplifier 

circuits are also desirable for dc-to-dc converter circuits. In an amplifier circuit, 

these techniques are applied once an equivalent circuit model of the amplifier is 

obtained by replacing the transistor,or the vacuum tube,with its equivalent circuit 

model. In order to apply these techniques to a PWM converter circuit,we have 

introduced the concept of the PWM switch and derived an equivalent circuit 

model for it. The PWM switch,just like the transistor,is a three-terminal nonlinear 

device which can be replaced with its equivalent circuit model to yield an 

equivalent circuit model of a PWM converter circuit. The model of the PWM 

switch does not depend on any particular converter topology,just like the model 

of a transistor does not depend on any particular amplifier topology. Hence,the 

analyses of the dynamics of amplifiers and PWM converters are identical. For

461 Problems 

example,to determine the small-signal characteristics of a PWM converter,first a 

dc analysis is performed and the dc operating point of the PWM switch is 

determined. Second,the small-signal parameters in the model of the PWM switch 

are evaluated at the dc operating point and a small-signal equivalent circuit of the 

converter is obtained from which the input and output impedance,the line-tooutput 

and the control-to-output transfer functions are determined. 

Various feedback control techniques can be used to regulate the output voltage 

of a converter against variations in the input voltage and the load current. In a 

single-loop feedback system,only the output voltage is fed back into the PWM 

control circuit where it is compared with a reference voltage. In a two-loop 

feedback system,in addition to the output voltage,the current in the active switch 

is fed back to improve the loop-gain characteristics of the voltage feedback loop. 

The nature of the sampled data of the active-switch current feedback loop must be 

correctly accounted for whenever a continuous-time model of the converter is 

sought. This can be done either by deriving a model for the current feedback loop 

alone or by deriving a model for the PWM switch and the current feedback loop 

combined together. The combination of the PWM switch and the current feedback 

loop is called the current-controlled PWM switch. 

Problems 

8.1 Linear series voltage regulator. A simplified diagram of a series regulator 

using a bipolar transistor is shown in Fig. 8.107a. An equivalent circuit diagram is 

shown in Fig. 8.107b. 

(a) Show that the line-to-output transfer function and the output impedance are 

given by: 

v (s) 

v (s) 1 

1 

a r 1 sC R R α 

r 

αa 

(8.266a, b) 

Z 

(s) 

R r 

αa 

1 sC R r 

αa 

⎫ 

⎬ 

⎭ 

(b) Ifa 

is an operational amplifier,then its gain can be approximated by 

a(s) ω 

/s. Show that the regulator in this case becomes unstable as R 

. 

One way to prevent this oscillation is to connect a large capacitance from the 

emitter to ground in order to shunt r 

. Determine the transfer functions in part


(a) with C connected from emitter to ground and discuss how the circuit 

becomes stable. (When a linear regulator is placed far from the source, r 

accounts for the resistance of the connecting wires. This is why manufacturers 

of linear regulator ICs recommend that a large capacitance (100 μF,solid 

tantalum) be connected immediately to the input terminals of the linear 

regulator whenever it is placed far from V 

.) 

Figure 8.107 

8.2 Linear shunt regulator. Show that for the shunt regulator in Fig. 8.108a we 

have: 

r 

R r 

v (s) 

 

 

 

i (s) Z (s) Z (s) 

1 a 

(8.267) 

r 1 sC R r 

 

1 a 

8.3 Incremental output resistance. 

(a) Show that the incremental output resistance of an ideal unregulated converter 

is given by:

463 Problems 

Figure 8.108 

M /I 

r V 

(8.268) 

1 V M /V 

Hint: Recall that M 

,in general,can be a function of α, V 

and I 

. Also we have: 

r dV d(M V ) dM 

V 

(8.269) 

dI dI dI 

(b) Deduce that when M is only a function of control parameter,then r 0. 

 

(c) Certain converters have certain modes of operation in which they act as 

gyrators,i.e. they transform the input voltage source to a current source which 

is linearly proportional to the input voltage: 

I 

g 

(α)V 

(8.270) 

in which g 

is some transconductance that depends on the control parameter α. 

(An example of such a converter is the series resonant converter operating in an 

even-type discontinuous conduction mode.) It is clear then that the output 

impedance for such a converter is infinite. Show that r 

indeed is infinite in Eq. 

(8.268) for such converters. 

Hint: Show that M 

can be written as:


M 

g 

R 

g 

V 

I 

(8.271) 

8.4 Transfer function of the LC low-pass filter. Use the 2-EET to determine the 

transfer function of the LC low-pass filter shown in Fig. 8.109. 

Figure 8.109 

8.5 Output ripple voltage in the buck converter. 

(a) Derive the expression of the output ripple voltage in the buck converter 

starting with the expressions of the individual components of the ripple voltage 

in Eqs. (8.29a, b). 

(b) Derive the same expression by recognizing that the peak-to-peak ripple voltage 

on the capacitor is equal to the amount of charge delivered to the capacitor 

in the time interval T /2 t (T T )/2 divided by the capacitance. This is 

 

shown in Fig. 8.110 in which I (t) is the ripple component of the inductor 

 

current. 

Figure 8.110 

8.6 Input ripple current of a buck converter with an input filter. Using simple 

geometry,derive the expression of the peak-to-peak ripple current of the input 

filter of the buck converter in Eq. (8.55). 

Hint: Recognize that the double integral in Eq. (8.54) is nothing more than the area under the 

triangle shown in Fig. 8.111,whose height is half the area of the rectangular voltage pulse during 

T 

.

465 Problems 

Figure 8.111 

8.7 Parallel damping of the input filter. An LC filter with parallel damping is 

shown in Fig. 8.112a. Use the 3-EET to show that the characteristic equation is 

given by: 

D(s) 1 s C R R L s LC LC R 

R R 

 

sLCC 

R 

(8.272) 

In order to ensure that R 

C 

damps the LC resonance (and does not create a new 

lower resonance),it should be chosen such that: 

1 

R 

C 

ω 

1 

LC 

(8.273) 

Figure 8.112 

If R 0,as in the case of loading by a regulating switching converter,we should 

further require that: 

R 

R (8.274) 

so that: 

R R 

0 (8.275) 

Hence,provided R is not too small,practical values of R 

can be realized. Show 

that under these considerations D(s) can be factored:


D(s) (1 sC R ) s L 

R R sLC (8.276) 

 

 

in which we see that the Q-factor of the quadratic term is given by Q 

in Eq. (8.59). 

Hint: Use the reference circuit in Fig. 8.112b to derive D(s) in Eq. (8.272). 

8.8 Series damping of the input filter. Following the same procedure as in 

Problem 8.7,derive similar results for the series-damped input filter shown in Fig. 

8.113. 

Figure 8.113 

8.9 Output ripple voltage of the boost converter under conditions of no load. Show 

that under conditions of no load (R 

) the current through S 

(assuming S 

is 

a bi-directional switch) in the boost converter in Fig. 8.19 has the shape shown in 

Fig. 8.114. Determine the ripple voltage across the capacitor and show that its 

peak-to-peak value is given by: 

V 

 

V 

DDT 

8LC 

T M 1 

 

8LC M 

⎫ 

⎬ 

⎭ 

(8.277a,b) 

Figure 8.114 

8.10 Output ripple voltage of the buck-boost converter under conditions of no 

load. Show that the peak-to-peak ripple voltage in the buck-boost converter 

under no-load conditions (assuming bi-directional switches) is given by:

467 Problems 

V 

(DT ) 

⎫ 

V 8LC 

 

8LC 

1 T ⎬⎭ 

 

1 M 

 

(8.278a,b) 

8.11 Isolated Cuk converter. The isolated Cuk converter is shown in Fig. 8.115. 

Show that the conversion ratio is given by: 

M 

n D D 

(8.279) 

Figure 8.115 

The magnetizing inductance of the transformer can have a significant effect on 

the control-to-output transfer function because it can resonate with C 

and C 

, 

both of which must be properly damped. 

8.12 The control-to-output transfer function of the tapped buck converter. 

(a) Determine the transfer function in Eq. (8.147). 

(b) Examine the current waveform i (t) in Figs. 8.51a, b,and explain why the zero 

 

in the control-to-output transfer function is in the right-half plane for n 1 

and in the left-half plane for n 1. 

(c) Derive the analytical expression of this zero using a similar argument given for 

the boost converter in Eqs. (8.138—8.143). 

8.13 Effect of parasitic elements on the voltage conversion ratio of the Watkins– 

Johnson converter. 

(a) Substitute the dc model of the PWM switch in the converter shown in Fig. 8.56 

and include a parasitic resistance, r 

,in series with the active terminal (or at any 

other place that you like). Determine the new conversion ratio using the EET 

with r 

as the designated extra element. 

(b) Show that the conversion in the presence of r 

is zero for D 0.5. 

(c) Sketch the conversion ratio in part (b) and determine its maximum value.


8.14 Inverse of the Watkins–Johnson converter. Identify the PWM switch in the 

converter shown in Fig. 8.58 and determine its voltage conversion ratio. 

8.15 Frequencyresponse of a quadratic converter. An OrCAD/Pspice simulation 

of the quadratic converter in Fig. 8.64 is shown below in which the control-tooutput 

transfer function is determined by expanding the large-signal model of the 

PWM switch (VMLSCCM) at a duty cycle of D 0.35. This is accomplished by 

setting the control voltage at a dc value of 1.35 V with a small-signal ac voltage 

superimposed on it. 

Using the numerical values of the components in Fig. 8.116a,verify the controlto-output 

transfer function derived in Eq. (8.185) against Fig. 8.116b. 

rL2 

0.233 

L2 

1200uH 

3 

Vg 

25V 

F1 

GAIN = 1 

1 

U1 

VMLSCCM 

A 

C 

4 

VC 

P 

2 

C2 

5uF 

0 

R1 

8.05 

0 

0 

rL1 

0.133 

L1 

524uH 

V_control 

ACMAG = 10mV 

DC = 1.35Vdc 

E1 

GAIN = -1 

+ 

+ 

- 

- 

0 

0 

1 

A 

3 

C 

4 

VC 

P 

U2 

VMLSCCM 

2 

0 

C1 

5uF 

0 

0 

Figure 8.116 

Notes: (a) Pspice simply ignores the actual magnitude of the ac voltage,shown here as 10 mV, 

and numerically expands the model of the PWM switch at the dc operating point and determines 

the numerical transfer function of the linearized circuit. (b) In the specification of the 

parameters of VMLSCCM,the height of the ramp is set to 1 V and the valley voltage at 1 V. 

Hence,a dc value of 1.35 V in the control voltage results in a duty cycle of 0.35. 

8.16 The high-frequencyresistance r e 

in the model of the PWM switch. (a) Show 

that r 

r 

 

for the converter in Fig. 8.59. (b) Show that r 

(r 

R)(1 n)/n for 

the Watkins—Johnson converter in Fig. 8.56. (c) Determine r 

for the converter in 

Fig. 8.58. 

8.17 Storage-time modulation in the Cuk converter. The effect of storage-time 

modulation on the line-to-output transfer function of the Cuk converter can be

469 Problems 


easily studied by using the model of the PWM switch in Fig. 8.74 as shown in Fig. 

8.117. In particular,we are interested in determining the numerator of the line-tooutput 

transfer function. Using the technique explained in (Section 2.4),show that: 

v (s) 

s 

 

v (s) 1 ω 

1 s 

ω 

 

D(s) 

 

(8.280) 

where: 

ω 1 

r C ⎫ 

(8.281a, b) 

DD 

ω C (DDr Dr Dr r ) 

 

in which the modulation resistance is given by: 

⎬ 

⎭ 

r 

V 

I 

V 

DI 

(8.282) 

It can be seen that ω 

can be either in the left-half plane or the right-half plane 

depending on the relative magnitudes of the parasitic resistances and the modulation 

resistance which can have either a positive or a negative value depending 

upon the type of base drive used.


Figure 8.117 

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the Isolated Cuk Converter’’, IEEE Transactions on Aerospace and Electronic Systems, 

Vol. 32, No. 3,July 1996,pp. 967—983.

台灣新竹交通大學 808 實驗室 (Power Electronics Systems and Chips Design Lab) 

電力電子系統與晶片、開關電源、綠色能源、數位電源、馬達控制、伺服控制 

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