Algredo-Badillo, I.; Morales-Sandoval, M.; Medina-Santiago, A.; Hernández-Gracidas, C.A.; Lobato-Baez, M.; Morales-Rosales, L.A.
A SHA-256 Hybrid-Redundancy Hardware Architecture for Detecting and Correcting Errors. Sensors 2022, 22, 5028.
https://doi.org/10.3390/s22135028
AMA Style
Algredo-Badillo I, Morales-Sandoval M, Medina-Santiago A, Hernández-Gracidas CA, Lobato-Baez M, Morales-Rosales LA.
A SHA-256 Hybrid-Redundancy Hardware Architecture for Detecting and Correcting Errors. Sensors. 2022; 22(13):5028.
https://doi.org/10.3390/s22135028
Chicago/Turabian Style
Algredo-Badillo, Ignacio, Miguel Morales-Sandoval, Alejandro Medina-Santiago, Carlos Arturo Hernández-Gracidas, Mariana Lobato-Baez, and Luis Alberto Morales-Rosales.
2022. "A SHA-256 Hybrid-Redundancy Hardware Architecture for Detecting and Correcting Errors" Sensors 22, no. 13: 5028.
https://doi.org/10.3390/s22135028
APA Style
Algredo-Badillo, I., Morales-Sandoval, M., Medina-Santiago, A., Hernández-Gracidas, C. A., Lobato-Baez, M., & Morales-Rosales, L. A.
(2022). A SHA-256 Hybrid-Redundancy Hardware Architecture for Detecting and Correcting Errors. Sensors, 22(13), 5028.
https://doi.org/10.3390/s22135028