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A Power-Efficient 16-bit 1-MS/s Successive Approximation Register Analog-to-Digital Converter with Digital Calibration in 0.18 μm Complementary Metal Oxide Semiconductor
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A Survey of Short-Range Wireless Communication for Ultra-Low-Power Embedded Systems
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OptimalNN: A Neural Network Architecture to Monitor Chemical Contamination in Cancer Alley
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Efficient Addition Circuits Using Three-Gate Reconfigurable Field Effect Transistors
Journal Description
Journal of Low Power Electronics and Applications
Journal of Low Power Electronics and Applications
is an international, peer-reviewed, open access journal on low power electronics published quarterly online by MDPI.
- Open Access— free for readers, with article processing charges (APC) paid by authors or their institutions.
- High Visibility: indexed within Scopus, ESCI (Web of Science), Inspec, and other databases.
- Rapid Publication: manuscripts are peer-reviewed and a first decision is provided to authors approximately 23.2 days after submission; acceptance to publication is undertaken in 4.6 days (median values for papers published in this journal in the first half of 2024).
- Journal Rank: CiteScore - Q2 (Electrical and Electronic Engineering)
- Recognition of Reviewers: reviewers who provide timely, thorough peer-review reports receive vouchers entitling them to a discount on the APC of their next publication in any MDPI journal, in appreciation of the work done.
Impact Factor:
1.6 (2023)
Latest Articles
Prospective Review of Magneto-Resistive Current Sensors with High Sensitivity and Wide Temperature Range
J. Low Power Electron. Appl. 2024, 14(3), 43; https://doi.org/10.3390/jlpea14030043 - 19 Aug 2024
Abstract
Current sensors play a vital role in power systems, industrial production, smart devices and other fields, which can provide critical current information in the systems for the safety and efficiency managements. The development of magneto-resistive effect technology in recent years expedites the research
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Current sensors play a vital role in power systems, industrial production, smart devices and other fields, which can provide critical current information in the systems for the safety and efficiency managements. The development of magneto-resistive effect technology in recent years expedites the research process of the current sensors in industrial-level applications. In the review, starting with the development status of the current sensors, the physical mechanisms of the relevant magneto-resistive effects and their early applications as the current sensors are introduced. Several design methods of the magnetic sensors, as well as their merits and shortcomings, are summarized. The performance parameters of the magnetic sensors based on AMR, GMR, TMR and Hall effects are reviewed, including the front-end amplification circuits and conditioning circuits. The industrial applications of the current sensors in the fields of automobiles and photovoltaic inverters are enumerated. The criterions for the current sensors to be used in different scenarios are discussed. In the future, it is imperative to continue the research and development of novel current sensors in order to satisfy the increasingly stringent demands of the industrial developments, in terms of the performance, cost and reliability of the current sensors.
Full article
Open AccessArticle
Field-Programmable Gate Array Architecture for the Discrete Orthonormal Stockwell Transform (DOST) Hardware Implementation
by
Martin Valtierra-Rodriguez, Jose-Luis Contreras-Hernandez, David Granados-Lieberman, Jesus Rooney Rivera-Guillen, Juan Pablo Amezquita-Sanchez and David Camarena-Martinez
J. Low Power Electron. Appl. 2024, 14(3), 42; https://doi.org/10.3390/jlpea14030042 - 7 Aug 2024
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Time–frequency analysis is critical in studying linear and non-linear signals that exhibit variations across both time and frequency domains. Such analysis not only facilitates the identification of transient events and extraction of key features but also aids in displaying signal properties and pattern
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Time–frequency analysis is critical in studying linear and non-linear signals that exhibit variations across both time and frequency domains. Such analysis not only facilitates the identification of transient events and extraction of key features but also aids in displaying signal properties and pattern recognition. Recently, the Discrete Orthonormal Stockwell Transform (DOST) has become increasingly utilized in many specialized signal processing tasks. Given its growing importance, this work proposes a reconfigurable field-programmable gate array (FPGA) architecture designed to efficiently implement the DOST algorithm on cost-effective FPGA chips. An accompanying MATLAB app enables the automatic configuration of the DOST method for varying sizes (64, 128, 256, 512, and 1024 points). For the implementation, a Cyclone V series FPGA device from Intel Altera, featuring the 5CSEMA5F31C6N chip, is used. To provide a complete hardware solution, the proposed DOST core has been integrated into a hybrid ARM-HPS (Advanced RISC Machine–Hard Processor System) control unit, which allows the control of different peripherals, such as communication protocols and VGA-based displays. Results show that less than 5% of the chip’s resources are occupied, indicating a low-cost architecture that can be easily integrated into other FPGA structures or hardware systems for diverse applications. Moreover, the accuracy of the proposed FPGA-based implementation is underscored by a root mean squared error of 6.0155 × 10−3 when compared with results from floating-point processors, highlighting its accuracy.
Full article
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Open AccessArticle
A Gate-Level Power Estimation Approach with a Comprehensive Definition of Thresholds for Classification and Filtering of Inertial Glitch Pulses
by
Benjamin Villegas and Ioannis Vourkas
J. Low Power Electron. Appl. 2024, 14(3), 41; https://doi.org/10.3390/jlpea14030041 - 5 Aug 2024
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Estimation of power consumption in digital circuits is performed at gate-level simulation. Its accuracy depends on the models of gate delays that capture the effects of spurious signal transitions, called “glitches”. Electronic Design Automation (EDA) software considers inertial gate delays and represses a
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Estimation of power consumption in digital circuits is performed at gate-level simulation. Its accuracy depends on the models of gate delays that capture the effects of spurious signal transitions, called “glitches”. Electronic Design Automation (EDA) software considers inertial gate delays and represses a glitch in the cell’s output if its width is below a threshold. Selecting threshold values for the inertial glitch classification and filtering is crucial for precise power estimations. In this direction, we explore the effectiveness of automatically adjusting such thresholds on a cell-specific basis according to the local cell’s information. We used a commercial industry-standard gate-level power estimation tool and a 32 nm CMOS standard cell library. Via power measurements in circuit simulations, we created customized lookup tables for each library cell employed in the benchmark circuits. We compared the proposed approach’s performance with other methods for glitch threshold definition. Our method demonstrated good power estimation accuracy while presenting the lowest mean absolute error among all the cells of the circuits under test and the smallest standard deviation. The latter suggests that the proposed method achieves better cell-specific accuracy, which is expected to allow for more precise circuit-level power estimations in complex circuits with a large number of combinational cells.
Full article
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Open AccessArticle
A 0.5 V, 32 nW Compact Inverter-Based All-Filtering Response Modes Gm-C Filter for Bio-Signal Processing
by
Ali Namdari, Orazio Aiello and Daniele D. Caviglia
J. Low Power Electron. Appl. 2024, 14(3), 40; https://doi.org/10.3390/jlpea14030040 - 4 Aug 2024
Abstract
A low-power, low-voltage universal multi-mode Gm-C filter using a 180 nm TSMC technology node is presented in this paper. The proposed filter employs only three transconductance operational amplifiers (OTAs) operating in the sub-threshold region with a supply voltage of 0.5 V, resulting in
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A low-power, low-voltage universal multi-mode Gm-C filter using a 180 nm TSMC technology node is presented in this paper. The proposed filter employs only three transconductance operational amplifiers (OTAs) operating in the sub-threshold region with a supply voltage of 0.5 V, resulting in a power consumption of 32 nW. Moreover, without additional active elements, the proposed circuit can operate various functional modes, such as voltage, current, transconductance, and trans-resistance. The filter’s frequency, centered at 462 Hz, and a compact and low-power solution showing only 93.5 µVrms input-referred noise make the proposed filter highly suitable for bio-signal processing.
Full article
(This article belongs to the Special Issue Ultra-Low-Power ICs for the Internet of Things Vol. 2)
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Open AccessArticle
An Ultra-Low-Voltage Approach to Accurately Set the Quiescent Current of Digital Standard Cells Used for Analog Design and Its Application on an Inverter-Based Operational Transconductance Amplifier
by
Riccardo Della Sala, Francesco Centurelli and Giuseppe Scotti
J. Low Power Electron. Appl. 2024, 14(3), 39; https://doi.org/10.3390/jlpea14030039 - 24 Jul 2024
Abstract
An approach to design analog building blocks based on digital standard cells is presented in this work. By ensuring that every CMOS inverter from a standard-cell library operates with a well-defined quiescent current and output voltage, the suggested method makes it possible to
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An approach to design analog building blocks based on digital standard cells is presented in this work. By ensuring that every CMOS inverter from a standard-cell library operates with a well-defined quiescent current and output voltage, the suggested method makes it possible to construct analog circuits that are resistant against PVT variations. The method uses the local supply voltages connected to the source terminals of the p-channel and n-channel MOS transistors of the standard-cell inverters as control inputs. It is based on adaptive supply voltage generator (ASVG) reusable blocks, which are comparable to those used in digital applications to handle process variations. All of the standard-cell inverters used for analog functions receive the local supply voltages produced by the ASVGs, which enable setting each cell’s quiescent current to a multiple of a reference current and each cell’s static output voltage to an appropriate reference voltage. Both the complete custom design of the ASVG blocks and a theoretical study of the feedback loop of the ASVG are presented. An application example through the design of a fully synthesizable two-stage operational transconductance amplifier (OTA) is also provided. The TSMC 180 nm CMOS technology has been used to implement both the OTA and the ASV generators. Simulation results have demonstrated that the proposed approach allows to accurately set the quiescent current of standard-cell inverters, dramatically reducing the effect of PVT variations on the pmain performance parameters of the standard-cell-based two-stage OTA.
Full article
(This article belongs to the Special Issue Ultra-Low-Power ICs for the Internet of Things Vol. 2)
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Open AccessArticle
A 0.064 mm2 16-Channel In-Pixel Neural Front End with Improved System Common-Mode Rejection Exploiting a Current-Mode Summing Approach
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Giovanni Nicolini, Alessandro Fava, Francesco Centurelli and Giuseppe Scotti
J. Low Power Electron. Appl. 2024, 14(3), 38; https://doi.org/10.3390/jlpea14030038 - 13 Jul 2024
Abstract
In this work, we introduce the design of a 16-channel in-pixel neural analog front end that employs a current-based summing approach to establish a common-mode feedback loop. The primary aim of this novel structure is to enhance both the system common-mode rejection ratio
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In this work, we introduce the design of a 16-channel in-pixel neural analog front end that employs a current-based summing approach to establish a common-mode feedback loop. The primary aim of this novel structure is to enhance both the system common-mode rejection ratio (SCMRR) and the common-mode interference (CMI) range. Compared to more conventional designs, the proposed front end utilizes DC-coupled inverter-based main amplifiers, which significantly reduce the occupied on-chip area. Additionally, the current-based implementation of the CMFB loop obviates the need for voltage buffers, replacing them with simple common-gate transistors, which, in turn, decreases both area occupancy and power consumption. The proposed architecture is further examined from an analytical standpoint, providing a comprehensive evaluation through design equations of its performance in terms of gain, common-mode rejection, and noise power. A 50 m × 65 m compact layout of the pixel amplifiers that make up the recording channels of the front end was designed using a 180 nm CMOS process. Simulations conducted in Cadence Virtuoso reveal an SCMRR of 80.5 dB and a PSRR of 72.58 dB, with a differential gain of 44 dB and a bandwidth that fully encompasses the frequency range of the bio-signals that can be theoretically captured by the neural probe. The noise integrated in the range between 1 Hz and 7.5 kHz results in an input-referred noise (IRN) of 4.04 . Power consumption is also tested, with a measured value of 3.77 W per channel, corresponding to an overall consumption of about 60 W. To test its robustness with respect to PVT and mismatch variations, the front end is evaluated through extensive parametric simulations and Monte Carlo simulations, revealing favorable results.
Full article
(This article belongs to the Special Issue Ultra-Low-Power ICs for the Internet of Things Vol. 2)
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Open AccessArticle
A 1.87 µW Capacitively Coupled Chopper Instrumentation Amplifier with a 0.36 mV Output Ripple and a 1.8 GΩ Input Impedance for Biomedical Recording
by
Xuan Phuong Tran, Xuan Thuc Kieu, Xuan Thanh Pham, Duy Phong Pham and Manh Kha Hoang
J. Low Power Electron. Appl. 2024, 14(3), 37; https://doi.org/10.3390/jlpea14030037 - 10 Jul 2024
Abstract
Chopper and capacitively coupled techniques are employed in instrumentation amplifiers to create capacitively coupled chopper instrumentation amplifiers (CCIAs) that obtain a high noise power efficiency. However, the CCIA has some disadvantages due to the chopper technique, namely chopper ripple and a low input
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Chopper and capacitively coupled techniques are employed in instrumentation amplifiers to create capacitively coupled chopper instrumentation amplifiers (CCIAs) that obtain a high noise power efficiency. However, the CCIA has some disadvantages due to the chopper technique, namely chopper ripple and a low input impedance. The amplifier can easily saturate due to the chopper ripple of the CCIA, especially in extremely low noise problems. Therefore, ripple attenuation is required when designing CCIAs. To record biomedical information, a CCIA with a low power consumption and a low noise, low output ripple, and high input impedance (Zin) is presented in this paper. By introducing a ripple attenuation loop (RAL) including the chopping offset amplifier and a low pass filter, the chopping ripple can be reduced to 0.36 mV. To increase the Zin of the CCIA up to 1.8 GΩ, an impedance boost loop (IBL) is added. By using 180 nm CMOS technology, the 0.123 mm2 CCIA consumes 1.87 µW at a supply voltage of 1 V. According to the simulation results using Cadance, the proposed CCIA architecture achieves a noise floor of 136 nV/√Hz, an input-referred noise (IRN) of 2.16 µVrms, a closed-loop gain of 40 dB, a power supply rejection ratio (PSRR) of 108.6 dB, and a common-mode rejection ratio (CMRR) of 118.7 dB. The proposed CCIA is a helpful method for monitoring neural potentials.
Full article
(This article belongs to the Special Issue Ultra-Low-Power ICs for the Internet of Things Vol. 2)
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Open AccessArticle
0.35 V Subthreshold Bulk-Driven CMOS Second-Generation Current Conveyor
by
Muhammad Omer Shah, Manfredi Caruso and Salvatore Pennisi
J. Low Power Electron. Appl. 2024, 14(3), 36; https://doi.org/10.3390/jlpea14030036 - 7 Jul 2024
Abstract
This study describes a high-performance second-generation Current Conveyor (CCII) operating at 0.35 V and achieving rail-to-rail operation at the Y terminal and class AB current drive at the X and Z terminals. The solution utilizes a low-voltage subthreshold bulk-driven CMOS OTA that was
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This study describes a high-performance second-generation Current Conveyor (CCII) operating at 0.35 V and achieving rail-to-rail operation at the Y terminal and class AB current drive at the X and Z terminals. The solution utilizes a low-voltage subthreshold bulk-driven CMOS OTA that was experimentally developed earlier, making systematic use of body terminals to improve small-signal and large-signal performance. The circuit has a high open-loop voltage gain and uses cascoded current mirror topologies, resulting in precise voltage and current transfer with bandwidths of 1.33 MHz and 2.13 MHz, respectively. The CCII offers a linear current drive up to 2.5 µA while consuming a total quiescent current of 2.86 µA (758 nA in the output branches), displaying one the highest figures of merit in terms of current utilization for sub 1 V solutions.
Full article
(This article belongs to the Special Issue Ultra-Low-Power ICs for the Internet of Things Vol. 2)
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Open AccessArticle
Spin–Orbit Coupling Free Nonlinear Spin Hall Effect in a Triangle-Unit Collinear Antiferromagnet with Magnetic Toroidal Dipole
by
Satoru Hayami
J. Low Power Electron. Appl. 2024, 14(3), 35; https://doi.org/10.3390/jlpea14030035 - 3 Jul 2024
Abstract
We investigate emergent conductive phenomena triggered by collinear antiferromagnetic orderings. We show that an up-down-zero spin configuration in a triangle cluster leads to linear and nonlinear spin conductivities even without the relativistic spin–orbit coupling; the linear spin conductivity is Drude-type, while the nonlinear
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We investigate emergent conductive phenomena triggered by collinear antiferromagnetic orderings. We show that an up-down-zero spin configuration in a triangle cluster leads to linear and nonlinear spin conductivities even without the relativistic spin–orbit coupling; the linear spin conductivity is Drude-type, while the nonlinear spin conductivity has Hall-type characterization. We demonstrate the emergence of both spin conductivities in a breathing kagome system consisting of a triangle cluster. The nonlinear spin conductivity becomes larger than the linear one when the Fermi level lies near the region where a small partial band gap opens. Our results indicate that collinear antiferromagnets with triangular geometry give rise to rich spin conductive phenomena.
Full article
(This article belongs to the Special Issue Recent Advances in Spintronics)
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Open AccessArticle
Design and Analysis of Self-Tanked Stepwise Charging Circuit for Four-Phase Adiabatic Logic
by
William Morell and Jin-Woo Choi
J. Low Power Electron. Appl. 2024, 14(3), 34; https://doi.org/10.3390/jlpea14030034 - 27 Jun 2024
Abstract
Adiabatic logic has been proposed as a method for drastically reducing power consumption in specialized low-power circuits. They often require specialized clock drivers that also function as the main power supply, in contrast to standard CMOS logic, and these power clocks are often
[...] Read more.
Adiabatic logic has been proposed as a method for drastically reducing power consumption in specialized low-power circuits. They often require specialized clock drivers that also function as the main power supply, in contrast to standard CMOS logic, and these power clocks are often a point of difficulty in the design process. A novel, stepwise charging driver circuit for four-phase adiabatic logic is proposed and validated through a simulation study. The proposed circuit consists of two identical driver circuits each driving two opposite adiabatic logic phases. Its performance relative to ideal step-charging and a standard CMOS across mismatched phase loads is analyzed, and new best practices are established. It is compared to a reference circuit consisting of one driver circuit for each phase along with a paired on-chip tank capacitor. The proposed driver uses opposite logic phases to act as the tank capacitor for each other in a “self-tanked” fashion. Each circuit was simulated in 15 nm FinFET across a variety of frequencies for an arbitrary logic operation. Both circuits showed comparable power consumption at all frequencies tested, yet the proposed driver uses fewer transistors and control signals and eliminates the explicit tank capacitors entirely, vastly reducing circuit area, complexity, and development time.
Full article
(This article belongs to the Special Issue Ultra-Low-Power ICs for the Internet of Things Vol. 2)
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Open AccessArticle
OptimalNN: A Neural Network Architecture to Monitor Chemical Contamination in Cancer Alley
by
Uchechukwu Leo Udeji and Martin Margala
J. Low Power Electron. Appl. 2024, 14(2), 33; https://doi.org/10.3390/jlpea14020033 - 10 Jun 2024
Abstract
The detrimental impact of toxic chemicals, gas, and oil spills in aquatic environments poses a severe threat to plants, animals, and human life. Regions such as Cancer Alley exemplify the profound consequences of inadequately controlled chemical spills, significantly affecting the local community. Given
[...] Read more.
The detrimental impact of toxic chemicals, gas, and oil spills in aquatic environments poses a severe threat to plants, animals, and human life. Regions such as Cancer Alley exemplify the profound consequences of inadequately controlled chemical spills, significantly affecting the local community. Given the far-reaching effects of these spills, it has become imperative to devise an efficient method for early monitoring, estimation, and cleanup, utilizing affordable and effective techniques. In this research, we explore the application of U-shaped neural Network (UNET) and U-shaped neural network transformer (UNETR) neural network models designed for the image segmentation of chemical and oil spills. Our models undergo training using the Commonwealth Scientific and Industrial Research Organization (CSIRO) dataset and the Oil Spill Detection dataset, employing a specialized filtering technique to enhance detection accuracy. We achieved training accuracies of 95.35% and 91% by applying UNET on the Oil Spill and the CSIRO datasets after 50 epochs of training, respectively. We also achieved a training accuracy of 75% by applying UNETR to the Oil Spill dataset. Additionally, we integrated mixed precision to expedite the model training process, thus maximizing data throughput. To further accelerate our implementation, we propose the utilization of the Field Programmable Gate Array (FPGA) architecture. The results obtained from our study demonstrate improvements in inference latency on FPGA.
Full article
(This article belongs to the Special Issue Advancements in Low-Power Ubiquitous Sensing, Computing, and Communication Interfaces for IoT: Circuits, Systems, and Applications)
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Open AccessArticle
A Power-Efficient 16-bit 1-MS/s Successive Approximation Register Analog-to-Digital Converter with Digital Calibration in 0.18 μm Complementary Metal Oxide Semiconductor
by
Xinyuan He, Weifeng Qiao, Xinpeng Xing and Haigang Feng
J. Low Power Electron. Appl. 2024, 14(2), 32; https://doi.org/10.3390/jlpea14020032 - 4 Jun 2024
Abstract
A power-efficient 16-bit 1-MS/s successive approximation register (SAR) analog-to-digital converter (ADC) is presented in this paper. High-bit sampling makes the bridge capacitance in the digital-to-analog converter (DAC) a unit one, eliminating fractional capacitance mismatch. The high-precision comparator is composed of a four-stage preamplifier
[...] Read more.
A power-efficient 16-bit 1-MS/s successive approximation register (SAR) analog-to-digital converter (ADC) is presented in this paper. High-bit sampling makes the bridge capacitance in the digital-to-analog converter (DAC) a unit one, eliminating fractional capacitance mismatch. The high-precision comparator is composed of a four-stage preamplifier and a strong-arm latch, with auto-zeroing used to mitigate input offset further. Digital foreground calibration based on low-bit weight is implemented to correct DAC capacitance mismatch. The post-layout simulation results show that the core ADC achieves 95.61 dB SNDR and 105.1 dB SFDR with calibration, consuming 5.4 mW power under a 3.3 V supply voltage, corresponding to a Schreier figure of merit (FoM) of 175.3 dB. The ADC core area is 1.06 mm2 in the 180 nm CMOS technology.
Full article
(This article belongs to the Special Issue Analog/Mixed-Signal Integrated Circuit Design)
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Open AccessArticle
Modeling Excitable Cells with Memristors
by
Maheshwar Sah, Alon Ascoli, Ronald Tetzlaff, Vetriveeran Rajamani and Ram Kaji Budhathoki
J. Low Power Electron. Appl. 2024, 14(2), 31; https://doi.org/10.3390/jlpea14020031 - 28 May 2024
Cited by 1
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This paper presents an in-depth analysis of an excitable membrane of a biological system by proposing a novel approach that the cells of the excitable membrane can be modeled as the networks of memristors. We provide compelling evidence from the Chay neuron model
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This paper presents an in-depth analysis of an excitable membrane of a biological system by proposing a novel approach that the cells of the excitable membrane can be modeled as the networks of memristors. We provide compelling evidence from the Chay neuron model that the state-independent mixed ion channel is a nonlinear resistor, while the state-dependent voltage-sensitive potassium ion channel and calcium-sensitive potassium ion channel function as generic memristors from the perspective of electrical circuit theory. The mechanisms that give rise to periodic oscillation, aperiodic (chaotic) oscillation, spikes, and bursting in an excitable cell are also analyzed via a small-signal model, a pole-zero diagram of admittance functions, local activity, the edge of chaos, and the Hopf bifurcation theorem. It is also proved that the zeros of the admittance functions are equivalent to the eigen values of the Jacobian matrix, and the presence of the positive real parts of the eigen values between the two bifurcation points lead to the generation of complicated electrical signals in an excitable membrane. The innovative concepts outlined in this paper pave the way for a deeper understanding of the dynamic behavior of excitable cells, offering potent tools for simulating and exploring the fundamental characteristics of biological neurons.
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Open AccessArticle
A Simple, Robust, and Versatile MATLAB Formulation of the Dynamic Memdiode Model for Bipolar-Type Resistive Random Access Memory Devices
by
Emili Salvador, Rosana Rodriguez and Enrique Miranda
J. Low Power Electron. Appl. 2024, 14(2), 30; https://doi.org/10.3390/jlpea14020030 - 28 May 2024
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Modeling in an emerging technology like RRAM devices is one of the pivotal concerns for its development. In the current bibliography, most of the models face difficulties in implementing or simulating unconventional scenarios, particularly when dealing with complex input signals. In addition, circuit
[...] Read more.
Modeling in an emerging technology like RRAM devices is one of the pivotal concerns for its development. In the current bibliography, most of the models face difficulties in implementing or simulating unconventional scenarios, particularly when dealing with complex input signals. In addition, circuit simulators like Spice require long running times for high-resolution results because of their internal mathematical implementation. In this work, a fast, simple, robust, and versatile model for RRAM devices built in MATLAB is presented. The proposed model is a recursive and discretized version of the dynamic memdiode model (DMM) for bipolar-type resistive switching devices originally implemented in LTspice. The DMM model basically consists of two coupled equations: one for the current (non-linear current generator) and a second one for the memory state of the device (time-dependent differential equation). This work presents an easy-to-use tool for researchers to reproduce the experimental behavior of their devices and predict the outcome from non-trivial experiments. Three study cases are reported, aimed at capturing different phenomenologies: a frequency effect study, a cycle-to-cycle variability fit, and a stochastic resonance impact analysis.
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Open AccessArticle
Coordination of SRF-PLL and Grid Forming Inverter Control in Microgrid with Solar PV and Energy Storage
by
V. Vignesh Babu, J. Preetha Roselyn and Prabha Sundaravadivel
J. Low Power Electron. Appl. 2024, 14(2), 29; https://doi.org/10.3390/jlpea14020029 - 21 May 2024
Cited by 1
Abstract
Recently, there has been a huge advancement in renewable energy integration in power systems. Power converters with grid-forming or grid-following topologies are typically employed to link these decentralized power sources to the grid. However, because distributed generation has less inertia than synchronous generators,
[...] Read more.
Recently, there has been a huge advancement in renewable energy integration in power systems. Power converters with grid-forming or grid-following topologies are typically employed to link these decentralized power sources to the grid. However, because distributed generation has less inertia than synchronous generators, their use of renewable energy sources threatens the electrical grid’s reliability. Suitable control approaches for ensuring frequency and voltage stability in the grid-connected form of operation are established in this study, which offers dynamic, seamless power switching in the islanded mode of operation. In this research, effective Phase Locked Loop (PLL) techniques for grid-forming (GFM) and grid-following (GFL) converters are designed to achieve a smooth transition from grid-tied to islanded mode of operation. In this work, PLL configurations are implemented while considering the active and reactive power, frequency, voltage, and current parameters of the system, and ensuring voltage and frequency stability. The simulation results in a microgrid network that ensures a smooth transition of power transfer while switching between modes of operation, and supports the voltage and frequency stability of the system.
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(This article belongs to the Special Issue Energy Aware Solutions for Battery Management Systems)
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Open AccessArticle
A Microdevice in a Submicron CMOS for Closed-Loop Deep-Brain Stimulation (CLDBS)
by
Tiago Matheus Nordi, Rodrigo Gounella, Marcio L. M. Amorim, Maximiliam Luppe, João Navarro Soares Junior, Joao L. Afonso, Vitor Monteiro, Jose A. Afonso, Erich Talamoni Fonoff, Eduardo Colombari and João Paulo Carmo
J. Low Power Electron. Appl. 2024, 14(2), 28; https://doi.org/10.3390/jlpea14020028 - 17 May 2024
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Deep-brain stimulation (DBS) is a highly effective and safe medical treatment that improves the lives of patients with a wide range of neurological and psychiatric diseases. It has been established as a first-line tool in the treatment of these conditions for the past
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Deep-brain stimulation (DBS) is a highly effective and safe medical treatment that improves the lives of patients with a wide range of neurological and psychiatric diseases. It has been established as a first-line tool in the treatment of these conditions for the past two decades. Closed-loop deep-brain stimulation (CLDBS) advances this tool further by automatically adjusting the stimulation parameters in real time based on the brain’s response. In this context, this paper presents a low-noise amplifier (LNA) and a neurostimulator circuit fabricated using the low-power/low-voltage 65 nm CMOS process from TSMC. The circuits are specifically designed for implantable applications. To achieve the best tradeoff between input-referred noise and power consumption, metaheuristic algorithms were employed to determine and optimize the dimensions of the LNA devices during the design phase. Measurement results showed that the LNA had a gain of 41.2 dB; a 3 dB bandwidth spanning over three decades, from 1.5 Hz to 11.5 kHz; a power consumption of 5.9 µW; and an input-referred noise of 3.45 µVRMS, from 200 Hz to 11.5 kHz. The neurostimulator circuit is a programmable Howland current pump. Measurements have shown its capability to generate currents with arbitrary shapes and ranging from −325 µA to +318 µA. Simulations indicated a quiescent power consumption of 0.13 µW, with zero neurostimulation current. Both the LNA and the neurostimulator circuits are supplied with a 1.2 V voltage and occupy a microdevice area of 145 µm × 311 µm and 88 µm × 89 µm, respectively, making them suitable for implantation in applications involving closed-loop deep-brain stimulation.
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Open AccessReview
A Survey of Short-Range Wireless Communication for Ultra-Low-Power Embedded Systems
by
Billy Baker, John Woods, Martin J. Reed and Martin Afford
J. Low Power Electron. Appl. 2024, 14(2), 27; https://doi.org/10.3390/jlpea14020027 - 14 May 2024
Abstract
Wireless short-range communication has become widespread in the modern era, partly due to the advancement of the Internet of Things (IoT) and smart technology. This technology is now utilized in various sectors, including lighting, medical, and industrial applications. This article aims to examine
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Wireless short-range communication has become widespread in the modern era, partly due to the advancement of the Internet of Things (IoT) and smart technology. This technology is now utilized in various sectors, including lighting, medical, and industrial applications. This article aims to examine the historical, present, and forthcoming advancements in wireless short-range communication. Additionally, the review will analyze the modifications made to communication protocols, such as Bluetooth, RFID and NFC, in order to better accommodate modern applications. Batteryless technology, particularly batteryless NFC, is an emerging development in short-range wireless communication that combines power and data transmission into a single carrier. This modification will significantly influence the trajectory of short-range communication and its applications. The foundation of most low-power, short-range communication applications relies on an ultra-low-power microcontroller. Therefore, this study will encompass an analysis of ultra-low-power microcontrollers and an investigation into the potential limitations they might encounter in the future. In addition to offering a thorough examination of current Wireless short-range communication, this article will also attempt to forecast future patterns and identify possible obstacles that future research may address.
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(This article belongs to the Special Issue Ultra-Low-Power ICs for the Internet of Things Vol. 2)
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Open AccessArticle
Multibeam Wideband Transmit Beamforming Using 2D Sparse FIR Trapezoidal Filters
by
Nadeeshan Dissanayake, Chamira U. S. Edussooriya, Chamith Wijenayake and Arjuna Madanayake
J. Low Power Electron. Appl. 2024, 14(2), 26; https://doi.org/10.3390/jlpea14020026 - 28 Apr 2024
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A low-complexity multibeam wideband transmit beamformer using a 2D sparse FIR filter design capable of multiple beams is proposed as a digital building block for fully digital beamformers. The 2D sparse FIR filter has multiple trapezoid-shaped passbands pertaining to wideband beams aimed at
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A low-complexity multibeam wideband transmit beamformer using a 2D sparse FIR filter design capable of multiple beams is proposed as a digital building block for fully digital beamformers. The 2D sparse FIR filter has multiple trapezoid-shaped passbands pertaining to wideband beams aimed at particular directions. The proposed multibeam digital beamformer drives a uniform linear array of wideband antenna elements to achieve the wideband multibeam transmit-mode signals desired by the communication system. The 2D sparse FIR filter is designed to be optimal in the minimax sense using convex optimization techniques. Full-wave electromagnetic simulations using real antenna models confirm that the proposed wideband transmit beamformer can achieve multibeam transmission in the 1.3–2.8 GHz frequency range, with more than 70% fractional bandwidth. Furthermore, the adoption of the wideband transmit multibeam beamformer leads to a significant reduction in digital arithmetic (computational) complexity compared with previously reported wideband transmit beamformers of similar transfer function type, without deteriorating beam directionality and causing increases in the side-lobe level. The proposed sparse 2D FIR multibeam beamformer architecture is well-suited for both sub-6 GHz (legacy) band transmit beamforming, frequency range three (FR3) beamforming up to 28 GHz, and mmWave operation for emerging 5G/6G applications.
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Open AccessArticle
Gate-Level Hardware Priority Resolvers for Embedded Systems
by
Padmanabhan Balasubramanian and Douglas L. Maskell
J. Low Power Electron. Appl. 2024, 14(2), 25; https://doi.org/10.3390/jlpea14020025 - 17 Apr 2024
Abstract
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An N-bit priority resolver having N inputs and N outputs functions as polling hardware in an embedded system, enabling access to a resource when multiple devices initiate access requests at its inputs which may be located on-chip or off-chip. Subsystems such as data
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An N-bit priority resolver having N inputs and N outputs functions as polling hardware in an embedded system, enabling access to a resource when multiple devices initiate access requests at its inputs which may be located on-chip or off-chip. Subsystems such as data buses, comparators, fixed- and floating-point arithmetic units, interconnection network routers, etc., utilize the priority resolver function. In the literature, there are many transistor-level designs for the priority resolver based on dynamic CMOS logic, some of which are modular and others are not. This article presents a novel gate-level modular design of priority resolvers that can accommodate any number of inputs and outputs. Based on our modular design architecture, small-size priority resolvers can be conveniently combined to form medium- or large-size priority resolvers along with extra logic. The proposed modular design approach helps to reduce the coding complexity compared to the conventional direct design approach and facilitates scalability. We discuss the gate-level implementation of 4-, 8-, 16-, 32-, 64-, and 128-bit priority resolvers based on the direct and modular approaches and provide a performance comparison between these based on the design metrics. According to the modular approach, different sizes of priority resolver modules were used to implement larger-size priority resolvers. For example, a 4-bit priority resolver module was used to implement 8-, 16-, 32-, 64-, and 128-bit priority resolvers in a modular fashion. We used a 28 nm CMOS standard digital cell library and Synopsys EDA tools to synthesize the priority resolvers. The estimated design metrics show that the modular approach tends to facilitate increasing reductions in delay and power-delay product (PDP) compared to the direct approach, especially as the size of the priority resolver increases. For example, a 32-bit modular priority resolver utilizing 16-bit priority resolver modules had a 39.4% reduced delay and a 23.1% reduced PDP compared to a directly implemented 32-bit priority resolver, and a 128-bit modular priority resolver utilizing 16-bit priority resolver modules had a 71.8% reduced delay and a 61.4% reduced PDP compared to a directly implemented 128-bit priority resolver.
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Open AccessBrief Report
Efficient Addition Circuits Using Three-Gate Reconfigurable Field Effect Transistors
by
Fanny Spagnolo, Pasquale Corsonello, Fabio Frustaci and Stefania Perri
J. Low Power Electron. Appl. 2024, 14(2), 24; https://doi.org/10.3390/jlpea14020024 - 14 Apr 2024
Abstract
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Reconfigurable FETs (RFETs) are widely recognized as a promising way to overcome conventional CMOS architectures. This paper presents novel addition circuit intentionally designed to exploit the ability of RFETs to operate efficiently on demand as n- or p-type FETs. First, a novel Full
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Reconfigurable FETs (RFETs) are widely recognized as a promising way to overcome conventional CMOS architectures. This paper presents novel addition circuit intentionally designed to exploit the ability of RFETs to operate efficiently on demand as n- or p-type FETs. First, a novel Full Adder (FA) is proposed and characterized. A comparison with other designs shows that the proposed FA achieves a worst-case delay and a dynamic power consumption of up to 43.5% and 79% lower. As a drawback, in terms of the estimated area, it is up to 32% larger than the competitors. Then, the new FA is used to implement Ripple-Carry Adders (RCAs). A 32-bit adder designed as proposed herein reaches an energy–delay product (EDP) ~25.7× and ~141× lower than its CMOS and the RFET-based counterparts.
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