ADC0808 ADC0809 8-Bit mP Compatible A D Converters with 8-Channel Multiplexer

November 1995

ADC0808 ADC0809 8-Bit mP Compatible A D Converters with 8-Channel Multiplexer

General Description
The ADC0808 ADC0809 data acquisition component is a monolithic CMOS device with an 8-bit analog-to-digital converter 8-channel multiplexer and microprocessor compatible control logic The 8-bit A D converter uses successive approximation as the conversion technique The converter features a high impedance chopper stabilized comparator a 256R voltage divider with analog switch tree and a successive approximation register The 8-channel multiplexer can directly access any of 8-single-ended analog signals The device eliminates the need for external zero and fullscale adjustments Easy interfacing to microprocessors is provided by the latched and decoded multiplexer address inputs and latched TTL TRI-STATE outputs The design of the ADC0808 ADC0809 has been optimized by incorporating the most desirable aspects of several A D conversion techniques The ADC0808 ADC0809 offers high speed high accuracy minimal temperature dependence excellent long-term accuracy and repeatability and consumes minimal power These features make this device ideally suited to applications from process and machine control to consumer and automotive applications For 16channel multiplexer with common output (sample hold port) see ADC0816 data sheet (See AN-247 for more information )

Features
Y Y

Y Y Y Y Y Y Y Y

Easy interface to all microprocessors Operates ratiometrically or with 5 VDC or analog span adjusted voltage reference No zero or full-scale adjust required 8-channel multiplexer with address logic 0V to 5V input range with single 5V power supply Outputs meet TTL voltage level specifications Standard hermetic or molded 28-pin DIP package 28-pin molded chip carrier package ADC0808 equivalent to MM74C949 ADC0809 equivalent to MM74C949-1

Key Specifications
Y Y Y Y Y

Resolution Total Unadjusted Error Single Supply Low Power Conversion Time

8 Bits LSB and g 1 LSB 5 VDC 15 mW 100 ms

Block Diagram

See Ordering Information

TL H 5672 1
TRI-STATE is a registered trademark of National Semiconductor Corp C1996 National Semiconductor Corporation TL H 5672 RRD-B30M36 Printed in U S A

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Absolute Maximum Ratings (Notes 1

2)

Operating Conditions (Notes 1

Temperature Range (Note 1) ADC0808CJ ADC0808CCJ ADC0808CCN ADC0809CCN ADC0808CCV ADC0809CCV Range of VCC (Note 1)

If Military Aerospace specified devices are required please contact the National Semiconductor Sales Office Distributors for availability and specifications Supply Voltage (VCC) (Note 3) 6 5V b 0 3V to (VCC a 0 3V) Voltage at Any Pin Except Control Inputs b 0 3V to a 15V Voltage at Control Inputs (START OE CLOCK ALE ADD A ADD B ADD C) b 65 C to a 150 C Storage Temperature Range 875 mW Package Dissipation at TA e 25 C Lead Temp (Soldering 10 seconds) Dual-In-Line Package (plastic) 260 C Dual-In-Line Package (ceramic) 300 C Molded Chip Carrier Package Vapor Phase (60 seconds) 215 C Infrared (15 seconds) 220 C ESD Susceptibility (Note 8) 400V

2) TMINsTAsTMAX b 55 C s TA s a 125 C
b 40 C s TA s a 85 C

b 40 C s TA s a 85 C

4 5 VDC to 6 0 VDC

Electrical Characteristics
Converter Specifications VCC e 5 VDC e VREF a VREF(b) e GND TMINsTAsTMAX and fCLK e 640 kHz unless otherwise stated Symbol Parameter ADC0808 Total Unadjusted Error (Note 5) ADC0809 Total Unadjusted Error (Note 5) Input Resistance Analog Input Voltage Range VREF( a ) VREF( a ) a VREF(b) 2 VREF(b) IIN Voltage Top of Ladder Voltage Center of Ladder Voltage Bottom of Ladder Comparator Input Current Measured at Ref(b) fc e 640 kHz (Note 6) Conditions 25 C TMIN to TMAX 0 C to 70 C TMIN to TMAX From Ref( a ) to Ref(b) (Note 4) V( a ) or V(b) Measured at Ref( a ) VCC 2-0 1
b0 1 b2

Min

Typ

Max

Units LSB LSB LSB LSB kX

g g

g1 g1

10 GNDb0 10

25 VCC a 0 10 VCC VCC 2 0

g0 5

VDC V V V

VCC a 0 1 VCC 2 a 0 1

mA

Electrical Characteristics
Digital Levels and DC Specifications ADC0808CJ 4 5VsVCCs5 5V b55 CsTAs a 125 C unless otherwise noted ADC0808CCJ ADC0808CCN ADC0808CCV ADC0809CCN and ADC0809CCV 4 75sVCCs5 25V b40 CsTAs a 85 C unless otherwise noted Symbol ANALOG MULTIPLEXER IOFF( a ) OFF Channel Leakage Current VCC e 5V VIN e 5V TA e 25 C TMIN to TMAX VCC e 5V VIN e 0 TA e 25 C TMIN to TMAX
b 200 b1 0

Parameter

Conditions

Min

Typ

Max

Units

10

200 10

nA mA nA mA

IOFF(b)

OFF Channel Leakage Current

b 10

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Electrical Characteristics (Continued) Digital Levels and DC Specifications ADC0808CJ 4 5VsVCCs5 5V b55 CsTAs a 125 C unless otherwise noted ADC0808CCJ ADC0808CCN ADC0808CCV ADC0809CCN and ADC0809CCV 4 75sVCCs5 25V b40 CsTAs a 85 C unless otherwise noted
Symbol CONTROL INPUTS VIN(1) VIN(0) IIN(1) IIN(0) ICC Logical 1 Input Voltage Logical 0 Input Voltage Logical 1 Input Current (The Control Inputs) Logical 0 Input Current (The Control Inputs) Supply Current VIN e 15V VIN e 0 fCLK e 640 kHz
b1 0

Parameter

Conditions

MIn

Typ

Max

Units

VCCb1 5 15 10

V V mA mA 03 30 mA

DATA OUTPUTS AND EOC (INTERRUPT) VOUT(1) VOUT(0) VOUT(0) IOUT Logical 1 Output Voltage Logical 0 Output Voltage Logical 0 Output Voltage EOC TRI-STATE Output Current IO eb360 mA IO e 1 6 mA IO e 1 2 mA VO e 5V VO e 0
b3

VCCb0 4 0 45 0 45 3

V V V mA mA

Electrical Characteristics
Timing Specifications VCC e VREF( a ) e 5V VREF(b) e GND tr e tf e 20 ns and TA e 25 C unless otherwise noted Symbol tWS tWALE ts tH tD tH1 tH0 t1H t0H tc fc tEOC CIN COUT Parameter Minimum Start Pulse Width Minimum ALE Pulse Width Minimum Address Set-Up Time Minimum Address Hold Time Analog MUX Delay Time From ALE OE Control to Q Logic State OE Control to Hi-Z Conversion Time Clock Frequency EOC Delay Time Input Capacitance TRI-STATE Output Capacitance Conditions MIn Typ 100 100 25 25 1 125 125 90 10 100 640 Max 200 200 50 50 25 250 250 116 1280 8 a 2 mS 10 10 15 15 Units ns ns ns ns mS ns ns mS kHz Clock Periods pF pF

(Figure 5) (Figure 5) (Figure 5) (Figure 5)

RS e 0X (Figure 5) CL e 50 pF RL e 10k (Figure 8) CL e 10 pF RL e 10k (Figure 8) fc e 640 kHz (Figure 5) (Note 7)

(Figure 5)
At Control Inputs At TRI-STATE Outputs

Note 1 Absolute Maximum Ratings indicate limits beyond which damage to the device may occur DC and AC electrical specifications do not apply when operating the device beyond its specified operating conditions Note 2 All voltages are measured with respect to GND unless othewise specified Note 3 A zener diode exists internally from VCC to GND and has a typical breakdown voltage of 7 VDC Note 4 Two on-chip diodes are tied to each analog input which will forward conduct for analog input voltages one diode drop below ground or one diode drop greater than the VCCn supply The spec allows 100 mV forward bias of either diode This means that as long as the analog VIN does not exceed the supply voltage by more than 100 mV the output code will be correct To achieve an absolute 0VDC to 5VDC input voltage range will therefore require a minimum supply voltage of 4 900 VDC over temperature variations initial tolerance and loading Note 5 Total unadjusted error includes offset full-scale linearity and multiplexer errors See Figure 3 None of these A Ds requires a zero or full-scale adjust However if an all zero code is desired for an analog input other than 0 0V or if a narrow full-scale span exists (for example 0 5V to 4 5V full-scale) the reference voltages can be adjusted to achieve this See Figure 13 Note 6 Comparator input current is a bias current into or out of the chopper stabilized comparator The bias current varies directly with clock frequency and has little temperature dependence (Figure 6) See paragraph 4 0 Note 7 The outputs of the data register are updated one clock cycle before the rising edge of EOC Note 8 Human body model 100 pF discharged through a 1 5 kX resistor

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Functional Description
Multiplexer The device contains an 8-channel single-ended analog signal multiplexer A particular input channel is selected by using the address decoder Table I shows the input states for the address lines to select any channel The address is latched into the decoder on the low-to-high transition of the address latch enable signal TABLE I SELECTED ANALOG CHANNEL IN0 IN1 IN2 IN3 IN4 IN5 IN6 IN7 ADDRESS LINE C L L L L H H H H B L L H H L L H H A L H L H L H L H to give fast accurate and repeatable conversions over a wide range of temperatures The converter is partitioned into 3 major sections the 256R ladder network the successive approximation register and the comparator The converters digital outputs are positive true The 256R ladder network approach (Figure 1) was chosen over the conventional R 2R ladder because of its inherent monotonicity which guarantees no missing digital codes Monotonicity is particularly important in closed loop feedback control systems A non-monotonic relationship can cause oscillations that will be catastrophic for the system Additionally the 256R network does not cause load variations on the reference voltage The bottom resistor and the top resistor of the ladder network in Figure 1 are not the same value as the remainder of the network The difference in these resistors causes the output characteristic to be symmetrical with the zero and full-scale points of the transfer curve The first output transition occurs when the analog signal has reached a LSB and succeeding output transitions occur every 1 LSB later up to full-scale The successive approximation register (SAR) performs 8 iterations to approximate the input voltage For any SAR type converter n-iterations are required for an n-bit converter Figure 2 shows a typical example of a 3-bit converter In the ADC0808 ADC0809 the approximation technique is extended to 8 bits using the 256R network

CONVERTER CHARACTERISTICS The Converter The heart of this single chip data acquisition system is its 8bit analog-to-digital converter The converter is designed

TL H 5672 2

FIGURE 1 Resistor Ladder and Switch Tree

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Functional Description

(Continued) comparator drift which has the greatest influence on the repeatability of the device A chopper-stabilized comparator provides the most effective method of satisfying all the converter requirements The chopper-stabilized comparator converts the DC input signal into an AC signal This signal is then fed throught a high gain AC amplifier and has the DC level restored This technique limits the drift component of the amplifier since the drift is a DC component which is not passed by the AC amplifier This makes the entire A D converter extremely insensitive to temperature long term drift and input offset errors

The A D converters successive approximation register (SAR) is reset on the positive edge of the start conversion (SC) pulse The conversion is begun on the falling edge of the start conversion pulse A conversion in process will be interrupted by receipt of a new start conversion pulse Continuous conversion may be accomplished by tying the endof-conversion (EOC) output to the SC input If used in this mode an external start conversion pulse should be applied after power up End-of-conversion will go low between 0 and 8 clock pulses after the rising edge of start conversion The most important section of the A D converter is the comparator It is this section which is responsible for the ultimate accuracy of the entire converter It is also the

Figure 4 shows a typical error curve for the ADC0808 as measured using the procedures outlined in AN-179

FIGURE 2 3-Bit A D Transfer Curve

FIGURE 3 3-Bit A D Absolute Accuracy Curve

TL H 5672 3

FIGURE 4 Typical Error Curve

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Connection Diagrams
Dual-In-Line Package Molded Chip Carrier Package

TL H 567211

Order Number ADC0808CCN ADC0809CCN ADC0808CCJ or ADC0808CJ See NS Package J28A or N28A

TL H 5672 12

Order Number ADC0808CCV or ADC0809CCV See NS Package V28A

Timing Diagram

TL H 5672 4

FIGURE 5

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Typical Performance Characteristics

TL H 5672 5

FIGURE 6 Comparator IIN vs VIN (VCC e VREF e 5V)

FIGURE 7 Multiplexer RON vs VIN (VCC e VREF e 5V)

TRI-STATE Test Circuits and Timing Diagrams

t1H tH1 t1H CL e 10 pF tH1 CL e 50 pF

t0H tH0

t0H CL e 10 pF

tH0 CL e 50 pF

TL H 5672 6

FIGURE 8 7
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Applications Information
OPERATION 1 0 RATIOMETRIC CONVERSION The ADC0808 ADC0809 is designed as a complete Data Acquisition System (DAS) for ratiometric conversion systems In ratiometric systems the physical variable being measured is expressed as a percentage of full-scale which is not necessarily related to an absolute standard The voltage input to the ADC0808 is expressed by the equation VIN DX e VfsbVZ DMAXbDMIN VIN e Input voltage into the ADC0808 Vfs e Full-scale voltage VZ e Zero voltage DX e Data point being measured DMAX e Maximum data limit DMIN e Minimum data limit A good example of a ratiometric transducer is a potentiometer used as a position sensor The position of the wiper is directly proportional to the output voltage which is a ratio of the full-scale voltage across it Since the data is represented as a proportion of full-scale reference requirements are greatly reduced eliminating a large source of error and cost for many applications A major advantage of the ADC0808 ADC0809 is that the input voltage range is equal to the supply range so the transducers can be connected directly across the supply and their outputs connected directly into the multiplexer inputs (Figure 9) Ratiometric transducers such as potentiometers strain gauges thermistor bridges pressure transducers etc are suitable for measuring proportional relationships however many types of measurements must be referred to an absolute standard such as voltage or current This means a system reference must be used which relates the full-scale voltage to the standard volt For example if VCC e VREF e 5 12V then the full-scale range is divided into 256 standard steps The smallest standard step is 1 LSB which is then 20 mV (1) 2 0 RESISTOR LADDER LIMITATIONS The voltages from the resistor ladder are compared to the selected into 8 times in a conversion These voltages are coupled to the comparator via an analog switch tree which is referenced to the supply The voltages at the top center and bottom of the ladder must be controlled to maintain proper operation The top of the ladder Ref( a ) should not be more positive than the supply and the bottom of the ladder Ref(b) should not be more negative than ground The center of the ladder voltage must also be near the center of the supply because the analog switch tree changes from N-channel switches to P-channel switches These limitations are automatically satisfied in ratiometric systems and can be easily met in ground referenced systems

Figure 10 shows a ground referenced system with a separate supply and reference In this system the supply must be trimmed to match the reference voltage For instance if a 5 12V is used the supply should be adjusted to the same voltage within 0 1V

TL H 5672 7

FIGURE 9 Ratiometric Conversion System

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Applications Information (Continued)

The ADC0808 needs less than a milliamp of supply current so developing the supply from the reference is readily accomplished In Figure 11 a ground referenced system is shown which generates the supply from the reference The buffer shown can be an op amp of sufficient drive to supply the milliamp of supply current and the desired bus drive or if a capacitive bus is driven by the outputs a large capacitor will supply the transient supply current as seen in Figure 12 The LM301 is overcompensated to insure stability when loaded by the 10 mF output capacitor The top and bottom ladder voltages cannot exceed VCC and ground respectively but they can be symmetrically less than VCC and greater than ground The center of the ladder voltage should always be near the center of the supply The sensitivity of the converter can be increased (i e size of the LSB steps decreased) by using a symmetrical reference system In Figure 13 a 2 5V reference is symmetrically centered about VCC 2 since the same current flows in identical resistors This system with a 2 5V reference allows the LSB bit to be half the size of a 5V reference system

QOUT e

VIN VREF

4 75V s VCC e VREF s 5 25V

FIGURE 10 Ground Referenced Conversion System Using Trimmed Supply

QOUT e

VIN VREF

4 75V s VCC e VREF s 5 25V

TL H 5672 8

FIGURE 11 Ground Referenced Conversion System with Reference Generating VCC Supply

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Applications Information

(Continued)

FIGURE 12 Typical Reference and Supply Circuit

RA e RB Ratiometric transducers
TL H 5672 9

FIGURE 13 Symmetrically Centered Reference 3 0 CONVERTER EQUATIONS The transition between adjacent codes N and N a 1 is given by
VIN e (VREF( a ) b VREF(b)) N 1 a g VTUE 256 512

a VREF(b)

(2)

The center of an output code N is given by

VIN (VREF( a ) b VREF(b)) N g VTUE 256

4 0 ANALOG COMPARATOR INPUTS The dynamic comparator input current is caused by the periodic switching of on-chip stray capacitances These are connected alternately to the output of the resistor ladder switch tree network and to the comparator input as part of the operation of the chopper stabilized comparator The average value of the comparator input current varies directly with clock frequency and with VIN as shown in Figure 6 If no filter capacitors are used at the analog inputs and the signal source impedances are low the comparator input current should not introduce converter errors as the transient created by the capacitance discharge will die out before the comparator output is strobed If input filter capacitors are desired for noise reduction and signal conditioning they will tend to average out the dynamic comparator input current It will then take on the characteristics of a DC bias current whose effect can be predicted conventionally

a VREF(b)

(3)

The output code N for an arbitrary input are the integers within the range
Ne VIN b VREF(b) c 256 g Absolute Accuracy VREF( a ) b VREF(b) (4)

where VIN e Voltage at comparator input VREF( a ) e Voltage at Ref( a ) VREF(b) e Voltage at Ref(b) VTUE e Total unadjusted error voltage (typically VREF( a ) d 512)

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10

Typical Application

TL H 5672 10

Address latches needed for 8085 and SC MP interfacing the ADC0808 to a microprocessor

MICROPROCESSOR INTERFACE TABLE PROCESSOR 8080 8085 Z-80 SC MP 6800 READ MEMR RD RD NRDS VMA  w2  R W WRITE MEMW WR WR NWDS VMA  w  R W INTERRUPT (COMMENT) INTR (Thru RST Circuit) INTR (Thru RST Circuit) INT (Thru RST Circuit Mode 0) SA (Thru Sense A) IRQA or IRQB (Thru PIA)

Ordering Information

TEMPERATURE RANGE Error

g

b 40 C to a 85 C

b 55 C to a 125 C

LSB Unadjusted

ADC0808CCN ADC0809CCN N28A Molded DIP

ADC0808CCV ADC0809CCV V28A Molded Chip Carrier

ADC0808CCJ

ADC0808CJ

g 1 LSB Unadjusted

Package Outline

J28A Ceramic DIP

J28A Ceramic DIP

11

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12

Physical Dimensions inches (millimeters)

Ceramic Dual-In-Line Package (J) Order Number ADC0808CCJ or ADC0808CJ NS Package Number J28A

Molded Dual-In-Line Package (N) Order Number ADC0808CCN or ADC0809CCN NS Package Number N28B

13

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ADC0808 ADC0809 8-Bit mP Compatible A D Converters with 8-Channel Multiplexer

Physical Dimensions inches (millimeters) (Continued)

Molded Chip Carrier (V) Order Number ADC0808CCV or ADC0809CCV NS Package Number V28A

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