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Script For Cadence RTL Compiler Synthesis

This script sets up the Cadence RTL Compiler synthesis environment by defining search paths, libraries, and other parameters. It then reads in Verilog files, elaborates the design, applies timing constraints, synthesizes to a target library, and writes out reports and output files with a specified name format.

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Murali
Copyright
© Attribution Non-Commercial (BY-NC)
Available Formats
Download as DOC, PDF, TXT or read online on Scribd
949 views

Script For Cadence RTL Compiler Synthesis

This script sets up the Cadence RTL Compiler synthesis environment by defining search paths, libraries, and other parameters. It then reads in Verilog files, elaborates the design, applies timing constraints, synthesizes to a target library, and writes out reports and output files with a specified name format.

Uploaded by

Murali
Copyright
© Attribution Non-Commercial (BY-NC)
Available Formats
Download as DOC, PDF, TXT or read online on Scribd
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###################################################### # Script for Cadence RTL Compiler synthesis # Erik Brunvand, 2008 # Use with syn-rtl -f <rtl-script> ######################################################

# Set the search paths to the libraries and the HDL files # Remember that "." means your current directory set_attribute hdl_search_path {./} ;# Search path for Verilog files set_attribute lib_search_path {./} ;# Search path for library files set_attribute library [list UofU_Digital_v1_2.lib] ;# Target Library set_attribute information_level 6 ;# See a lot of warnings. set set set set set set set myFiles [list moore.v] basename moore myClk clk myPeriod_ps 10000 myInDelay_ps 250 myOutDelay_ps 250 runname RTL ;# ;# ;# ;# ;# ;# ;# All your HDL files name of top level module clock name Clock period in ps delay from clock to inputs valid delay from clock to output valid name appended to output files

#********************************************************* #* below here shouldn't need to be changed... * #********************************************************* # Analyze and Elaborate the HDL files read_hdl ${myFiles} elaborate ${basename} # Apply Constraints and generate clocks set clock [define_clock -period ${myPeriod_ps} -name ${myClk} [clock_ports]] external_delay -input $myInDelay_ps -clock ${myClk} [find / -port ports_in/*] external_delay -output $myOutDelay_ps -clock ${myClk} [find / -port ports_out/*] # Sets transition to default values for Synopsys SDC format, # fall/rise 400ps dc::set_clock_transition .4 $myClk # check that the design is OK so far check_design -unresolved report timing -lint # Synthesize the design to the target library synthesize -to_mapped # Write out the report timing > report gates > report power > reports ${basename}_${runname}_timing.rep ${basename}_${runname}_cell.rep ${basename}_${runname}_power.rep

# Write out the structural Verilog and sdc files write_hdl -mapped > ${basename}_${runname}.v write_sdc > ${basename}_${runname}.sdc quit

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