3-1

Chapter 3 Sequential Logic

3-2

Chapter 3 Sequential Logic

Chapter 3: Sequential Logic

Some Definitions
Combinational logic: a digital logic circuit in which logical decisions are made based only on combinations of the inputs (e.g., an adder). Sequential logic: a circuit in which decisions are made based on combinations of the current inputs as well as the past history of inputs (e.g., a memory unit). Finite state machine: a circuit which has an internal state, and whose outputs are functions of both current inputs and its internal state (e.g., a vending machine controller).

Dr. Tim McGuire Sam Houston State University

Based on notes by Miles Murdocca

3-3

Chapter 3 Sequential Logic

3-4

Chapter 3 Sequential Logic

The Combinational Logic Unit

Translates a set of inputs into a set of outputs according to one or more mapping functions. Inputs and outputs for a CLU normally have two distinct (binary) values: high and low, 1 and 0, 0 and 1, or 5 v and 0 v, for example. The outputs of a CLU are strictly functions of the inputs, and the outputs are updated immediately after the inputs change. A set of inputs i0i n are presented to the CLU, which produces a set of outputs according to mapping functions f0fm. i0 f0

Sequential Logic
The combinational logic circuits we have been studying so far have no memory. The outputs always follow the inputs. There is a need for circuits with a memory, which behave differently depending upon their previous state. An example is the vending machine, which must remember how many and what kinds of coins have been inserted, and which behave according to not only the current coin inserted, but also upon how many and what kind of coins have been deposited previously. These are referred to as finite state machines, because they can have at most a finite number of states.

in

...

...

i1

Combinational logic unit

f1 fm

3-5

Chapter 3 Sequential Logic

3-6

Chapter 3 Sequential Logic

Classical Model of a Finite State Machine

... ...
io Inputs ik fo Outputs fm Combinational logic unit

A NOR Gate with a Lumped Delay

A
1 0 1 0 1

...

...

A B
State bits

??

A+B

A+B

Q0 D0 s0

?? Timing behavior

Qn Dn sn Synchronization signal Delay elements (one per state bit)

...

This delay between input and output is at the basis of the functioning of an important memory element, the flip-flop.

Page 1

3-7

Chapter 3 Sequential Logic

3-8

Chapter 3 Sequential Logic

An R-S Flip-Flop
Qt 0 S Q 0 0 0 1 R Q 1 1 1 St 0 0 1 1 0 0 1 1 Rt 0 1 0 1 0 1 0 1 Q i+1 0 0 1 (disallowed) 1 0 1 (disallowed) Q ?? 2? ? ?? 2? ? Q S R

A Clock Waveform
Amplitude

Time Cycle time = 25 ns

In a positive logic system, the action happens when the clock is high, or positive. The low part of the clock cycle allows propagation between subcircuits, so their inputs are stable at the correct value when the clock next goes high.

Timing behavior

The R-S flip-flop is an active-high (positive logic) device.

3-9

Chapter 3 Sequential Logic

3-10

Chapter 3 Sequential Logic

A Clocked R-S Flip-Flop

S R S Q CLK Q Q R Q 2? ? 3? ? Timing behavior CLK D CLK

A Clocked D (Data) Flip-Flop

Circuit D Q CLK

Q Q

D Symbol C

Q 2? ? Q

?? 2? ?

??

Timing behavior

The clock signal, CLK, turns on the inputs to the flip-flop.

The clocked D flip-flop, sometimes called a latch, has a potential problem: If D changes while the clock is high, the output will also change. The MasterSlave flip-flop solves this problem.

3-11

Chapter 3 Sequential Logic

3-12

Chapter 3 Sequential Logic

A Master-Slave Flip-Flop
Circuit Master D D QM Slave D QS D CLK QM QS D Symbol Q 3? ? 2? ? Q QS ?? 2? ? 2? ? ??

The Basic J-K Flip-Flop

J CLK K Q Q Q J Q

CLK

C QS

K Circuit

Symbol

Timing behavior

The rising edge of the clock clocks new data into the master, while the slave holds previous data. The falling edge clocks the new master data into the slave.

The J-L flip-flop eliminates the S = R = 1 problem of the S-R flip-flop, because Q enables J while Q' disables K, and vice versa. However there is still a problem. If J goes momentarily to 1 and then back to 0 while the flip-flop is active and in the reset, the flip-flop will catch the 1. This is referred to as 1 s catching. The J-K master-slave flip-flop solves this problem.

Page 2

3-13

Chapter 3 Sequential Logic

3-14

Chapter 3 Sequential Logic

A Master-Slave J-K Flip-Flop

1
J CLK K K Q Q Q J Q

A T Flip-Flop
J Q T K Q Q Symbol Q

Circuit

Symbol

Circuit

The presence of a constant 1 at J and K means that the flipflop will change its state from 0-1 or 1-0 each time it is clocked by the T (toggle) input.

3-15

Chapter 3 Sequential Logic

3-16

Chapter 3 Sequential Logic

Negative Edge-Triggered D Flip-Flop

Stores D

Finite State Machine Design

Counter has a clock input, CLK, and a RESET input. Has two output lines, which must take values of 00, 01, 10, and 11 on subsequent clock cycles.
Q

Amplitude

A Modulo-4 Counter
Time (t) 4 3 2 1 0 4 3 2 1 0 Time (t) RESET q0 q1 01100 01010 D D s1 CLK Q Q s0 Q Q 00001

CLK

Time
S

Q Main latch

Cycle time = 25 ns
D Stores D

3-bit synchronous s 0 counter

When the clock is high, the two input latches output 0, so the main latch remains in its previous state regardless of changes in D. When the clock goes high-low, values in the two input latches will affect the state of the main latch. While the clock is low, D cannot affect the main latch.

It requires two flip-flops to store the state.

s1

3-17

Chapter 3 Sequential Logic

3-18

Chapter 3 Sequential Logic

State Transition Diagram for a Modulo(4) Counter

Output 00 state 0/01 RESET 1/00 q 1 q 0 10/1 01/1 A 1/00 B Output 01 state

Truth Table
r(t) 0 0 0 0 1 1 1 1 s 1 (t)s 0 (t) 00 01 10 11 00 01 10 11 s 1 s 0 (t+1) 01 10 11 00 00 00 00 00 q1 q 0 (t+1) 01 10 11 00 00 00 00 00

Present State State Table A B C D Present State

Next State RESET 0 1 B/01 A/00 C/10 A/00 D/11 A/00 A/00 A/00 RESET 0 1 01 00 10 00 11 00 00 00

1/00 0/10 0/00 1/00

C 0/11

Output 10 state

Output 11 state

State Table With States Assigned

A:00 B:01 C:10 D:11

The state diagram and state table tell all there is to know about the FSM, and are the basis for a provably correct design.

Develop equations from this truth table for s0(t+1), s1(t+1), q0(t+1), and q1(t+1) from inputs r(t), s0(t) and s1(t)

Page 3

3-19

Chapter 3 Sequential Logic

3-20

Chapter 3 Sequential Logic

Equations
RESET

Logic Design for a Modulo(4) Counter

s 0(t ? 1) ? r (t )s1(t )s 0 (t ) ? r (t )s1( t )s 0(t ) s1(t ? 1) ? r (t )s1(t )s 0(t ) ? r( t )s1(t ) s0 (t ) q 0(t ? 1) ? r (t )s1(t )s 0 (t ) ? r (t )s1( t )s 0(t ) q1(t ? 1) ? r (t )s1(t )s 0(t ) ? r( t )s1(t ) s0 (t )
CLK

D s1

Q q1 Q

D s0

Q q0 Q

Implement these equations There are many simpler techniques for implementing counters.

3-21

Chapter 3 Sequential Logic

3-22

Chapter 3 Sequential Logic

Example: A Sequence Detector

State Transition Diagram for Sequence Detector Design a

machine that outputs a 1 when exactly 2 of the last 3 inputs are 1.
B 0/0 1/0 A 0/0 1/0 C 0/1 G 1/0 1/1 E 0/0 0/0 0/0 D 1/0 0/0

Design a machine that outputs a 1 when exactly 2 of the last 3 inputs are 1. e.g. input sequence of 011011100 produces an output sequence of 001111010 Assume input is a 1-bit serial line. Use D flip-flops and 8-1 multiplexers. Begin by constructing a state transition diagram.

Pres. State
S 2S 1S 0 A=000 B=001 C=010 D=011 E=100 F=101 G=110

X
0 S 2 S 1S 0Z 001/0 011/0 101/0 011/0 101/0 011/0 101/1 1 S 2 S 1S 0Z 010/0 100/0 110/0 100/0 110/1 100/1 110/0

1/1

1/0

Discuss: the meaning of each state.

Convert table to truth table (how?). Solve for s2 s1 s0 and Z.

3-23

Chapter 3 Sequential Logic

3-24

Chapter 3 Sequential Logic

Logic Diagram for Sequence Detector

0 x 1 x 1 x 1 0 000 001 010 011 100 101 110 111 D s2 Q Q x x x x x x x 0 000 001 010 011 100 101 110 111 D s1 Q Q x x x x x x x 0 000 001 010 011 100 101 110 111 D s0 Q Q 0 0 0 0 x x x 0 000 001 010 011 100 101 110 111 Z

Example: A Vending Machine Controller

Acepts nickel, dime, and quarter. When value of money inserted equals or exceeds twenty cents, machine vends item and returns change if any, and waits for next transaction. Implement with PLA and D flip-flops.

CLK

Page 4

3-25

Chapter 3 Sequential Logic

3-26

Chapter 3 Sequential Logic

State Transition Diagram for Vending Machine Controller

1/0 = Dispense/Do not dispense merchandise A dime is inserted Q/110 N/100 N/000 A 0 Q/101 B 5 D/000 Q/111 D/000 Q/111 D/100 C 10 N = Nickel D = Dime Q = Quarter N/000 N/000 D 15 1/0 = Return/Do not return a nickel in change 1/0 = Return/Do not return a dime in change D/110

Truth Table for Vending Machine Controller

Present state Coin Base 10 equivalent Next state Dispense Return nickel Return dime

s1 s0 x1 x0

s1 s0 z2 z1 z 0

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15

0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1

0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1

0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1

0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1

0 1 0 d 1 1 0 d 1 0 0 d 0 0 0 d

1 0 0 d 0 1 0 d 1 0 0 d 0 0 1 d

0 0 1 d 0 0 1 d 0 1 1 d 1 1 1 d

0 0 1 d 0 0 0 d 0 0 1 d 0 1 1 d

0 0 0 d 0 0 1 d 0 0 1 d 0 0 1 d

3-27

Chapter 3 Sequential Logic

3-28

Chapter 3 Sequential Logic

(a)FSM Circuit, (b)Truth Table, and (c)PLA Realization for Vending Machine Controller
x1 x0 5x5 PLA Q D s0 CLK Q D s1 z2 z z1 0 s1 s0 x1 x0 0 1 2 4
Dispense Return nickel Next Return dime state

Mealy versus Moore Machines

Mealy model: Outputs are functions of inputs and present state. Previous FSM designs were Mealy machines, because next state was computed from present state and inputs.
x1 x0
z2

Moore model: Outputs are functions of present state only.

0 1 x 00 01 4-to-1 10 MUX 11 D Q s0 Q z0

(a)

5 6 8 9 10 12 13 14

Present state Coin Base 10 equivalent

s1 s0 x1 x0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1

s1 s0 z2 z1 z0 0 1 0 d 1 1 0 d 1 0 0 d 0 0 0 d 1 0 0 d 0 1 0 d 1 0 0 d 0 0 1 d 0 0 1 d 0 0 1 d 0 1 1 d 1 1 1 d 0 0 1 d 0 0 0 d 0 0 1 d 0 1 1 d 0 0 0 d 0 0 1 d 0 0 1 d 0 0 1 d

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15

5x5 PLA Q D s0

z1 z0

00 01 4-to-1 10 MUX 11

D Q s1 Q

z1

CLK
(c) s1 s0 z2 z1 z0

(b)

Q D s1

CLK

Both are equally powerful.

3-29

Chapter 3 Sequential Logic

3-30

Chapter 3 Sequential Logic

Tri-State Buffers
C A 0 0 1 1 0 1 0 1 F C A 0 0 1 1 0 1 0 1 F 0 1

A 4-Bit Register
D3 D2 D Write (WR) CLK Enable (EN) Q D Q D1 D Q D0 D Q

? ?
0 1

? ?

Gate-Level View

Q3

Q2

Q1

Q0

A C

F=AC or F=? Tri-state buffer

A C

F=AC or F=?

Abstract Representation of a 4-Bit Register

WR Chip-Level View D3 D2 D1 D0 Q 3 Q2 Q1 Q 0

Tri-state buffer, inverted control

There is a third state: high impedance. This means the gate output is essentially disconnected from the circuit. This state is indicated by ? in the figure.

EN

Page 5

3-31

Chapter 3 Sequential Logic

3-32

Chapter 3 Sequential Logic

Internal Layout and Block Diagram for Left-Right Shift with Parallel Read/Write Capabilities
c1 c0 D3 Left shift out Left shift in D2 D1 D0 Right shift in

A Modulo(8) Ripple Counter

Note the use of CLK the T flip-flops. Enable (EN) They are used to RESET toggle the input of the next flipflop when its output is 1.
1 J Q K 1 J Q K 1 J Q K

Q2

Q1

Q0

c0 c1 CLK Enable (EN)

D Q

Right shift out

CLK Enable MOD(8) COUNTER

Q3 Q2 Q1 Q0

Q0 Q1 Q2 Timing behavior

RESET
Cont rol c1 0 0 1 1 c0 0 1 0 1 No c hange Shift left Shift right Parallel load Function Left shift in Left shift out c0 c1 D3 D2 D1 D0 Q3 Q2 Q 1 Q 0

Q2 Q1 Q0

Right shift out Right shift in

3-33

Chapter 3 Sequential Logic

3-34

Chapter 3 Sequential Logic

Converting a NOR S-R to an NAND S-R

S Q S Q S Q R Q

A Circuit with a Hazard

A B

AB

C B A AB

S Q

S ?? R

Glitch c aused by a hazard

Active-high NOR Implementation

Push bubbles (DeMorgan s)

Rearrange bubbles

Convert from bubbles to active-low signal names

Q Q

It is desirable to be able to turn off the flip-flop so it does not respond to such hazards.

?? 2? ? Timing behavior

Page 6