Chp1 - Latches and Flip-Flops

CHAPTER 1
LATCHES & FLIP-FLOPS
Outcome
After learning this chapter, student should be able to; Recognize the difference between latches and flipflops Analyze the operation of the flip flop Draw the output timing diagram (waveform) for single and combination of latches and flip-flops Troubleshoot basic flip-flops circuits
Terminology
Multivibrator A class of digital circuits in which the output is connected back to the input (i.e. it is fed back to the input, commonly referred to as feedback) to produce either two stable states, one stable state, or no stable states, depending on the configuration. Bistable Having two stable states. Latches and flip-flops are bistable multivibrators Latch An asynchronous bistable multivibrator, used for storing 1 bit Flip-Flop A synchronous bistable multivibrator, used for storing 1 bit
Teminology (continue..)
Asynchronous
There is no fixed timing relationship
Synchronous
There is a fixed timing relationship, usually through the use of a clock pulse
Edge-triggered Flip-Flop
A type of flip-flop in which the input data are entered and appear on the output on the same clock edge, either the positive or negative edge
Introduction: Comparison between combinational circuits and sequential circuits

Characteristics of combinational circuits are; Output depends only to current input No feedback from output of the system Unable to remember past values Logic gates AND, OR, XOR, NOT
Introduction (continue..)
Fundamental of sequential circuits Characteristics of sequential circuits are; Output depends not only on current input but also on past input values Output from the system is feedback as new input Capable of storing binary information : memory Latches, flip-flops and logic gates
Generic block diagram of sequential circuit
Introduction (continue..)
Multivibrator any digital circuit employing feedback. Sequential/Multivibrator devices are categorized as; Bistable Two stable states, SET and RESET Latches and flip-flops Monostable Has one stable state Timer Astable No stable state Oscillator (to generate periodic pulse waveforms for timing purposes. )
Fig: inverter with feedback
7
Latches
Latches are bistable multivibrator A two stable states digital circuit that produces HIGH or LOW depending on the input For gated (enabled) latches, the output are controlled by the enable (EN) input It is level triggered, means that any input changes during the EN is active, the output will be affected The operation will be observed by examining the timing diagram
Latches (continue..)
Four types; S-R latch S-R latch
Gated S-R latch
Gated D latch
S-R (Set-Reset) Latch

Logic circuit Symbol
Truth table
10
S-R Latch Timing Diagram
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S-R (Set-Reset) Latch

Truth table
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S-R Latch Timing Diagram
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Gated S-R Latch

Truth table
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Gated S-R Latch Timing Diagram
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Gated D latch
Truth table
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Gated D Latch Timing Diagram
17
How does S-R latch works?

By using DeMorgans Theorem
NAND gate
Negative-OR gate
The equivalent logic circuit
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How does S-R latch works? (continue..)

Assume that S = 0 and R = 1, therefore Q = 1 and Q = 0
Change both S and R to 1, therefore both Q and Q are still the same as previous value
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Now, change S = 1 and R = 0, therefore Q = 0 and Q = 1
Change both S and R to 1, therefore both Q and Q are still the same as previous value
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Now, set both input to 0, hence, both Q and Q are 1 which is invalid
This state should be avoided since the changing state from invalid is unpredictable. Prove it!!!
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Gated D Latch Exercises
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Latch applications
SR and D latches are among the simplest and least expensive types of memory elements used in logic circuits.
Fig: Typical use of latches in a computers input/output circuits

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Edge-Triggered Flip-Flops
Flip-flops are synchronous bistable multivibrator. Synchronous means the output changes state only occur at a triggering point called clock Edge-triggered can be either positive (rising) edge or negative (falling) edge of the clock Edge triggered flip-flops change state either at positive or negative clock Clock input for flip-flops
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Edge-Triggered Flip-Flops (continue..)

Four types; S-R flip flops
Positive-edge triggered Negative-edge triggered
D flip-flops
J-K flip-flops
T flip-flops
25
Edge-Triggered S-R Flip-Flop

Positive-edge S-R FF
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Edge-Triggered S-R Flip-Flop Exercises
27
Edge-Triggered D Flip-Flop
Positive-edge D FF
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Edge-Triggered D Flip-Flop Exercises
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Edge-Triggered J-K Flip-Flop

Positive-edge J-K FF
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Edge-Triggered J-K Flip-Flop Exercises
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Edge-Triggered T Flip-Flop
Positive-edge T FF
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Edge-Triggered T Flip-Flop Exercises
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Latch and Flip-Flop Exercise

Draw the output waveform for the JK flip flop and D latch whose input are as given
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Master Slave Flip-Flops

Introduced to overcome timing problem that might be occurred to flip-flop
Two similar flip-flops are connected with different clock

The output is stable even though input changes
Qo
Q1
35
Asynchronous Preset and Clear

Most integrated circuit FF have asynchronous inputs These input change the FF output without clock triggering
/PRE 0
Normally label as preset (PRE) and clear (CLR)

For example, take the T FF
/CLR 0 OUTPUT Invalid
0
1 1
1
0 1
Q = 1 (Set)
Q = 0 (Reset) Flip-flop normal operation
36
Flip-Flop Operating Characteristics

Propagation Delay Times Required time interval for output signal to occur after an input signal has been applied
CLK Q tPHL
50%
CLK Q tPLH
Set-up Time Minimum time interval for the signal to retain the value before clock pulse is triggered
D CLK ts 37
Flip-Flop Operating Characteristics

Hold time Minimum time interval for the signal to retain the value after clock pulse is triggered
CLK D th
Maximum Clock Frequency Highest rate at which a flip-flop can respond to the input signal
fmax
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Flip-Flop Operating Characteristics (continue..)

Pulse Width Minimum clock pulse width is smallest time between HIGH and LOW Power Dissipation Total power consumption of the flip-flops For example, a 7474 chip has two D flip-flops which each of the flip-flop operates at +5Vdc and draws 5mA P = Vcc x Icc = 5 x 5 = 25mW PT = 2 x 25 mW = 50mW I = 50mW/5V = 10mA
Therefore, the chip must be supplied by +5Vdc supply with at least 10mA of current.
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Flip-Flop Applications
Parallel data storage
You will learn more in Chapter 3
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Flip-Flop Applications (continue..)

Frequency division
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Flip-Flop Applications (continue..)

Counting You will learn more in Chapter 2
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Exercises
(a) What is the difference between latch and flip-flop operation? (b) List 3 applications of flip-flops. Explain briefly each of the application of the flipflops. (c) Give the definition and describe the propagation delay time in flip-flop operating characteristics.
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Exercises (Continue)
(d) For negative edge triggered J-K flip-flop with preset (/PRE) and (/CLR) inputs, determine the Q output for the input shown in the timing diagram in Figure Q1(d). Assume Q starts with 1 and the input J and K always 1.
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CHAPTER 1

LATCHES & FLIP-FLOPS

Introduction: Comparison between combinational circuits and sequential circuits

Generic block diagram of sequential circuit

Gated S-R latch

S-R (Set-Reset) Latch

S-R Latch Timing Diagram

S-R (Set-Reset) Latch

S-R Latch Timing Diagram

Gated S-R Latch

Gated S-R Latch Timing Diagram

Gated D Latch Timing Diagram

How does S-R latch works?

The equivalent logic circuit

How does S-R latch works? (continue..)

How does S-R latch works? (continue..)

How does S-R latch works? (continue..)

Gated D Latch Exercises

Fig: Typical use of latches in a computers input/output circuits

Edge-Triggered Flip-Flops (continue..)

Edge-Triggered S-R Flip-Flop

Edge-Triggered S-R Flip-Flop Exercises

Edge-Triggered D Flip-Flop Exercises

Edge-Triggered J-K Flip-Flop

Edge-Triggered J-K Flip-Flop Exercises

Edge-Triggered T Flip-Flop Exercises

Latch and Flip-Flop Exercise

Master Slave Flip-Flops

Two similar flip-flops are connected with different clock

Asynchronous Preset and Clear

Normally label as preset (PRE) and clear (CLR)

Flip-Flop Operating Characteristics

Flip-Flop Operating Characteristics

Flip-Flop Operating Characteristics (continue..)

Parallel data storage

You will learn more in Chapter 3

Flip-Flop Applications (continue..)

Flip-Flop Applications (continue..)

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