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“Machine Language Instruction Formats”.

1. Operation code field is present in :

a) programming language instruction
b) assembly language instruction
c) machine language instruction
d) none of the mentioned
View Answer

Answer: c
Explanation: Machine language instruction format has one or more fields. The first one is the
operation code field.

2. A machine language instruction format consists of

a) Operand field
b) Operation code field
c) Operation code field & operand field
d) none of the mentioned
View Answer

Answer: c
Explanation: Machine language instruction format has both the fields.

3. The length of the one-byte instruction is

a) 2 bytes
b) 1 byte
c) 3 bytes
d) 4 bytes
View Answer

Answer: b
Explanation: This format is only one byte long.

4. The instruction format ‘register to register’ has a length of

a) 2 bytes
b) 1 byte
c) 3 bytes
d) 4 bytes
View Answer

Answer: a
Explanation: This format is 2 bytes long.
5. The R/M field in a machine instruction format specifies
a) another register
b) another memory location
c) other operands
d) all of the mentioned
View Answer

Answer: d
Explanation: The LSBs(least significant bits) from 0 to 3 represent R/M field that specifies
another register or memory location i.e. the other operand.

6. In a machine instruction format, S-bit is the

a) status bit
b) sign bit
c) sign extension bit
d) none of the mentioned
View Answer

Answer: c
Explanation: The S-bit known as sign extension bit is used along with W-bit to show the type
of operation.

7. The bit which is used by the ‘REP’ instruction is

a) W-bit
b) S-bit
c) V-bit
d) Z-bit
View Answer

Answer: d
Explanation: The Z-bit is used by the REP instruction to control the loop.

8. If a W-bit value is ‘1’ then the operand is of

a) 8 bits
b) 4 bits
c) 16 bits
d) 2 bits
View Answer

Answer: c
Explanation: If W-bit is ‘1’ then the operand is of 16-bits, and if it is ‘0’ then the operand is
of 8-bits.

9. The instructions which after execution transfer control to the next instruction in the
sequence are called
a) Sequential control flow instructions
b) control transfer instructions
c) Sequential control flow & control transfer instructions
d) none of the mentioned
View Answer
Answer: a
Explanation: The sequential control flow instructions follow sequence order in their
execution.

10. The instructions that transfer the control to some predefined address or the address
specified in the instruction are called as
a) sequential control flow instructions
b) control transfer instructions
c) sequential control flow & control transfer instructions
d) none of the mentioned
View Answer

Answer: b
Explanation: The control transfer instructions transfer control to the specified address.

11. The instruction “JUMP” belongs to

a) sequential control flow instructions
b) control transfer instructions
c) branch instructions
d) control transfer & branch instructions
View Answer

Answer: d
Explanation: The JUMP instruction transfers the control to the address located in the
instruction.

This set of Microprocessor Multiple Choice Questions & Answers (MCQs) focuses on
“Addressing Modes of 8086”.

1. The instruction, MOV AX, 0005H belongs to the address mode

a) register
b) direct
c) immediate
d) register relative
View Answer

Answer: c
Explanation: In Immediate addressing mode, immediate data is a part of instruction and
appears in the form of successive byte or bytes.

2. The instruction, MOV AX, 1234H is an example of

a) register addressing mode
b) direct addressing mode
c) immediate addressing mode
d) based indexed addressing mode
View Answer

Answer: c
Explanation: Since immediate data is present in the instruction.

3. The instruction, MOV AX, [2500H] is an example of

a) immediate addressing mode
b) direct addressing mode
c) indirect addressing mode
d) register addressing mode
View Answer

Answer: b
Explanation: Since the address is directly specified in the instruction as a part of it.

4. If the data is present in a register and it is referred using the particular register, then it is
a) direct addressing mode
b) register addressing mode
c) indexed addressing mode
d) immediate addressing mode
View Answer

Answer: b
Explanation: Since register is used to refer the address.

5. The instruction, MOV AX,[BX] is an example of

a) direct addressing mode
b) register addressing mode
c) register relative addressing mode
d) register indirect addressing mode
View Answer

Answer: d
Explanation: Since the register used to refer to the address is accessed indirectly.

6. If the offset of the operand is stored in one of the index registers, then it is
a) based indexed addressing mode
b) relative based indexed addressing mode
c) indexed addressing mode
d) none of the mentioned
View Answer

Answer: c
Explanation: In the indexed addressing mode, the offset of an operand is stored and in the rest
of them, address is stored.

7. The addressing mode that is used in unconditional branch instructions is

a) intrasegment direct addressing mode
b) intrasegment indirect addressing mode
c) intrasegment direct and indirect addressing mode
d) intersegment direct addressing mode
View Answer

Answer: b
Explanation: In intrasegment indirect mode, the branch address is found as the content of a
register or a memory location.

8. If the location to which the control is to be transferred lies in a different segment other than
the current one, then the mode is called
a) intrasegment mode
b) intersegment direct mode
c) intersegment indirect mode
d) intersegment direct and indirect mode
View Answer

Answer: d
Explanation: In intersegment mode, the control to be transferred lies in a different segment.

9. The instruction, JMP 5000H:2000H;

is an example of
a) intrasegment direct mode
b) intrasegment indirect mode
c) intersegment direct mode
d) intersegment indirect mode
View Answer

Answer: c
Explanation: Since in intersegment direct mode, the address to which the control is to be
transferred is in a different segment.

10. The contents of a base register are added to the contents of index register in
a) indexed addressing mode
b) based indexed addressing mode
c) relative based indexed addressing mode
d) based indexed and relative based indexed addressing mode
View Answer

Answer: d
Explanation: The effective address is formed by adding the contents of both base and index
registers to a default segment.

This set of Microprocessor Multiple Choice Questions & Answers (MCQs) focuses on
“Instruction Set of 8086/8088 – 1”.

1. The instruction that is used to transfer the data from source operand to destination operand
is
a) data copy/transfer instruction
b) branch instruction
c) arithmetic/logical instruction
d) string instruction
View Answer

Answer: a
Explanation: These instructions are used to copy and transfer the instructions.

2. Which of the following is not a data copy/transfer instruction?

a) MOV
b) PUSH
c) DAS
d) POP
View Answer

Answer: c
Explanation: DAS (Decimal Adjust after Subtraction) is an arithmetic instruction.

3. The instructions that involve various string manipulation operations are

a) branch instructions
b) flag manipulation instructions
c) shift and rotate instructions
d) string instructions
View Answer

Answer: d
Explanation: The string instructions perform operations on strings such as load, move, scan,
compare etc.

4. Which of the following instruction is not valid?

a) MOV AX, BX
b) MOV DS, 5000H
c) MOV AX, 5000H
d) PUSH AX
View Answer

Answer: b
Explanation: Both the source and destination operands cannot be memory locations except
for string instructions.

5. In PUSH instruction, after each execution of the instruction, the stack pointer is
a) incremented by 1
b) decremented by 1
c) incremented by 2
d) decremented by 2
View Answer

Answer: d
Explanation: The actual current stack-top is always occupied by the previously pushed data.
So, the push operation decrements SP by 2 and then stores the two bytes contents of the
operand onto the stack.

6. The instruction that pushes the contents of the specified register/memory location on to the
stack is
a) PUSHF
b) POPF
c) PUSH
d) POP
View Answer

Answer: c
Explanation: Since PUSH operation transfers data to stack from a register or memory
location.

7. In POP instruction, after each execution of the instruction, the stack pointer is
a) incremented by 1
b) decremented by 1
c) incremented by 2
d) decremented by 2
View Answer

Answer: c
Explanation: The actual current stack top is poped into the specific operand as the contents of
stack top memory is stored in AL&SP and further contents of the memory location pointed to
by SP are copied to AH & SP.

8. The instructions that are used for reading an input port and writing an output port
respectively are
a) MOV, XCHG
b) MOV, IN
c) IN, MOV
d) IN, OUT
View Answer

Answer: d
Explanation: The address of the input/output port may be specified directly or indirectly.
Example for input port: IN AX, DX; This instruction reads data from a 16-bit port whose
address is in DX and stores it in AX
Example for output port: OUT 03H, AL; This sends data available in AL to a port whose
address is 03H.

9. The instruction that is used for finding out the codes in case of code conversion problems
is
a) XCHG
b) XLAT
c) XOR
d) JCXZ
View Answer
Answer: b
Explanation: The translate(XLAT) instruction is used to find codes.

10. The instruction that loads effective address formed by destination operand into the
specified source register is
a) LEA
b) LDS
c) LES
d) LAHF
View Answer

Answer: a
Explanation: The instruction, LEA loads effective address and is more useful for assembly
language rather than for machine language.

11. The instruction that loads the AH register with the lower byte of the flag register is
a) SAHF
b) AH
c) LAHF
d) PUSHF
View Answer

Answer: c
Explanation: The instruction LAHF(Load AH from a lower byte of Flag) may be used to
observe the status of all the condition code flags(except overflow flag) at a time.

12. The instruction that pushes the flag register on to the stack is
a) PUSH
b) POP
c) PUSHF
d) POPF
View Answer

Answer: c
Explanation: The instruction PUSHF(push flags to stack) pushes the flag register on to the
stack.
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13. The instruction that loads the flag register completely from the word contents of the
memory location is
a) PUSH
b) POP
c) PUSHF
d) POPF
View Answer

Answer: d
Explanation: POPF is pop flags to stack.
14. The instruction that adds immediate data/contents of the memory location specified in an
instruction/register to the contents of another register/memory location is
a) SUB
b) ADD
c) MUL
d) DIV
View Answer

Answer: b
Explanation: ADD instruction adds the data.

15. The instruction that supports addition when carry exists is

a) ADD
b) ADC
c) ADD & ADC
d) None of the mentioned
View Answer

Answer: b
Explanation: ADC(Add with Carry) instruction performs the same operation as ADD
operation, but adds the carry flag bit to the result.

This set of Microprocessors Interview Questions and Answers focuses on “Instruction Set of
8086/8088 – 2”.

1. The instruction, “INC” increases the contents of the specified register or memory location
by
a) 2
b) 0
c) 1
d) 3
View Answer

Answer: c
Explanation: This instruction adds 1 to the contents of the operand and so increments by 1.

2. The instruction that subtracts 1 from the contents of the specified register/memory location
is
a) INC
b) SUBB
c) SUB
d) DEC
View Answer

Answer: d
Explanation: The DEC instruction decrements the contents of a specified register/memory
location by 1.
3. The instruction that enables subtraction with borrow is
a) DEC
b) SUB
c) SBB
d) None of the mentioned
View Answer

Answer: c
Explanation: The SBB instruction subtracts the source operand and the borrow flag from the
destination operand.

4. The flag that acts as Borrow flag in the instruction, SBB is

a) direction flag
b) carry flag
c) parity flag
d) trap flag
View Answer

Answer: b
Explanation: If borrow exists in the subtraction operation performed then carry flag is set.

5. In general, the source operand of an instruction can be

a) memory location
b) register
c) immediate data
d) all of the mentioned
View Answer

Answer: d
Explanation: The source operand is the element which is data or data stored memory location
on which operation is performed.

6. In general, the destination operand of an instruction can be

a) memory location
b) register
c) immediate data
d) memory location and register
View Answer

Answer: d
Explanation: Since the destination should be able to store the data, immediate data cannot be
considered as a destination operand.

7. The instruction, CMP to compare source and destination operands it performs

a) addition
b) subtraction
c) division
d) multiplication
View Answer
Answer: b
Explanation: For comparison, the instruction CMP subtracts source operand from destination
operand.

8. During comparison operation, the result of comparing or subtraction is stored in

a) memory
b) registers
c) stack
d) no where
View Answer

Answer: d
Explanation: The result of subtraction operation is not stored anywhere during a comparison.

9. The instruction that converts the result in an unpacked decimal digits is

a) AAA
b) AAS
c) AAM
d) All of the mentioned
View Answer

Answer: d
Explanation: All the ASCII adjust instructions give result in unpacked decimal form and so
are called as “Unpacked BCD arithmetic instructions”.

10. Which of the following is a mnemonic?

a) ADD
b) ADC
c) AAA
d) ADD & ADC
View Answer

Answer: c
Explanation: AAA is a mnemonic. It doesn’t have either a source or destination operand.

11. The instruction in which adjustment is made before performing the operation is
a) AAA
b) AAS
c) AAM
d) AAD
View Answer

Answer: d
Explanation: The AAD instruction converts two unpacked BCD digits in AH and AL to the
equivalent binary number in AL. This adjustment must be made before dividing the two
unpacked BCD digits.

12. The expansion of DAA is

a) decimal adjust after addition
b) decimal adjust before addition
c) decimal adjust accumulator
d) decimal adjust auxiliary
View Answer

Answer: c
Explanation: This instruction performs conversion operation.
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13. The instruction that is used to convert the result of the addition of two packed BCD
numbers to a valid BCD number is
a) DAA
b) DAS
c) AAA
d) AAS
View Answer

Answer: a
Explanation: In this conversion, the result has to be only in AL.

14. The ROR instruction rotates the contents of the destination operand to
a) left
b) right
c) left and then right
d) right and then left
View Answer

Answer: b
Explanation: ROR stands for Rotate Right without carry. so, the instruction rotates right.

This set of Microprocessors Questions and Answers for Freshers focuses on “Instruction Set
of 8086/8088 – 3”.

1. The mnemonic that is placed before the arithmetic operation is performed is

a) AAA
b) AAS
c) AAM
d) AAD
View Answer

Answer: d
Explanation: The AAD instruction converts two unpacked BCD digits in AH and AL to the
equivalent binary number in AL.

2. The Carry flag is undefined after performing the operation

a) AAA
b) ADC
c) AAM
d) AAD
View Answer

Answer: d
Explanation: Since the operation, AAD is performed before division operation is performed,
the carry flag, auxiliary flag and overflow flag are undefined.

3. The instruction that performs logical AND operation and the result of the operation is not
available is
a) AAA
b) AND
c) TEST
d) XOR
View Answer

Answer: c
Explanation: In the TEST instruction, the logical AND operation is performed and the result
is not stored but flags are affected.

4. In the RCL instruction, the contents of the destination operand undergo function as
a) carry flag is pushed into LSB & MSB is pushed into the carry flag
b) carry flag is pushed into MSB & LSB is pushed into the carry flag
c) auxiliary flag is pushed into LSB & MSB is pushed into the carry flag
d) parity flag is pushed into MSB & LSB is pushed into the carry flag
View Answer

Answer: a
Explanation: In RCL(Rotate right through carry), for each operation, the carry flag is pushed
into LSB and the MSB of the operand is pushed into carry flag.

5. The instruction that is used as prefix to an instruction to execute it repeatedly until the CX
register becomes zero is
a) SCAS
b) REP
c) CMPS
d) STOS
View Answer

Answer: b
Explanation: The instruction to which the REP is prefix, is executed repeatedly until CX
register becomes zero. When CX becomes zero, the execution proceeds to the next
instruction in sequence.

6. Match the following

A) MOvSB/SW 1) loads AL/AX register by content of a string

B) CMPS 2) moves a string of bytes stored in source to
destination
C) SCAS 3) compares two strings of bytes or words whose length is
stored in CX register
D) LODS 4) scans a string of bytes or words
a) A-3,B-4,C-2,D-1
b) A-2,B-1,C-4,D-3
c) A-2,B-3,C-1,D-4
d) A-2,B-3,C-4,D-1
View Answer

Answer: d
Explanation: By using the string instructions, the operations on strings can be performed.

7. The instructions that are used to call a subroutine from the main program and return to the
main program after execution of called function are
a) CALL, JMP
b) JMP, IRET
c) CALL, RET
d) JMP, RET
View Answer

Answer: c
Explanation: At each CALL instruction, the IP and CS of the next instruction are pushed onto
the stack, before the control is transferred to the procedure. At the end of the procedure, the
RET instruction must be executed to retrieve the stored contents of IP & CS registers from a
stack.

8. The instruction that unconditionally transfers the control of execution to the specified
address is
a) CALL
b) JMP
c) RET
d) IRET
View Answer

Answer: b
Explanation: In this the control transfers to the address specified in the instruction and flags
are not affected by this instruction.
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9. Which instruction cannot force the 8086 processor out of ‘halt’ state?
a) Interrupt request
b) Reset
c) Both interrupt request and reset
d) Hold
View Answer

Answer: d
Explanation: Only an interrupt request or Reset will force the 8086 processor to come out of
the ‘halt’ state.

10. NOP instruction introduces

a) Address
b) Delay
c) Memory location
d) None of the mentioned
View Answer

Answer: b
Explanation: NOP is the No operation. It means that the processor performs no operation for
the clock cycle and thus there exists a delay.

11. Which of the following is not a machine controlled instruction?

a) HLT
b) CLC
c) LOCK
d) ESC
View Answer

Answer: b
Explanation: Since CLC is a flag manipulation instruction where CLC stands for Clear Carry
Flag.

This set of Microprocessor Multiple Choice Questions & Answers (MCQs) focuses on
“Assembler Directives and Operators”.

1. The assembler directives which are the hints using some predefined alphabetical strings are
given to
a) processor
b) memory
c) assembler
d) processor & assembler
View Answer

Answer: c
Explanation: These directives help the assembler to correctly understand the assembly
language programs to prepare the codes.

2. The directive used to inform the assembler, the names of the logical segments to be
assumed for different segments used in the program is
a) ASSUME
b) SEGMENT
c) SHORT
d) DB
View Answer

Answer: a
Explanation: In ALP, each segment is given a name by using the directive ASSUME
SYNTAX: ASSUME segment:segment_name
Eg: ASSUME CS:Code
here CS is the Code segment and code is the name assumed to the segment.
3. Match the following

a) DB 1) used to direct the assembler to reserve only 10-bytes

b) DT 2) used to direct the assembler to reserve only 4 words
c) DW 3) used to direct the assembler to reserve byte or bytes
d) DQ 4) used to direct the assembler to reserve words

a) a-3, b-2, c-4, d-1

b) a-2, b-3, c-1, d-4
c) a-3, b-1, c-2, d-4
d) a-3, b-1, c-4, d-2
View Answer

Answer: d
Explanation: These directives are used for allocating memory locations in the available
memory.

4. The directive that marks the end of an assembly language program is

a) ENDS
b) END
c) ENDS & END
d) None of the mentioned
View Answer

Answer: b
Explanation: The directive END is used to denote the completion of the program.

5. The directive that marks the end of a logical segment is

a) ENDS
b) END
c) ENDS & END
d) None of the mentioned
View Answer

Answer: a
Explanation: The directive ENDS is used to end a segment where as the directive END is
used to end the program.

6. The directive that updates the location counter to the next even address while executing a
series of instructions is
a) EVN
b) EVEN
c) EVNE
d) EQU
View Answer

Answer: b
Explanation: The directive updates location counter to next even address if the current
location counter contents are not even.
7. The directive that directs the assembler to start the memory allotment for a particular
segment/block/code from the declared address is
a) OFFSET
b) LABEL
c) ORG
d) GROUP
View Answer

Answer: c
Explanation: If an ORG is written then the assembler initiates the location counter to keep the
track of allotted address for the module as mentioned in the directive.
If the directive is not present, then the location counter is initialized to 0000H.

8. The directive that marks the starting of the logical segment is

a) SEG
b) SEGMENT
c) SEG & SEGMENT
d) PROC
View Answer

Answer: b
Explanation: The directive SEGMENT indicates the beginning of the segment.
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9. The recurrence of the numerical values or constants in a program code is reduced by

a) ASSUME
b) LOCAL
c) LABEL
d) EQU
View Answer

Answer: d
Explanation: In this, the recurring/repeating value is assigned with a label. The label is placed
instead of the numerical value in the entire program code.

10. The labels or constants that can be used by any module in the program is possible when
they are declared as
a) PUBLIC
b) LOCAL
c) GLOBAL
d) Either PUBLIC or GLOBAL
View Answer

Answer: c
Explanation: The labels, constants, variables, procedures declared as GLOBAL can be used
by any module in the program.
This set of Microprocessor Multiple Choice Questions & Answers (MCQs) focuses on
“Programming With An Assembler”.

1. The disadvantage of machine level programming is

a) time consuming
b) chances of error are more
c) debugging is difficult
d) all of the mentioned
View Answer

Answer: d
Explanation: The machine level programming is complicated.

2. The coded object modules of the program to be assembled are present in

a) .ASM file
b) .OBJ file
c) .EXE file
d) .OBJECT file
View Answer

Answer: b
Explanation: .OBJ file is created with same name as source file and extension .OBJ. It
contains the coded object modules of the program to be assembled.

3. The advantages of assembly level programming are

a) flexibility of programming is more
b) chances of error are less
c) debugging is easy
d) all of the mentioned
View Answer

Answer: d
Explanation: The assembly level programming is more advantageous than the machine level
programming.

4. The extension that is essential for every assembly level program is

a) .ASP
b) .ALP
c) .ASM
d) .PGM
View Answer

Answer: c
Explanation: All the files should have the extension, .ASM.

5. The directory that is under work must have the files that are related to
a) Norton’s editor
b) Assembler
c) Linker
d) All of the mentioned
View Answer

Answer: d
Explanation: Before starting the process of entering a small program on PC, ensure that all
the files namely Norton’s editor, assembler, linker and debugger are available in the same
directory in which work is been done.

6. The listing file is identified by

a) source file name
b) extension .LSF
c) source file name and an extension .LSF
d) source file name and an extension .LST
View Answer

Answer: d
Explanation: The listing file is automatically generated in the assembly process and is
identified by the entered or source file name and an extension .LST.

7. The extension file that is must for a file to be accepted by the LINK as a valid object file is
a) .OBJ file
b) .EXE file
c) .MASM file
d) DEBUG file
View Answer

Answer: a
Explanation: The .OBJ extension is a must for a file to be accepted by the LINK as a valid
object file.

8. The listing file contains

a) total offset map of a source file
b) offset address and labels
c) memory allotments for different labels
d) all of the mentioned
View Answer

Answer: d
Explanation: The listing file contains total offset map of source file including labels, offset
addresses, opcodes, memory allotments for different directives and labels and relocation
information.

9. DEBUG.COM facilitates the

a) debugging
b) trouble shooting
c) debugging and trouble shooting
d) debugging and assembling
View Answer
Answer: c
Explanation: DEBUG.COM is a DOS utility that facilitates the debugging and trouble
shooting.

10. DEBUG is able to troubleshoot only

a) .EXE files
b) .OBJ files
c) .EXE file and .OBJ file
d) .EXE flie and .LST file
View Answer

Answer: a
Explanation: The DEBUG may be used either to debug a source program or to observe the
results of execution of an .EXE file.

This set of Microprocessor Multiple Choice Questions & Answers (MCQs) focuses on
“Stack”.

1. The Stack follows the sequence

a) first-in-first-out
b) first-in-last-out
c) last-in-first-out
d) last-in-last-out
View Answer

Answer: c
Explanation: The stack follows last-in-first-out sequence.

2. If the processor is executing the main program that calls a subroutine, then after executing
the main program up to the CALL instruction, the control will be transferred to
a) address of main program
b) subroutine address
c) address of CALL instruction
d) none of the mentioned
View Answer

Answer: b
Explanation: Since subroutine is called, to start the execution of the subroutine, the control is
transferred to the subroutine address.

3. The stack is useful for

a) storing the register status of the processor
b) temporary storage of data
c) storing contents of registers temporarily inside the CPU
d) all of the mentioned
View Answer
Answer: d
Explanation: Stack is used for temporary storage of contents of registers and memory
locations, status of registers.

4. The Stack is accessed using

a) SP register
b) SS register
c) SP and SS register
d) None of the mentioned
View Answer

Answer: c
Explanation: The stack is accessed using a pointer that is implemented using SP and SS
registers.

5. As the storing of data words onto the stack is increased, the stack pointer is
a) incremented by 1
b) decremented by 1
c) incremented by 2
d) decremented by 2
View Answer

Answer: d
Explanation: The data is stored from top address of the stack and is decremented by 2.

6. While retrieving data from the stack, the stack pointer is

a) incremented by 1
b) incremented by 2
c) decremented by 1
d) decremented by 2
View Answer

Answer: b
Explanation: The data in the stack, may again be transferred back from a stack to register. At
that time, the stack pointer is incremented by 2.

7. The process of storing the data in the stack is called ……… the stack.
a) pulling into
b) pulling out
c) pushing into
d) popping into
View Answer

Answer: c
Explanation: The data is pushed into the stack while loading the stack.

8. The reverse process of transferring the data back from the stack to the CPU register is
known as
a) pulling out the stack
b) pushing out the stack
c) popping out the stack
d) popping off the stack
View Answer

Answer: d
Explanation: The data retrieved from stack is called popping off.

9. The books arranged one on the other on a table is an example of

a) queue
b) queue and first-in-first out
c) stack
d) stack and last-in-first-out
View Answer

Answer: d
Explanation: If the books are arranged one on the other, then the book that is placed last will
be the first out.

10. The PID temperature controller using 8086 has

a) data flow
b) data flow and uses queue
c) sequential flow
d) sequential flow and uses stack
View Answer

Answer: d
Explanation: Since PID temperature controller has steps that need to be sequentially executed
such as sampling the output, conversion of a signal with ADC, finding errors, deriving
control signals and applying the control signal to control flow of energy.

This set of Microprocessor Multiple Choice Questions & Answers (MCQs) focuses on “Stack
Structure of 8086/8088”.

1. The stack pointer register contains

a) address of the stack segment
b) pointer address of the stack segment
c) offset of address of stack segment
d) data present in the stack segment
View Answer

Answer: c
Explanation: The stack pointer register contains the offset of the address of the stack
segment.

2. The stack segment register contains

a) address of the stack segment
b) base address of the stack segment
c) pointer address of the stack segment
d) data in the stack segment
View Answer

Answer: b
Explanation: The stack segment register contains base address of the stack segment in the
memory. The stack pointer register (sP) and stack segment register (SS) together address the
stack-top.

3. PUSH operation
a) decrements SP
b) increments SP
c) decrements SS
d) increments SS
View Answer

Answer: a
Explanation: Each PUSH operation decrements the SP ( Stack Pointer) register.

4. POP operation
a) decrements SP
b) increments SP
c) decrements SS
d) increments SS
View Answer

Answer: b
Explanation: Each POP operation increments the SP ( Stack Pointer) register.

5. The register or memory location that is pushed into the stack at the end must be
a) popped off last
b) pushed off first
c) popped off first
d) pushed off last
View Answer

Answer: c
Explanation: The data can be retrieved by POP operation and as in stack, the data that is
pushed at the end must be popped off first.

6. In the instruction, ASSUME CS : CODE, DS : DATA, SS : STACK

the ASSUME directive directs to the assembler the
a) address of the stack segment
b) pointer address of the stack segment
c) name of the stack segment
d) name of the stack, code and data segments
View Answer

Answer: d
Explanation: The directive ASSUME facilitates to name the segments with the desired name
that is not a mnemonic or keyword.
7. When a stack segment is initialised then
a) SS and SP are initialised
b) only SS is initialised
c) only SP is initialised
d) SS and SP need not be initialised
View Answer

Answer: a
Explanation: Though the Stack segment is initialised, the SS and SP pointers must be
initialised.

8. The number of PUSH instructions and POP instructions in a subroutine must be

a) PUSH instructions must be greater than POP instructions
b) POP instructions must be greater than PUSH instructions
c) Both must be equal
d) Instructions may be any kind
View Answer

Answer: c
Explanation: The number of PUSH instructions must be equal to the number of POP
instructions.

9. 8086 does not support

a) Arithmetic operations
b) logical operations
c) BCD operations
d) Direct BCD packed multiplication
View Answer

Answer: d
Explanation: The 8086 microprocessor does not support direct BCD packed operations.

10. For 8086 microprocessor, the stack segment may have a memory block of a maximum of
a) 32K bytes
b) 64K bytes
c) 16K bytes
d) NONE
View Answer

Answer: b
Explanation: In 8086 microprocessor, the memory segments each have a memory of 64K
bytes.

This set of Microprocessor Multiple Choice Questions & Answers (MCQs) focuses on
“Interrupts and Interrupt Service Routines”.
1. While CPU is executing a program, an interrupt exists then it
a) follows the next instruction in the program
b) jumps to instruction in other registers
c) breaks the normal sequence of execution of instructions
d) stops executing the program
View Answer

Answer: c
Explanation: An interrupt function is to break the sequence of operation.

2. An interrupt breaks the execution of instructions and diverts its execution to

a) Interrupt service routine
b) Counter word register
c) Execution unit
d) control unit
View Answer

Answer: a
Explanation: An interrupt transfers the control to interrupt service routine (ISR). After
executing ISR, the control is transferred back again to the main program.

3. While executing the main program, if two or more interrupts occur, then the sequence of
appearance of interrupts is called
a) multi-interrupt
b) nested interrupt
c) interrupt within interrupt
d) nested interrupt and interrupt within interrupt
View Answer

Answer: d
Explanation: If an interrupt occurs while executing a program, and the processor is executing
the interrupt, if one more interrupt occurs again, then it is called a nested interrupt.

4. Whenever a number of devices interrupt a CPU at a time, and if the processor is able to
handle them properly, it is said to have
a) interrupt handling ability
b) interrupt processing ability
c) multiple interrupt processing ability
d) multiple interrupt executing ability
View Answer

Answer: c
Explanation: The processor if handles more devices as interrupts then it has multiple interrupt
processing ability.

5. NMI stands for

a) nonmaskable interrupt
b) nonmultiple interrupt
c) nonmovable interrupt
d) none of the mentioned
View Answer

Answer: a
Explanation: NMI is the acronym for nonmaskable interrupt.

7. If any interrupt request given to an input pin cannot be disabled by any means then the
input pin is called
a) maskable interrupt
b) nonmaskable interrupt
c) maskable interrupt and nonmaskable interrupt
d) none of the mentioned
View Answer

Answer: b
Explanation: A nonmaskable interrupt input pin is one which means that any interrupt request
at NMI (nonmaskable interrupt) input cannot be masked or disabled by any means.

8. The INTR interrupt may be

a) maskable
b) nonmaskable
c) maskable and nonmaskable
d) none of the mentioned
View Answer

Answer: a
Explanation: the INTR (interrupt request) is maskable or can be disabled.
advertisement

9. The Programmable interrupt controller is required to

a) handle one interrupt request
b) handle one or more interrupt requests at a time
c) handle one or more interrupt requests with a delay
d) handle no interrupt request
View Answer

Answer: b
Explanation: If more than one interrupt request (INTR) occurs at a time, then an external chip
called programmable interrupt controller is required to handle them.

10. The INTR interrupt may be masked using the flag

a) direction flag
b) overflow flag
c) interrupt flag
d) sign flag
View Answer

Answer: c
Explanation: If a microprocessor wants to serve any interrupt then interrupt flag, IF=1. If
interrupt flag, IF=0, then the processor ignores the service.
This set of Microprocessor Multiple Choice Questions & Answers (MCQs) focuses on
“Interrupt Cycle of 8086/8088”.

1. If an interrupt is generated from outside the processor then it is an

a) internal interrupt
b) external interrupt
c) interrupt
d) none of the mentioned
View Answer

Answer: b
Explanation: If an external device or a signal interrupts the processor from outside then it is
an external interrupt.

2. If the interrupt is generated by the execution of an interrupt instruction then it is

a) internal interrupt
b) external interrupt
c) interrupt-in-interrupt
d) none of the mentioned
View Answer

Answer: a
Explanation: The internal interrupt is generated internally by the processor circuit or by the
execution of an interrupt instruction.

3. Example of an external interrupt is

a) divide by zero interrupt
b) keyboard interrupt
c) overflow interrupt
d) type2 interrupt
View Answer

Answer: b
Explanation: Since the keyboard is external to the processor, it is an external interrupt.

4. Example of an internal interrupt is

a) divide by zero interrupt
b) overflow interrupt
c) interrupt due to INT
d) all of the mentioned
View Answer

Answer: d
Explanation: Since the interrupts occur within the processor itself, they are called internal
interrupts.

5. The interrupt request that is independent of IF flag is

a) NMI
b) TRAP
c) Divide by zero
d) All of the mentioned
View Answer

Answer: d
Explanation: These requests are independent of IF flag.

6. The type of the interrupt may be passed to the interrupt structure of CPU from
a) interrupt service routine
b) stack
c) interrupt controller
d) none of the mentioned
View Answer

Answer: c
Explanation: After an interrupt is acknowledged, the CPU computes the vector address from
the type of the interrupt that may be passed to the internal structure of the CPU from an
interrupt controller in case of external interrupts.

7. During the execution of an interrupt, the data pushed into the stack is the content of
a) IP
b) CS
c) PSW
d) All of the mentioned
View Answer

Answer: d
Explanation: The contents of IP, CS and PSW are pushed into the stack during the execution.

8. After every response to the single step interrupt the flag that is cleared is
a) IF (Interrupt Flag)
b) TF (Trap Flag)
c) OF (Overflow Flag)
d) None of the mentioned
View Answer

Answer: b
Explanation: If the trap flag is set then the processor enters the single step execution mode.
After the execution, the trap flag is cleared.

9. At the end of ISR, the instruction should be

a) END
b) ENDS
c) IRET
d) INTR
View Answer

Answer: c
Explanation: After the execution of the ISR, the control must go to the previous program
(maybe main program) which was being executed. To execute it, IRET is placed at the end of
ISR.
10. When the CPU executes IRET,
a) contents of IP and CS are retrieved
b) the control transfers from ISR to main program
c) clears the trap flag
d) clears the interrupt flag
View Answer

Answer: a
Explanation: When the instruction IRET is executed, the contents of flags, IP and CS which
were saved at the stack by the CALL instruction are retrieved to the respective registers

This set of Microprocessor Multiple Choice Questions & Answers (MCQs) focuses on “Non
Maskable Interrupt and Maskable Interrupt (INTR)”.

1. The interrupt for which the processor has the highest priority among all the external
interrupts is
a) keyboard interrupt
b) TRAP
c) NMI
d) INT
View Answer

Answer: c
Explanation: The Non-Maskable Interrupt input pin has the highest priority among all the
external interrupts.

2. The interrupt for which the processor has highest priority among all the internal interrupts
is
a) keyboard interrupt
b) TRAP
c) NMI
d) INT
View Answer

Answer: b
Explanation: TRAP is the internal interrupt that has highest priority among all the interrupts
except the Divide By Zero (Type 0) exception.

3. In case of string instructions, the NMI interrupt will be served only after
a) initialisation of string
b) execution of some part of the string
c) complete string is manipulated
d) the occurrence of the interrupt
View Answer

Answer: c
Explanation: When NMI is activated, the current instruction being executed is completed and
then NMI is served. In the case of string instructions, it is served after the complete string is
manipulated.

4. The NMI pin should remain high for atleast

a) 4 clock cycles
b) 3 clock cycles
c) 1 clock cycle
d) 2 clock cycles
View Answer

Answer: d
Explanation: The NMI pin should remain high for atleast 2 clock cycles and need not be
synchronized with the clock for being sensed.

5. The INTR signal can be masked by resetting the

a) TRAP flag
b) INTERRUPT flag
c) MASK flag
d) DIRECTION flag
View Answer

Answer: b
Explanation: The INTR signal can be masked by resetting the interrupt flag.

6. For the INTR signal, to be responded to in the next instruction cycle, it must go ________
in the last clock cycle of the current instruction
a) high
b) low
c) high or low
d) unchanged
View Answer

Answer: a
Explanation: The INTR signal must go high in the clock cycle of the current instruction in
order to respond in the next instruction cycle.

7. The status of the pending interrupts is checked at

a) the end of main program
b) the end of all the interrupts executed
c) the beginning of every interrupt
d) the end of each instruction cycle
View Answer

Answer: d
Explanation: At the end of each instruction, the status of the pending interrupts is checked.

8. Once the processor responds to an INTR signal, the IF is automatically

a) set
b) reset
c) high
d) low
View Answer

Answer: b
Explanation: The IF is automatically reset when the processor responds to an INTR signal. If
the processor wants to respond to any type of INTR signal further then, the IF should again
be set.

9. If the pin LOCK (active low based) is low at the trailing edge of the first ALE pulse, then
till the start of the next machine cycle, the pin LOCK (active low) is
a) low
b) high
c) low or high
d) none of the mentioned
View Answer

Answer: a
Explanation: The pin LOCK (active low) remains low till the start of the next machine cycle.

10. With the trailing edge of the LOCK (active low), the INTA (active low) goes low and
remains in it for
a) 0 clock cycle
b) 1 clock cycle
c) 2 clock cycles
d) 3 clock cycles
View Answer

Answer: c
Explanation: The INTA (active low) goes low and remains low for two clock cycles before
returning back to the high state.

This set of Microprocessors Interview Questions and Answers for freshers focuses on
“Interrupt Programming, Passing Parameters to Procedures, Handling Programs of Size More
Than 64KB”.

1. The method of defining the interrupt service routine for software is

a) same as that of hardware
b) difficult than hardware
c) easier than software
d) none of the mentioned
View Answer

Answer: a
Explanation: For both software and hardware, the method of defining the interrupt service
routine is the same.

2. While programming for any type of interrupt, the interrupt vector table is set
a) externally
b) through a program
c) either externally or through the program
d) externally and through the program
View Answer

Answer: c
Explanation: The programmer must, either externally or through the program, set the
interrupt vector table for that type preferably with the CS and IP addresses of the interrupt
service routine.

3. To execute a program one should

a) assemble the program
b) link the program
c) apply external pulse
d) all of the mentioned
View Answer

Answer: d
Explanation: To execute a program, first assemble it, link it and then execute it. After
execution, a new file RESULT is created in the directory. Then external pulse is applied to
IRQ2 pin, and this will again cause the execution of ISR into the file.

4. Procedures are also known as

a) macros
b) segment
c) subroutines
d) none
View Answer

Answer: c
Explanation: Procedures are also known as subroutines.

5. Procedures, for their execution, require

a) input data
b) output data
c) constants
d) input data or constants
View Answer

Answer: d
Explanation: Procedures require input data or constants for their execution. Their data or
constants may be passed to the subroutine by the main program.

6. The technique that is used to pass the data or parameter to procedures in assembly
language program is by using
a) global declared variable
b) registers
c) stack
d) all of the mentioned
View Answer
Answer: d
Explanation: The techniques that are used to pass the data or parameter to procedures are by
using global declared variable, registers of CPU, memory locations, stack, PUBLIC &
EXTRN.

7. If a procedure is interactive, then

a) it accepts inputs directly from input devices
b) it uses global declared variable technique
c) it uses stack
d) it uses memory locations
View Answer

Answer: a
Explanation: If a procedure is interactive, then it accepts the inputs directly from input
devices.

8. For passing the parameters to procedures using the PUBLIC & EXTRN directives, it must
be declared PUBLIC in the
a) subroutine
b) procedure
c) main routine
d) main routine and subroutine
View Answer

Answer: c
Explanation: For passing the parameters to procedures, it must be declared PUBLIC in the
main routine and the same should be declared EXTRN in the procedure.

9. The technique to estimate the size of an executable program, before it is assembled and
linked is
a) memory location technique
b) global variable technique
c) stack
d) none
View Answer

Answer: d
Explanation: There is no technique to estimate the size of an executable program before it is
assembled and linked.

10. To estimate the size of an executable program before it is assembled and linked, the
programming methodology concerned is by writing
a) programs with more than one segment for data and code
b) programs with FAR subroutines each of size up to 64KB
c) programs with more than one segment for stack
d) all of the mentioned
View Answer

Answer: d
Explanation: By writing programs with more than one segment for data, code or stack or by
writing programs with FAR subroutines each of size 64KB, the size of an executable program
can be estimated.

This set of Microprocessor Multiple Choice Questions & Answers (MCQs) focuses on
“Macros”.

1. If a number of instructions are repeating through the main program, then to reduce the
length of the program, __________ is used.
a) procedure
b) subroutine
c) macro
d) none of the mentioned
View Answer

Answer: c
Explanation: For a certain number of instructions that are repeated in the main program,
when macro is defined then the code of a program is reduced by placing the name of the
macro at which the set of instructions are needed to be repeated.

2. The process of assigning a label or macroname to the string is called

a) initialising macro
b) initialising string macro
c) defining a string macro
d) defining a macro
View Answer

Answer: d
Explanation: The process of assigning a label to the string is called defining a macro.

3. A macro within a macro is called

a) macro-within-macro
b) nested macro
c) macro-in-macro
d) none of the mentioned
View Answer

Answer: b
Explanation: A macro may be called from inside a macro. This type of macro is called nested
macro.

4. A macro can be defined as

a) beginning of a program
b) end of a program
c) after initialisation of program
d) anywhere in a program
View Answer
Answer: d
Explanation: A macro can be defined anywhere in a program.

5. A macro can be used as ________

a) in data segment
b) to represent directives
c) to represent statements
d) all of the mentioned
View Answer

Answer: d
Explanation: A macro may be used in data segment and can also be used to represent
statements and directives.

6. The end of a macro can be represented by the directive.

a) END
b) ENDS
c) ENDM
d) ENDD
View Answer

Answer: c
Explanation: The ENDM directive marks the end of the instructions or statements sequence
assigned with the macro name.

7. Inserting the statements and instructions represented by macro, directly at the place of the
macroname, in the program, is known as
a) calling a macro
b) inserting a macro
c) initializing a macro
d) none of the mentioned
View Answer

Answer: a
Explanation: Inserting the statements and instructions at the place of macroname, in the
program, is known as calling a macro.

8. The time required for execution of a macro is ________ that of the procedure.
a) greater than
b) less than
c) equal to
d) none of the mentioned
View Answer

Answer: b
Explanation: The time required for execution of a macro is less than that of procedure as it
does not contain CALL and RET instructions as the procedures do.

9. Which of the following statements is incorrect?

a) complete code of instruction string is inserted at each place, wherever the macroname
appears
b) macro requires less time of execution than that of procedure
c) macro uses stack memory
d) macroname can be anything except registers and mnemonics
View Answer

Answer: c
Explanation: Macro does not require stack memory and hence has less time for execution.

10. The beginning of the macro can be represented as

a) START
b) BEGIN
c) MACRO
d) None of the mentioned
View Answer

Answer: c
Explanation: The beginning of the macro is represented as macroname followed by the
directive MACRO.
SYNTAX: macroname MACRO
EXAMPLE: STRINGS MACRO.

This set of Microprocessor Multiple Choice Questions & Answers (MCQs) focuses on
“Timings and Delays”.

1. If ‘n’ denotes the number of clock cycles and ‘T’ denotes period of the clock at which the
microprocessor is running, then the duration of execution of loop once can be denoted by
a) n+T
b) n-T
c) n*T
d) n/T
View Answer

Answer: c
Explanation: The duration of execution of the loop is the product of number of clock cycles
and the period of the clock cycle at which microprocessor is running.

2. The number of instructions actually executed by the microprocessor depends on the

a) stack
b) loop count
c) program counter
d) time duration
View Answer

Answer: b
Explanation: As the microprocessor executes each instruction corresponding loop counter
value decreases and the microprocessor executes the instructions till the loop counter
becomes zero.
3. In case of subroutines, the actual number of instructions executed by the processor depends
on
a) loop count
b) length of interrupt service routine
c) length of procedure
d) none
View Answer

Answer: c
Explanation: In case of subroutines or interrupt service routines, the number of instructions
executed by the processor depends on the length of procedure (or subroutine) or length of
interrupt service routine along with the main calling program.

4. The step included in generating delays is

a) determining exact required delay
b) selecting instructions for delay loop
c) finding period of clock frequency
d) all of the mentioned
View Answer

Answer: d
Explanation: The delays can be generated step wise.

5. The Count, N can be defined as

a) required delay/duration for execution
b) duration of execution/required delay
c) required delay/number of clock cycles
d) required delay/period of clock frequency
View Answer

Answer: a
Explanation: The count N can be defined as the required time delay by the duration for
execution of the loop once.
Count, N = required delay (Td)/duration for execution of the loop once (n*T).

6. In the instruction set,

MOV CX, BA03H

WAIT: DEC CX
NOP
JNZ WAIT
RET

if the zeroth condition is satisfied then, for execution, the JNZ instruction takes
a) 1 clock cycle
b) 2 clock cycles
c) 3 clock cycles
d) 4 clock cycles
View Answer
Answer: d
Explanation: The JNZ instruction takes only 4 clock cycles if the zeroth condition is satisfied.

7. In the instruction set,

MOV CX, BA03H

WAIT: DEC CX
NOP
JNZ WAIT
RET

if the zeroth condition is not satisfied, then the JNZ instruction takes
a) 2 clock cycles
b) 8 clock cycles
c) 16 clock cycles
d) 64 clock cycles
View Answer

Answer: c
Explanation: The JNZ instruction takes 16 clock cycles if the zeroth condition is not satisfied.
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8. The maximum count value of 16-bit count register puts a limitation on

a) memory usage
b) storage of address of registers
c) to generate clock pulse
d) to generate maximum delay
View Answer

Answer: d
Explanation: The maximum count value of 16-bit count register is FFFFH. This may put the
limitation on the maximum delay that can be generated using the instructions.

9. When large delays are required, then to serve the purpose

a) one or more count registers can be used
b) one or more shift registers can be used
c) one or more pointer registers can be used
d) one or more index registers can be used
View Answer

Answer: a
Explanation: One or more count registers can be used to serve large delays.

This set of Microprocessor Multiple Choice Questions & Answers (MCQs) focuses on
“Semiconductor Memory Interfacing”.

1. The semiconductor memories are organised as __________ dimension(s) of array of

memory locations.
a) one dimensional
b) two dimensional
c) three dimensional
d) none
View Answer

Answer: b
Explanation: The semiconductor memories are organised as two dimensions of an array
which consists of rows and columns.

2. If a location is selected, then all the bits in it are accessible using a group of conductors
called
a) control bus
b) address bus
c) data bus
d) either address bus or data bus
View Answer

Answer: c
Explanation: The bits in a selected location are accessible using data bus.

3. To address a memory location out of N memory locations, the number of address lines
required is
a) log N (to the base 2)
b) log N (to the base 10)
c) log N (to the base e)
d) log (2N) (to the base e)
View Answer

Answer: a
Explanation: For n memory locations, log n(to the base of 2) address lines are required. For
addressing 4K bytes of memory, 12 address lines are required since log(4KB)
=log(4*1024)=log(212)=12.

4. If the microprocessor has 10 address lines, then the number of memory locations it is able
to address is
a) 512
b) 1024
c) 2048
d) none
View Answer

Answer: b
Explanation: Since for n address lines, the number of memory locations able to address is
2^n.

5. In static memory, the upper 8-bit bank of an available 16-bit memory chip is called
a) upper address memory bank
b) even address memory bank
c) static upper memory
d) odd address memory bank
View Answer

Answer: d
Explanation: In static memory, the upper 8-bit bank is called odd address memory bank.

6. In static memory, the lower 8-bit bank of an available 16-bit memory chip is called
a) lower address memory bank
b) even address memory bank
c) static lower memory bank
d) odd address memory bank
View Answer

Answer: b
Explanation: In static memory, the lower 8-bit bank is called even address memory bank.

7. In most of the cases, the method used for decoding that may be used to minimise the
required hardware is
a) absolute decoding
b) non-linear decoding
c) linear decoding
d) none
View Answer

Answer: c
Explanation: In general, linear decoding is used to minimise the required hardware.

8. To obtain 16-bit data bus width, the two 4K*8 chips of RAM and ROM are arranged in
a) parallel
b) serial
c) both serial and parallel
d) neither serial nor parallel
View Answer

Answer: a
Explanation: The two 4K*8 chips of RAM and ROM are arranged in parallel.

9. If (address line) Ao=0 then, the status of address and memory are
a) address is even and memory is in ROM
b) address is odd and memory is in ROM
c) address is even and memory is in RAM
d) address is odd and memory is in RAM
View Answer

Answer: c
Explanation: If Ao=0 then address is even and is in RAM. If Ao=1 then, address is odd and is
in RAM.

10. If at a time Ao and BHE(active low) both are zero then, the chip(s) selected will be
a) RAM
b) ROM
c) RAM and ROM
d) ONLY RAM
View Answer

Answer: c
Explanation: If at a time Ao and BHE(active low) both are zero, then both RAM and ROM
are selected.

This set of Microprocessor Multiple Choice Questions & Answers (MCQs) focuses on
“Interfacing I/O Ports”.

1. The device that enables the microprocessor to read data from the external devices is
a) printer
b) joystick
c) display
d) reader
View Answer

Answer: b
Explanation: Since joystick is an input device, it reads data from the external devices.

2. The example of output device is

a) CRT display
b) 7-segment display
c) Printer
d) All of the mentioned
View Answer

Answer: d
Explanation: The output device transfers data from the microprocessor to the external
devices.

3. The input and output operations are respectively similar to the operations,
a) read, read
b) write, write
c) read, write
d) write, read
View Answer

Answer: c
Explanation: The input activity is similar to read operation and the output activity is similar
to write operation.

4. The operation, IOWR (active low) performs

a) write operation on input data
b) write operation on output data
c) read operation on input data
d) read operation on output data
View Answer

Answer: b
Explanation: IOWR (active low) operation means writing data to an output device and not an
input device.

5. The latch or IC 74LS373 acts as

a) good input port
b) bad input port
c) good output port
d) bad output port
View Answer

Answer: c
Explanation: If the output port is to source large currents, the port lines must be buffered. So,
the latch is used as it acts as a good output port.

6. While performing read operation, one must take care that much current should not be
a) sourced from data lines
b) sinked from data lines
c) sourced or sinked from data lines
d) sinked from address lines
View Answer

Answer: c
Explanation: More current should not be sourced or sinked from data lines while reading to
avoid loading.

7. To avoid loading during read operation, the device used is

a) latch
b) flipflop
c) buffer
d) tristate buffer
View Answer

Answer: d
Explanation: A tristate buffer is used as an input device to overcome loading.

8. The chip 74LS245 is

a) bidirectional buffer
b) 8-bit input port
c) one that has 8 buffers
d) all of the mentioned
View Answer

Answer: d
Explanation: The chip 74LS245 is a bidirectional buffer that contains 8 buffers and may be
used as an 8-bit input port. But while using as an input device, only one direction is useful.
9. In 74LS245, if DIR is 1, then the direction is from
a) inputs to outputs
b) outputs to inputs
c) source to sink
d) sink to source
View Answer

Answer: a
Explanation: If DIR is 1, then the direction is from A(inputs) to B(outputs).

10. In memory-mapped scheme, the devices are viewed as

a) distinct I/O devices
b) memory locations
c) only input devices
d) only output devices
View Answer

Answer: b
Explanation: In memory-mapped scheme, the devices are viewed as memory locations and
are addressed likewise.

This set of Microprocessor Multiple Choice Questions & Answers (MCQs) focuses on “PIO
8255 (Programmable Input – Output Port)”.

1. Programmable peripheral input-output port is another name for

a) serial input-output port
b) parallel input-output port
c) serial input port
d) parallel output port
View Answer

Answer: b
Explanation: The parallel input-output port chip 8255 is also known as programmable
peripheral input-output port.

2. Port C of 8255 can function independently as

a) input port
b) output port
c) either input or output ports
d) both input and output ports
View Answer

Answer: c
Explanation: Port C can function independently either as input or as output ports.

3. All the functions of the ports of 8255 are achieved by programming the bits of an internal
register called
a) data bus control
b) read logic control
c) control word register
d) none of the mentioned
View Answer

Answer: c
Explanation: By programming the bits of control word register, the operations of the ports are
specified.

4. The data bus buffer is controlled by

a) control word register
b) read/write control logic
c) data bus
d) none of the mentioned
View Answer

Answer: b
Explanation: The data bus buffer is controlled by read/write control logic.

5. The input provided by the microprocessor to the read/write control logic is

a) RESET
b) A1
c) WR(ACTIVE LOW)
d) All of the mentioned
View Answer

Answer: d
Explanation: RD(ACTIVE LOW), WR(ACTIVE LOW), A1, A0, RESET are the inputs
provided by the microprocessor to the read/write control logic of 8255.

6. The device that receives or transmits data upon the execution of input or output
instructions by the microprocessor is
a) control word register
b) read/write control logic
c) 3-state bidirectional buffer
d) none of the mentioned
View Answer

Answer: c
Explanation: 3-state bidirectional buffer is used to receives or transmits data upon the
execution of input or output instructions by the microprocessor.

7. The port that is used for the generation of handshake lines in mode 1 or mode 2 is
a) port A
b) port B
c) port C Lower
d) port C Upper
View Answer
Answer: d
Explanation: Port C upper is used for the generation of handshake lines in mode 1 or mode 2.

8. If A1=0, A0=1 then the input read cycle is performed from

a) port A to data bus
b) port B to data bus
c) port C to data bus
d) CWR to data bus
View Answer

Answer: b
Explanation: If A1=0, A0=1 then the input read cycle is performed from port B to data bus.

9. The function, ‘data bus tristated’ is performed when

a) CS(active low) = 1
b) CS(active low) = 0
c) CS(active low) = 0, RD(active low) = 1, WR(active low) = 1
d) CS(active low) = 1 OR CS(active low) = 0, RD(active low) = 1, WR(active low) = 1
View Answer

Answer: d
Explanation: The data bus is tristated when chip select pin=1 or chip select pin=0 and read
and write signals are high i.e 1.

10. The pin that clears the control word register of 8255 when enabled is
a) CLEAR
b) SET
c) RESET
d) CLK
View Answer

Answer: c
Explanation: If reset pin is enabled then the control word register is cleare

This set of Microprocessor Multiple Choice Questions & Answers (MCQs) focuses on
“Modes of Operation of 8255”.

1. In the I/O mode, the 8255 ports work as

a) reset pins
b) set pins
c) programmable I/O ports
d) only output ports
View Answer

Answer: c
Explanation: In the I/O mode, the 8255 ports work as programmable I/O ports.
2. In BSR mode, only port C can be used to
a) set individual ports
b) reset individual ports
c) set and reset individual ports
d) programmable I/O ports
View Answer

Answer: c
Explanation: In BSR (Bit Set-Reset) Mode, port C can be used to set and reset its individual
port bits.

3. The feature of mode 0 is

a) any port can be used as input or output
b) output ports are latched
c) maximum of 4 ports are available
d) all of the mentioned
View Answer

Answer: d
Explanation: In mode 0, any port can be used as input or output and output ports are latched.

4. The strobed input/output mode is another name of

a) mode 0
b) mode 1
c) mode 2
d) none
View Answer

Answer: b
Explanation: In this mode, the handshaking signals control the input or output action of the
specified port.

5. If the value of the pin STB (Strobe Input) falls to low level, then
a) input port is loaded into input latches
b) input port is loaded into output latches
c) output port is loaded into input latches
d) output port is loaded into output latches
View Answer

Answer: a
Explanation: If the value of the pin STB (Strobe Input) falls to low level, the input port is
loaded into input latches.

6. The signal, SLCT in the direction of signal flow, OUT, indicates the selection of
a) Control word register
b) CPU
c) Printer
d) Ports
View Answer
Answer: c
Explanation: This signal indicates that the printer is selected.

7. The pulse width of the signal INIT at the receiving terminal must be more than
a) 10 microseconds
b) 20 microseconds
c) 40 microseconds
d) 50 microseconds
View Answer

Answer: d
Explanation: The pulse width of the signal must be more than 50microseconds at the
receiving terminal.

8. The level of the signal ERROR(active low) becomes ‘low’ when the printer is in
a) Paper end state
b) Offline state
c) Error state
d) All of the mentioned
View Answer

Answer: d
Explanation: The level of the signal ERROR(active low) becomes ‘low’ when the printer is in
the Paper end state, Offline state and Error state.

9. The signals that are provided to maintain proper data flow and synchronization between
the data transmitter and receiver are
a) handshaking signals
b) control signals
c) input signals
d) none
View Answer

Answer: a
Explanation: Handshaking signals maintain proper data flow and synchronization.

10. The feature of mode 2 of 8255 is

a) single 8-bit port is available
b) both inputs and outputs are latched
c) port C is used for generating handshake signals
d) all of the mentioned
View Answer

Answer: d
Explanation: In mode 2 of 8255, a single 8-bit port is available i.e group A.
This set of Microprocessors Puzzles focuses on “Interfacing Analog to Digital Data
Converters”.

1. The time taken by the ADC from the active edge of SOC(start of conversion) pulse till the
active edge of EOC(end of conversion) signal is called
a) edge time
b) conversion time
c) conversion delay
d) time delay
View Answer

Answer: c
Explanation: Broadly speaking, the time taken by the converter to calculate the equivalent
digital data output from the moment of the start of conversion is called conversion delay.

2. The popular technique that is used in the integration of ADC chips is

a) successive approximation
b) dual slope integration
c) successive approximation and dual slope integration
d) none
View Answer

Answer: c
Explanation: Successive approximation and dual slope integration are the most popular
techniques that are used in the integrated ADC chips.

3. The procedure of algorithm for interfacing ADC contain

a) ensuring stability of analog input
b) issuing start of conversion pulse to ADC
c) reading digital data output of ADC as equivalent digital output
d) all of the mentioned
View Answer

Answer: d
Explanation: The general algorithm for interfacing ADC contains ensuring the stability of
analog input, issuing start of conversion pulse to ADC, reading end of conversion signal to
mark the end of a conversion process, reading digital data output of ADC as equivalent
digital output.

4. Which is the ADC among the following?

a) AD 7523
b) 74373
c) 74245
d) ICL7109
View Answer

Answer: d
Explanation: AD 7523 is a DAC(Digital to analog converter), 74373 is a latch, 74245 is
transceiver and ICL7109 is an ADC.
5. The conversion delay in a successive approximation of an ADC 0808/0809 is
a) 100 milliseconds
b) 100 microseconds
c) 50 milliseconds
d) 50 milliseconds
View Answer

Answer: b
Explanation: The conversion delay is 100microseconds which is low as compared to other
converters.

6. The number of inputs that can be connected at a time to an ADC that is integrated with
successive approximation is
a) 4
b) 2
c) 8
d) 16
View Answer

Answer: c
Explanation: As these converters internally have 3:8 analog multiplexer, at a time 8 different
analog inputs can be connected to the chip.

7. ADC 7109 integrated by Dual slope integration technique is used for

a) low cost option
b) slow practical applications
c) low complexity
d) all of the mentioned
View Answer

Answer: d
Explanation: Compared to other 12-bit ADCs, it is of very low cost and useful for slow
practical applications.

8. Which of the following is not one of the phases of the total conversion cycle?
a) autozero phase
b) conversion phase
c) signal integrate phase
d) disintegrate phase
View Answer

Answer: b
Explanation: Autozero phase, signal integrate phase and disintegrate phase are the three
phases of total conversion cycle.

9. Which of the following phase contain feedback loop in it?

a) autozero phase
b) signal integrate phase
c) disintegrate phase
d) none
View Answer

Answer: a
Explanation: A feedback loop is closed around the system to charge the autozero capacitor to
compensate for the offset voltages in the buffer amplifier, integrator and comparator.

10. In the signal integrate phase, the differential input voltage between IN LO(input low) and
IN HI(input high) pins is integrated by the internal integrator for a fixed period of
a) 256 clock cycles
b) 1024 clock cycles
c) 2048 clock cycles
d) 4096 clock cycles
View Answer

Answer: c
Explanation: The internal integrator needs 2048 clock cycles to integrate voltage difference
between input low and input high.