Terms relevant to Verilog HDL - Module & Test bench

Any Verilog program begins with a keyword – called a “module.” A module is the name given to any
system considering it as a black box with input and output terminals. A module is the name given to
any system considering it as a black box with input and output terminals as shown in Figure

The terminals of the module are referred to as ‘ports’. The ports attached to a module can be of three
types:
 input ports through which one gets entry into the module
 output ports through which one exits the module.
 inout ports: These represent ports through which one gets entry into the module or exits the
module
All the constructs in Verilog are centered on the module.

Syntax for Module:

module module_name (port_list);
Input, output, inout declaration
Intermediate variable declarations
Functional Description
(gate / switch / data flow / Behv.)
endmodule

A test bench is HDL code that allows you to provide a documented, repeatable set of stimuli.

Syntax for Test bench:

module tb_module_name ;
Input, output, inout declaration
Intermediate variable declarations
Stimulus (initial / always)
endmodule

Design description in Verilog HDL:

The components of the target design can be described at different levels with the help of the
constructs in Verilog.

Circuit Level:
At the circuit level, a switch is the basic element with which digital circuits are built. Switches can be
combined to form inverters and other gates at the next higher level of abstraction. Verilog has the basic
MOS switches built into its constructs, which can be used to build basic circuits like inverters, basic
logic gates, simple 1-bit dynamic and static memories. They can be used to build up larger designs to
simulate at the circuit level, to design performance critical circuits.

Data Flow:
Data flow is the next higher level of abstraction. All possible operations on signals and variables are
represented here in terms of assignments. All logic and algebraic operations are accommodated. The
assignments define the continuous functioning of the concerned block. At the data flow level, signals
Page 1 of 12
are assigned through the data manipulating equations. All such assignments are concurrent in nature.
The design descriptions are more compact than those at the gate level.
Behavioral Level:
Behavioral level constitutes the highest level of design description; it is essentially at the system level
itself . With the assignment possibilities, looping constructs and conditional branching possible, the
design description essentially looks like a “C” program. The statements involved are “dense” in
function. Compactness and the comprehensive nature of the design description make the development
process fast and efficient.

Data types in Verilog HDL:

The data handled in Verilog fall into two categories:
(i). Net data type
(ii).Variable data type

The two types differ in the way they are used as well as with regard to their respective hardware
structures. Data type of each variable or signal has to be declared prior to its use. The same is valid
within the concerned block or module.

Nets
A net signifies a connection from one circuit unit to another. Such a net carries the value of the signal it
is connected to and transmits to the circuit blocks connected to it. If the driving end of a net is left
floating, the net goes to the high impedance state. A net can be specified in different ways.
wire: It represents a simple wire doing an interconnection. Only one output is connected to a wire and is
driven by that.

tri: It represents a simple signal line as a wire. Unlike the wire, a tri can be driven by more than one
signal outputs.
Functionally, wire and tri are identical. Distinct nomenclatures are provided for the convenience of
assigning roles.
Variable Data Type:
A variable is an abstraction for a storage device. It can be declared through the keyword reg and stores
the value of a logic level: 0, 1, x, or z. A net or wire connected to a reg takes on the value stored in the
reg and can be used as input to other circuit elements. But the output of a circuit cannot be connected to
a reg. The value stored in a reg is changed through a fresh assignment in the program. time, integer,
real, and realtime are the other variable types of data; these are dealt with later.

System tasks available in Verilog HDL for monitoring and controlling simulation:
SYSTEM TASKS: During the simulation of any design, a number of activities are to be carried out to
monitor and control simulation. The “$” symbol identifies a system task.
A task has the format $<keyword>

$display:
When the system encounters this task, the specified items are displayed in the formats specified and the
system advances to a new line. The structure, format, and rules for these are the same as for the “printf”
/ “scanf” function in C.

Page 2 of 12
Examples
$display (“The value of a is : a = , %d”, a);
Execution of this line results in printing the value of a as a decimal number (specified by “%d”). The
string present within the inverted commas specifies this. Thus if a has the value 3.5, we get the display
The value of a is : a = 3.5.

After printing the above line, the system advances to the next line.

$monitor

The $monitor task monitors the variables specified whenever any one of those specified changes.
During the running of the program the monitor task is invoked and the concerned quantities displayed
whenever any one of these changes. Following this, the system advances to the next line. A monitor
statement need appear only once in a simulation program. All the quantities specified in it are
continuously monitored. The format for the $monitor task is identical to that of the $displaytask.
Examples
$monitor (“The value of a is : a = , %d”, a);
With the task, whenever the value of a changes during execution of a program, its new value is printed
according to the format specified. Thus if the value of a changes to 2.4 at any time during execution of
the program, we get the following display on the monitor.

Tasks for Control of Simulation:

Two system tasks are available for control of simulation:
$finish task, when encountered, exits simulation. Control is reverted to the Operating System.
Normally the simulation time and location are also printed out by default as part of the exit operation.
$stop task, suspends simulation; if necessary the simulation can be resumed by user intervention.
Thus with the stop task, the simulator is in an interactive mode. In contrast with $finish, simulation has
to be started afresh.

Logic values supported by Verilog HDL:

Signal lines, logic values appearing on signal lines, etc., can normally take two logic
levels:
1 - signifies the 1 or high or true level
0 - signifies the 0 or low or false level.
Two additional levels are also possible – designated as x and z. Here x represents an unknown or an
uninitialized value. This corresponds to the don’t- care case in logic circuits. z represents / signifies a
high impedance state. This is possible when a signal line is tri-stated or left floating. The following are
noteworthy here:
When a variable in an expression is in the z state, the effect is the same as it having z value. But when
an input to a gate is in the z state (see Chapter 4), it is equivalent to having the x value.
The MOS switches form an exception to the above. If the input to a MOS switch is in the z state, its
output too remains at the z state.
With a few exceptions all data types in Verilog can take on all the 4 logic values or levels. The event
is an exception to this. It cannot store any value. The trireg cannot take on the z value.

Page 3 of 12
Gate primitives in Verilog HDL.

All the basic gates are available as “Primitives” in Verilog

Basic gate primitives in Verilog with details:

Gate Mode of instantiation Output port(s) Input port(s)
AND and ga ( o, i1, i2, . . . i8); o i1, i2, . .
OR or gr ( o, i1, i2, . . . i8); o i1, i2, . .
NAND nand gna ( o, i1, i2, . . . i8); o i1, i2, . .
NOR nor gnr ( o, i1, i2, . . . i8); o i1, i2, . .
XOR xor gxr ( o, i1, i2, . . . i8); o i1, i2, . .
XNOR xnor gxn ( o, i1, i2, . . . i8); o i1, i2, . .
BUF buf gb ( o1, o2, …. i); o1, o2, o3, . . i
NOT not gn (o1, o2, o3, . . . i); o1, o2, o3, . . i

Rules for deciding the output values of gate primitives for different input combinations:

Type of gate 0 output state 1 output state x output state

Any one of the inputs is zero All the inputs are at one
AND
All the inputs are at one Any one of the inputs is zero
NAND
All the inputs are at zero Any one of the inputs is one
OR All other cases
Any one of the inputs is one All the inputs are at zero
NOR
XOR If every one of the inputs is definite at zero or one, the output is If any one of the inputs is
zero or one as decided by the XOR or XNOR function at x or z state, the output
XNOR
is at x state
If the only input is at 0 state If the only input is at 1 state
BUF
If the only input is at 1 state If the only input is at 0 state All other cases of inputs
NOT

Gate delays with instantiations:

Gate Delay:

Gates too can have delays associated with them. These can be specified as part of the instantiation itself.
and#3 g ( a, b, c);
The above represents an AND gate description with a uniform delay of 3 ns for all transitions from input
to output. A more detailed description can be as follows:

and#(2, 1) (a, b, c);

With the above statement the positive (0 to 1) transition at the output has a delay of 2 time steps while
the negative (1 to 0) transition has a delay of 1 time step.

A module to illustrate the delays associated with gate primitives.

module gade(a,a1,b,c,b1,c1);
input b,c,b1,c1;
output a,a1;
or #3gg1(a1,c1,b1);
and #(2,1)gg2(a,c,b);
endmodule

Page 4 of 12
A test bench for the same is also shown.,
module tst_gade();
reg b,c,b1,c1;
wire c,c1;
gade ggde(a,a1,b,c,b1,c1);
initial
begin
b =1'b0;
c =1'b0;
b1 =1'b0;
c1=1'b0;
end
always begin
#5 b =1'b0; c =1'b0; b1 =1'b1; c1=1'b1;
#5 b =1'b1; c =1'b1; b1 =1'b0; c1=1'b0;
#5 b =1'b1; c =1'b0; b1 =1'b1; c1=1'b0;
#5 b =1'b0; c =1'b1; b1 =1'b0; c1=1'b1;
#5 b =1'b1; c =1'b1; b1 =1'b1; c1=1'b1;
#5 b =1'b1; c =1'b1; b1 =1'b1; c1=1'b1;
end
initial$monitor($time , " b= %b , c = %b , b1 =%b
,c1 = %b , a = %b ,a1 = %b" ,b,c,b1,c1,a,a1);
initial #30 $stop;
endmodule

Types of tri-state buffers available in Verilog HDL:

Typical instantiation Functional representation Functional description

in out Out = in if control = 1;

bufif1(out, in, control); else
out = z
control

in out Out = in if control = 0;

bufif0(out, in, control); else
out = z
control

Out = complement of in
notif1(out, in, control); in out if control = 1;
else
out = z
control

Out = complement of in
notif0(out, in, control); in out if control = 0;
else
out = z
control

Four types of tri-state buffers are available in Verilog as primitives. Their outputs can be turned ON or OFF by a control
signal. The direct buffer is instantiated as
Bufif1nn (out, in, control);

The symbol of the buffer is shown in Figure :

We have
out as the single output variable
in as the single input variable and

Page 5 of 12
 control as the single control signal variable.

When control = 1, out = in.

When control = 0, out is cut off from the input and tri-stated.
The output, input and control signals should appear in the instantiation in the same order as above.
Details of bufif1 as well as the other tri-state type primitives are shown in Table.
In all the cases shown in Table out is the output, in is the input, and control, the control variable.

Representation of a number in verilog HDL:

Real Numbers:

Real numbers can be specified in decimal or scientific notation. The decimal notation has the form
-a.b:
where a, b, the negative sign, and the decimal point have the usual significance. The fields a and b must be present in the
number. A number can be specified in scientific notation as
4.3e2:

where 4.3 is the mantissa and 2 the exponent. The decimal equivalent of this number is 430. Other examples of numbers
represented in scientific notation are

–4.3e2, –4.3e–2, and 4.3e–2. The representations are common.

Integer Numbers:
Integers can be represented in two ways. In the first case it is a decimal number – signed or unsigned; an unsigned number is
automatically taken as a positive number. Some examples of valid number representations of this category are given below:
2 25 253 –253
The following are invalid since non-decimal representations are not permissible.
2a B8 –2a –B8
Normally the number is taken as 32 bits wide. Thus all the following numbers are assigned 32 bits of width:
2 25 53 –2 –25 –253
If a design description has a number specified in the form given here, the circuit synthesizer program will assign 32 bits of
width to it and to all the related circuits.
Number representation is more specific – though elaborate. The number can be specified in binary, octal, decimal, or
hexadecimal form. The representation has three tokens with an optional sign preceding it.

Page 6 of 12
Different ways of number representations in Verilog:

Representation Remarks

33 Both of these represent decimal numbers of unspecified size – normally interpreted by

‘d33 Verilog as 32 bitwide, i.e., 0000 0000 0000 0000 0000 0000 0010 0001

9’d439 All these represent 3 digit decimal numbers. D &d both specify decimal numbers. “_”
9’D439 (underscore) is ignored
9’D4_39
9’b1_10111x01 All these represent binary numbers of value 11011x01. B & b specify binary numbers.
9’b11011x01 “_” is ignored. xsignifies the concerned bit to be of unknown value.
9’B11011x01
9’o123 All these represent 9-bit octal numbers. The binary equivalents are 001 010 011,
9’O123 001 010 011, 001 xxx011, 001 010 zzzrespectively. zsignifies the concerned bits to be
9’o1x3 in the high impedance state.
9’o12z
‘o213 An octal number of unspecified size having octal value 213.

8’ha5 All these are 8 bit-wide-hex numbers of hex value a5h. The equivalent binary value is
8’HA5 1010 0101.
8’hA5
8’ha_5
11’hb0 A 11 bit number with a hex assignment. Its value is 000 1011 0000. The number of bits
specified is more than that indicated in the value field. Enough zeros are padded to the
left as shown.
9’hza A hex number of 9 bits. Its value is taken as zzzzz1010.

5’hza A 5-bit hex number. Its value is taken as z1010.

5’h?a A 5-bit hex number. Its value is taken as z1010. ‘?’ is another representation for ‘z’.

-5’h1a Negative numbers. Negative numbers are represented in 2’s complement form.
-3’b101

-4’d7 A 4 bit negative number. Its value in 2’s complement form is 7. Thus the number is
actually – (16 – 7) = –9.

Strengths in Verilog HDL:

The logic levels are also associated with strengths. In many digital circuits, multiple assignments are often combined to
reduce silicon area or to reduce pin- outs. To facilitate this, one can assign strengths to logic levels. Verilog has eight
strength levels – four of these are of the driving type, three are of capacitive type and one of the hi-Z type.
When a signal line is driven simultaneously from two sources of different strength levels, the stronger of the two prevails. A
few illustrative examples are considered here.
If a signal line a is driven by two sources – b at 1 level with strength “strong1” and c at level 0 with strength “pull0”– a
will take the value 1.
If a signal line a is driven by two sources – b at 1 level with strength “pull1” and c at level 0 with strength “strong0,”
a will take the value 0.
If a signal line a is driven by two sources – b at 1 level with strength “strong1” and c at level 0 with strength
“strong0,” a will take the value x (indeterminate).

If a signal line a is driven by two sources – b at 1 level with strength “weak1” and c at level 0 with strength “large0,”
a will take the value 0.

Page 7 of 12
 (Note : large signifies a capacitive drive on a tri-stated line whereas weak signifies a gate / assigned output drive with a
high source impedance; despite this, due to the higher strength level, the large signal prevails.

Strength level
(signifies inverse
Strength of source Specification
Abbreviation Element modeled
name impedance) keyword
Supply Supply1 Su1 Power supply
7 connection
drive Supply0 Su0
Strong1 St1 Default gate
Strong
6 and assign
drive Strong0 St0 output strength
Pull1 Pu1 Gate and assign
Pull drive 5 output strength
Pull0 Pu0
Large Large1 La1 Size of trireg net
4 capacitor
capacitor Large0 La0
Weak1 We1 Gate and assign
Weak drive 3 output strength
Weak0 We0
Medium Medium1 Me1 Size of trireg net
2 capacitor
capacitor Medium0 Me0
Small Small1 Sm1 Size of trireg net
1 capacitor
capacitor Small0 Sm0
High Highz1 Hi1 Tri-stated line
0
impedance Highz0 Hi0

AOI logic diagram in gate level modeling using verilog HDL:

The circuit has been realized here by instantiating the AND and NOR gate primitives. The module aoi_gate has input and
output ports since it describes a circuit with signal inputs and an output.

g1

o1
g3
o2

g2

The module aoi_st is a stimulus module. It generates inputs to the aoi_gate module and gets its output. It has no input or
outputports.
module for the aoi-gate of instantiating the gate primitives

module aoi_gate(o,a1,a2,b1,b2);
input a1,a2,b1,b2;
output o;
wire o1,o2;
and g1(o1,a1,a2);
and g2(o2,b1,b2);
nor g3(o,o1,o2);
endmodule
Test-bench for the aoi_gate:
module aoi_st;
reg a1,a2,b1,b2;
wire o;
initial
begin

Page 8 of 12
 a1 =0;
a2 =0;
b1 =0;
b2 =0;
#3 a1 =1;
#3 a2 =1;
#3 b1 =1;
#3 b2 =0;
#3 a1 =1;
#3 a2 =0;
#3 b1 =0;
End
initial #100 $stop;
initial$monitor($time,"o = %b , a1 = %b , a2 = %b ,
b1 = %b ,b2 = %b",
o,a1,a2,b1,b2);
aoi_gate gg(o,a1,a2,b1,b2);
endmodule

Verilog code for 4X1 multiplexer using tri state buffers in gate level modeling:

module ttrimux4_1(out,e,i,s);
input[3:0]i;
input e;
input[1:0]s;
output out;
tri o;
tri [1:0]o1;
bufif0 g1(o1[0],i[0],s[0]);
bufif1 g2(o1[0],i[1],s[0]);
bufif0 g3(o1[1],i[2],s[0]);
bufif1 g4(o1[1],i[3],s[0]);
bufif0 g5(o,o1[0],s[1]);
bufif1 g6(o,o1[1],s[1]);
bufif1 g7(out,o,e);
endmodule

Testbench:

module ttst_ttrimux4_1();
reg e;
reg[3:0]i;
reg[1:0]s;
ttrimux4_1 mm(out,e,i,s);
initial
begin
e = 0;
i = 4'b 0000;
end
always
begin
#4 e =0;{i,s} = 6'b 0001_00;
#4 e =1;{i,s} = 6'b 0001_00;
#4 e =1;{i,s} = 6'b 0010_01;
#4 e =1;{i,s} = 6'b 0000_01;
#4 e =1;{i,s} = 6'b 0100_10;
#4 e =1;{i,s} = 6'b 0101_10;
#4 e =1;{i,s} = 6'b 1000_11;
#4 e =1;{i,s} = 6'b 0000_11;
end
initial $monitor($time ," enable e = %b , s= %b , input i = %b ,output out = %b ",e
,s,i,out);
initial #48 $stop;
endmodule

Page 9 of 12
Verilog code for 4X1 multiplexer in gate level modeling:
module mux4_1(y,i,s);
input [3:0] i;
input [1:0] s;
output y;
wire [1:0] ss;
wire [3:0]yy;
not (ss[0],s[0]),(ss[1],s[1]);
and (yy[0],i[0],ss[0],ss[1]);
and(yy[1],i[1],s[0],ss[1]);
and(yy[2],i[2],ss[0],s[1]);
and (yy[3],i[3],s[0],s[1]);
or (y,yy[3],yy[2],yy[1],yy[0]);
endmodule

Test-bench:
module tst_mux4_1();
reg [3:0]i;
reg [1:0] s;
mux4_1 mm(y,i,s);
initial
begin
#2{i,s} = 6'b 0000_00;
#2{i,s} = 6'b 0001_00;
#2{i,s} = 6'b 0010_01;
#2{i,s} = 6'b 0100_10;
#2{i,s} = 6'b 1000_11;
#2{i,s} = 6'b 0001_00;
end initial
$monitor($time," input s = %b,y = %b" ,s,y);
endmodule

OAI logic diagram and develop verilog code in gate level modeling:

module for the oai-gate of instantiating the gate primitives

module oai_gate(o,a1,a2,b1,b2);
input a1,a2,b1,b2;
output o;
wire o1,o2;
or g1(o1,a1,a2);
or g2(o2,b1,b2);
nand g3(o,o1,o2);
endmodule
Test-bench for the oai_gate:
module oai_st;
reg a1,a2,b1,b2;
wire o;
initial
begin
a1 =0;a2 =0;b1 =0;b2 =0;
#3 a1 =1; #3 a2 =1; #3 b1 =1; #3 b2 =0;
#3 a1 =1; #3 a2 =0; #3 b1 =0;
End
initial #100 $stop;
initial$monitor($time,"o = %b , a1 = %b , a2 = %b ,
b1 = %b ,b2 = %b",
o,a1,a2,b1,b2);
oai_gate gg(o,a1,a2,b1,b2);
endmodule

Page 10 of 12
Verilog code in gate level modeling for the following logic equation. F  AB  BC  CA :

module logic(f,A,B,C);
input A,B,C;
output f;
wire x,y,z;
and g1(x,A,B);
and g2(y,B,C);
and g3 (z,C,A);
or (f,x,y,z);
endmodule

Verilog code for 4X1 multiplexer in gate level modeling:

module mux4_1(y,i,s);
input [3:0] i;
input [1:0] s;
output y;
wire [1:0] ss;
wire [3:0]yy;
not (ss[0],s[0]),(ss[1],s[1]);
and (yy[0],i[0],ss[0],ss[1]);
and(yy[1],i[1],s[0],ss[1]);
and(yy[2],i[2],ss[0],s[1]);
and (yy[3],i[3],s[0],s[1]);
or (y,yy[3],yy[2],yy[1],yy[0]);
endmodule

Test-bench
module tst_mux4_1();
reg [3:0]i;
reg [1:0] s;
mux4_1 mm(y,i,s);
initial
begin
#2{i,s} = 6'b 0000_00;
#2{i,s} = 6'b 0001_00;
#2{i,s} = 6'b 0010_01;
#2{i,s} = 6'b 0100_10;
#2{i,s} = 6'b 1000_11;
#2{i,s} = 6'b 0001_00;
end initial
$monitor($time," input s = %b,y = %b" ,s,y);
endmodule

full adder circuit using two half adders and develop Verilog code in gate level modeling:

module fa(sum,cout,a,b,cin);
input a,b,cin;
output sum,cout;
wire s,c1,c2;
ha ha1(s,c1,a,b), ha2(sum,c2,s,cin);
or(cout,c2,c1);
endmodule

Page 11 of 12
Test-bench
module tst_fa();
reg a,b,cin;
fa ff(sum,cout,a,b,cin);
initial
begin
a =0;b=0;cin=0;
end
always
begin
#2 a=1;b=1;cin=0;#2a=1;b=0;cin=1;
#2 a=1;b=1;cin=1;#2a=1;b=0;cin=0;
#2 a=0;b=0;cin=0;#2a=0;b=1;cin=0;
#2 a=0;b=0;cin=1;#2a=0;b=1;cin=1;
#2 a=1;b=0;cin=0;#2a=1;b=1;cin=0;
#2 a=0;b=1;cin=0;#2 a=1;b=1;cin=1; end
initial $monitor($time ," a = %b, b = %b, cin = %b, outsum = %b, outcar = %b
", a,b,cin,sum,cout);
initial #30 $stop ;
endmodule

Page 12 of 12