Microprocessors & Interfacing
Microprocessors & Interfacing
Microprocessors & Interfacing
8086 MICROPROCESSORS
Introduction to processor:
2
Evolution of Microprocessor:
3
Evolution of Microprocessor:
The address bus is unidirectional because the address information is
always given by the Micro Processor to address a memory location
of an input / output devices.
The data bus is Bi-directional because the same bus is used for
transfer of data between Micro Processor and memory or input /
output devices in both the direction.
It has limitations on the size of data. Most Microprocessor
does not support floating-point operations.
Microprocessor contain ROM chip because it
contain instructions to execute data.
Storage capacity is limited. It has a volatile memory. In secondary
storage device the storage capacity is larger. It is a nonvolatile
memory.
4
Evolution of Microprocessor:
Primary devices are: RAM (Read / Write memory, High Speed,
Volatile Memory) / ROM (Read only memory, Low Speed, Non Volatile
Memory)
Compiler:
5
Evolution of Microprocessor:
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Features of RISC Processors:
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Features of RISC Processors:
8
Features of CISC Processors:
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8086 Architecture :
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8086 Architecture :
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8086 Architecture :
• Segment register:
BIU has 4 segment buses, i.e. CS, DS, SS& ES. It holds the addresses of
instructions and data in memory, which are used by the processor to
access memory locations. It also contains 1 pointer register IP, which
holds the address of the next instruction to executed by the EU.
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Special functions of general purpose register
AX & DX registers:
In 8 bit multiplication, one of the operands must be in AL. The
other operand can be a byte in memory location or in another 8
bit register. The resulting 16 bit product is stored in AX, with AH
storing the MS byte.
In 16 bit multiplication, one of the operands must be in AX.
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Special functions of general purpose register
BX register :
CX register :
In Loop Instructions, CX register will be always used as the implied
counter. In I/O instructions, the 8086 receives into or sends out data
from AX or AL depending as a word or byte operation.
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Segment register:
• Segment register:
BIU has 4 segment buses, i.e. CS, DS, SS& ES. It holds the addresses of
instructions and data in memory, which are used by the processor to
access memory locations. It also contains 1 pointer register IP, which holds
the address of the next instruction to executed by the EU.
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Flag Register and Functions of 8086
Flags
Flag Register contains a group of status bits called flags that
indicate the status of the CPU or the result of arithmetic operations.
There are two types of flags:
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Flag Register and Functions of 8086
Flags
• Nine individual bits of the status register are used as control flags (3 of
them) and status flags (6 of them).The remaining 7 are not used.
• A flag can only take on the values 0 and 1. We say a flag is set if it has
the value 1.The status flags are used to record specific characteristics
of arithmetic and of logical instructions.
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Structure of Flag Register
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Flag Register and Functions of 8086
Flags
• Control Flags: There are three control flags
• The Direction Flag (D): Affects the direction of moving data blocks by such
instructions as MOVS, CMPS and SCAS. The flag values are 0 = up and 1 =
down and can be set/reset by the STD (set D) and CLD (clear D) instructions.
• The Interrupt Flag (I): Dictates whether or not system interrupts can occur.
Interrupts are actions initiated by hardware block such as input devices that
will interrupt the normal execution of programs. The flag values are 0 =
disable interrupts or 1 = enable interrupts and can be manipulated by the
CLI (clear I) and STI (set I) instructions.
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Flag Register and Functions of 8086
Flags
• The Trap Flag (T): Determines whether or not the CPU is halted after the
execution of each instruction. When this flag is set (i.e. = 1), the
programmer can single step through his program to debug any errors.
When this flag = 0 this feature is off. This flag can be set by the INT 3
instruction.
• Status Flags: There are six status flags
• The Carry Flag (C): This flag is set when the result of an unsigned
arithmetic operation is too large to fit in the destination register. This
happens when there is an end carry in an addition operation or there an
end borrows in a subtraction operation. A value of 1 = carry and 0 = no
carry.
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Flag Register and Functions of 8086
Flags
• The Overflow Flag (O): This flag is set when the result of a signed
arithmetic operation is too large to fit in the destination register (i.e. when
an overflow occurs). Overflow can occur when adding two numbers with
the same sign (i.e. both positive or both negative). A value of 1 = overflow
and 0 = no overflow.
• The Sign Flag (S): This flag is set when the result of an arithmetic or logic
operation is negative. This flag is a copy of the MSB of the result (i.e. the
sign bit). A value of 1 means negative and 0 = positive.
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Flag Register and Functions of 8086
Flags
• The Zero Flag (Z): This flag is set when the result of an arithmetic or logic
operation is equal to zero. A value of 1 means the result is zero and a value
of 0 means the result is not zero.
• The Auxiliary Carry Flag (A): This flag is set when an operation causes a
carry from bit 3 to bit 4 (or a borrow from bit 4 to bit 3) of an operand. A
value of 1 = carry and 0 = no carry.
• The Parity Flag (P): This flags reflects the number of 1s in the result of an
operation. If the number of 1s is even its value = 1 and if the number of 1s is
odd then its value = 0.
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Addressing Modes of 8086
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Addressing Modes of 8086
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Addressing Modes of 8086
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Addressing Modes of 8086
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Addressing Modes of 8086
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Addressing Modes of 8086
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Addressing Modes of 8086
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Addressing Modes of 8086
••
Based indexed addressing mode:
• Intersegment
– Intersegment direct
– Intersegment indirect
• Intrasegment
– Intrasegment direct
– Intrasegment indirect
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Addressing Modes of 8086
• Intersegment direct:
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Addressing Modes of 8086
Intersegment indirect:
In this mode, the address to which the control is to be transferred lies in a
different segment and it is passed to the instruction indirectly, i.e. contents
of a memory block containing four bytes, i.e. IP(LSB), IP(MSB), CS(LSB) and
CS(MSB) sequentially. The starting address of the memory block may be
referred using any of the addressing modes, except immediate mode.
Example: JMP [2000H].
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Addressing Modes of 8086
In this mode, the address to which the control is to be transferred lies in the
same segment in which the control transfers instruction lies and appears
directly in the instruction as an immediate displacement value. In this
addressing mode, the displacement is computed relative to the content of
the instruction pointer.
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Addressing Modes of 8086
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Addressing Modes of 8086
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INSTRUCTION SET OF 8086
• String instructions
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Data Transfer
instructions
MOV instruction
• It is a general purpose instruction to transfer byte or word from
register to register, memory to register, register to memory or with
immediate addressing.
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Data Transfer
instructions
General Form:
• MOV destination, source
• Here the source and destination needs to be of the same size, that
is both 8 bit or both 16 bit.
• MOV instruction does not affect any flags.
Example:-
•
• MOV BX, load the immediate number 00F2H in
00F2H; BX register
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Data Transfer
instructions
•MOV [589H], BX; Copy the 16 bit content of BX register on to
the memory location, which at a
displacement of 589H from the data segment
base.
• MOV DS, CX; Move the content of CX to DS
PUSH instruction
• The PUSH instruction decrements the stack pointer by two and
copies the word from source to the location where stack pointer
now points. Here the source must of word size data. Source can be
a general purpose register, segment register or a memory location.
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Data Transfer
instructions
The PUSH instruction first pushes the most significant byte to sp-1, then
the least significant to the sp-2.
Push instruction does not affect any flags.
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Data Transfer
instructions
Example:-
• PUSH CX ; Decrements SP by 2, copy content of CX to the
stack (figure shows execution of this
• PUSH DS instruction)
; Decrement SP by 2 and copy DS to stack
• POP instruction
The POP instruction copies a word from the stack location pointed by
the stack pointer to the destination. The destination can be a
General purpose register, a segment register or a memory location.
Here after the content is copied the stack pointer is automatically
incremented by two.
• The execution pattern is similar to that of the PUSH instruction.
Example:
• POP CX ; Copy a word from the top of the stack to CX and
increment SP by 2.
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Data Transfer
instructions
• IN & OUT instructions
• The IN instruction will copy data from a port to the accumulator. If 8
bit is read the data will go to AL and if 16 bit then to AX. Similarly
OUT instruction is used to copy data from accumulator to an
output port.
• Both IN and OUT instructions can be done using direct and indirect
addressing modes.
Example:
• IN AL, 0F8H; Copy a byte from the port 0F8H to AL
• MOV DX, 30F8H;Copy port address in DX
• IN AL, DX; Move 8 bit data from 30F8H port
• IN AX, DX; Move 16 bit data from 30F8H port
• OUT 047H, AL; Copy contents of AL to 8 bit port 047H
• MOV DX, 30F8H;Copy port address in DX
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Data Transfer
instructions
XCHG instruction
• The XCHG instruction exchanges contents of the destination and
source. Here destination and source can be register and register or
register and memory location, but XCHG cannot interchange the
value of 2 memory locations.
General Format
• XCHG Destination, Source
Example:
• XCHG BX, CX; exchange word in CX with the word in BX
• XCHG AL, CL; exchange byte in CL with the byte in AL
• XCHG AX, SUM[BX];here physical address, which is
DS+SUM+[BX]. The content at physical
address and the content of AX are
interchanged.
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Arithmetic Instructions: ADD, ADC, INC, AAA,
DAA
Mnemonic Meaning Format Operation Flags
affected
ADD Addition ADD D,S (S)+(D) (D) ALL
carry
(CF)
ADC Add with ADC D,S (S)+(D)+(CF) (D) ALL
carry carry (CF)
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Arithmetic Instructions–SUB, SBB, DEC, AAS, DAS,
NEG
Mnemonic Meaning Format Operation Flags
affected
SUB Subtract SUB D,S (D) - (S) (D) All
Borrow
(CF)
SBB Subtract SBB D,S (D) - (S) - (CF) (D) All
with
borrow
DEC Decrement DEC D (D) - 1 All but CF
by one (D)
NEG Negate NEG D All
DAS Decimal DAS Convert the result in AL to All
adjust for packed decimal format
subtraction
AAS ASCII AAS (AL) difference CY,AC
adjust for (AH) dec by 1 if borrow
subtraction
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Multiplication and
Division
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Multiplication and Division
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Logical Instructions
AND instruction
• This instruction logically ANDs each bit of the source byte/word
with the corresponding bit in the destination and stores the result
in destination. The source can be an immediate number, register or
memory location, register can be a register or memory location.
• The CF and OF flags are both made zero, PF, ZF, SF are affected by
the operation and AF is undefined.
• General Format:
• AND Destination, Source
Example:
• AND BL, AL ;suppose BL=1000 0110 and AL = 1100 1010
then
• AND CX, AX ;CX after
<= the operation
CX AND AX BL would be BL= 1000 0010.
• AND CL, 08 ;CL<= CL AND (0000
1000) 50
Logical Instructions
OR instruction
• This instruction logically ORs each bit of the source byte/word with
the corresponding bit in the destination and stores the result in
destination. The source can be an immediate number, register or
memory location, register can be a register or memory location.
• The CF and OF flags are both made zero, PF, ZF, SF are affected by
the operation and AF is undefined.
• General Format:
• OR Destination, Source
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Logical Instructions
Example:
• OR BL, AL; suppose BL=1000 0110 and AL = 1100 1010 then
after the operation BL would be BL= 1100 1110.
• OR CX, AX;CX <= CX AND AX
• OR CL, 08;CL<= CL AND (0000 1000)
NOT instruction
• The NOT instruction complements (inverts) the contents of an
operand register or a memory location, bit by bit. The examples are
as follows:
Example:
• NOT AX (BEFORE AX= (1011)2= (B) 16 AFTER EXECUTION AX=
(0100)2= (4)16).
• NOT [5000H]
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Logical Instructions
XOR instruction
• The XOR operation is again carried out in a similar way to the AND
and OR operation. The constraints on the operands are also similar.
The XOR operation gives a high output, when the 2 input bits are
dissimilar. Otherwise, the output is zero. The example instructions
are as follows:
Example:
• XOR AX,0098H
• XOR AX,BX
• XOR AX,[5000H]
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Logical Instructions
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Logical Instructions
SHL/SAL instruction
• Both the instruction shifts each bit to left, and places the MSB in CF and LSB
is made 0. The destination can be of byte size or of word size, also it can be
a register or a memory location. Number of shifts is indicated by the count.
• All flags are affected.
General Format:
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Logical Instructions
SHR instruction
• This instruction shifts each bit in the specified destination to the right and
0 is stored in the MSB position. The LSB is shifted into the carry flag. The
destination can be of byte size or of word size, also it can be a register or a
memory location. Number of shifts is indicated by the count.
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String Instruction
Basics
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String Instruction
Basics
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String Control
Instructions
1) MOVS/ MOVSB/ MOVSW
Dest string name, src string name
This instruction moves data byte or word from location in DS to
location in ES.
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String Control
Instructions
4) SCAS / SCASB / SCASW
Scan a string byte or string word.
Compares byte in AL or word in AX. String address is to be loaded
in DI.
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5. Program Execution TransferInstructions
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5. Program Execution TransferInstructions
CALL instruction
Near call
1. Direct Near CALL: The destination address is specified in
the instruction itself.
2. Indirect Near CALL: The destination address is
specified in any
16-bit register, except IP.
Far call
1. DirectFar CALL: The destination is specified in the
address
instruction itself. It will be in different Code Segment.
2. Indirect Far CALL: The destination address is specified in two
word memory locations pointed by a register.
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5. Program Execution TransferInstructions
JMP instruction
The processor jumps to the specified location rather than the
instruction after the JMP instruction.
RET
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5. Program Execution TransferInstructions
Conditional TransferInstructions
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5. Program Execution TransferInstructions
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5. Program Execution TransferInstructions
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5. Program Execution Transfer Instructions
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Interrupt Instructions
Hardware Interrupts:
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Interrupt Instructions
Software Interrupts
• INT : Interrupt program execution, call service procedure
• INTO : Interrupt program execution if OF=1
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High Level Language Interface Instructions
LEAVE: Leaveprocedure.
bounds.
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Processor Control
Instructions
I. Flag set/clear instructions
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Processor Control
Instructions
II. External Hardware synchronizationinstructions
WAIT: Wait (Do nothing) until signal on the test pin islow.
ASSUME
DB - Defined Byte.
DD - Defined Double
DQ - Word Defined Quad
DT - Word Define Ten
DW - Bytes Define Word
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Assembler Directives
ASSUME Directive-
The ASSUME directive is used to tell the assembler that the name of the
logical segment should be used for a specified segment. The 8086 works
directly with only 4 physical segments: a Code segment, a data segment, a
stack segment, and an extra segment.
Example:
ASUME CS:CODE ;This tells the assembler that the logical segment named
CODE contains the instruction statements for the program and should be
treated as a code segment.
ASSUME DS:DATA ;This tells the assembler that for any instruction which
refers to a data in the data segment, data will found in the logical segment
DATA.
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Assembler Directives
DB - DB directive is used to declare a byte- type variable store a byte
or to
in memory location.
Example:
3. TEMP DB 100 DUP(?) ;Set 100 bytes of storage in memory and give it the
name as TEMP, but leave the 100 bytes uninitialized. Program instructions
will load values into these locations.
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Assembler Directives
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Assembler Directives
Example:
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Assembler Directives
- End Program
END
ENDP - End Procedure
ENDS - End Segment
EQU - Equate
EVEN
- Align on Even Memory Address
EXTRN
-
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Assembler Directives
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Assembler Directives
GROUP - Used to tell the assembler to group the logical statements
named after the directive into one logical group segment, allowing the
contents of all the segments to be accessed from the same group
segment base.
INCLUDE - Used to tell the assembler to insert a block of source code
from the named file into the current source module.
LABEL- Used to give a name to the current value in the location
counter.
NAME- Used to give a specific name to each assembly module
when programs consisting of several modules are written.
ORG- The location counter is set to 0000 when the assembler starts
reading a segment. The ORG directive allows setting a desired value at any
point in the program.
E.g.: ORG 2000H
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Assembler Directives
PUBLIC- Used to tell the assembler that a specified name or label will be
accessed from other modules.
SEGMENT- Used to indicate the start of a logical segment.
84
Write an assembly language program to find the factorial of
given number using 8086 microprocessors.
DATA SEGMENT
FIRST DW 03H
SEC DW 01H
DATA ENDS
CODE SEGMENT
ASSUME
CS:CODE,DS:DATA
START MOV AX,DATA
: MOV DS,AX
MOV AX,SEC
MOV
CX,FIRST
L1: MUL CX
DEC CX
JCXZ L2
JMP
L1
L2: INT 3H
CODE ENDS
END START
85
Write an assembly language program to find the sum of
squares using 8086 microprocessors.
DATA SEGMENT
NUM DW 5H
RES DW ?
DATA ENDS
CODE SEGMENT
ASSUME CS: CODE, DS: DATA
START: MOV
AX,DATA
MOV DS,AX
MOV
CX,NUM
MOV BX,00
L1: MOV AX,CX
MUL CX
ADD BX,AX
DEC CX
JNZ L1
CODE
MOVENDS
RES,BX INT
END START3H
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Procedures and Macros
Procedures:
• While writing programs, it may be the case that a particular sequence of
instructions is used several times. To avoid writing the sequence of
instructions again and again in the program, the same sequence can be
written as a separate subprogram called a procedure.
Defining Procedures:
• Assembler provides PROC and ENDP directives in order to define
procedures. The directive PROC indicates beginning of a procedure.
Its general form is:
Procedure_name PROC [NEAR|FAR]
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Procedures and Macros
MACROS:
When the repeated group of instruction is too short or not suitable to be
implemented as a procedure, we use a MACRO. A macro is a group of
instructions to which a name is given. Each time a macro is called in a
program, the assembler will replace the macro name with the group of
instructions.
Defining MACROS:
Before using macros, we have to define them. MACRO directive
informs the assembler the beginning of a macro. The general form is:
Macro_name MACRO argument1, argument2, …Arguments are optional.
ENDM informs the assembler the end of the macro. Its general form is :
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ENDM
Procedures and Macros
Procedures Macros
Accessed by CALL and RET mechanism Accessed by name given to macro
during program execution when
defined during assembly
Machine code for instructions only put Machine code generated
in memory once for instructions
each time called
Parameters are passed in registers, Parameters passed as part of statement
memory locations or stack which calls macro
Procedures uses stack Macro does not utilize stack
A procedure can be defined anywhere in A macro can be defined anywhere in
program using the directives PROC program using the directives MACRO
and ENDP and ENDM
Procedures takes huge memory for Length of code is very huge if macro’s are
CALL(3 bytes each time CALL is called for more number of times
used) instruction
90
Minimum mode operation in 8086:
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Minimum mode operation in 8086:
In a minimum mode 8086 system, the microprocessor 8086 is operated in
minimum mode by strapping its MN/MX pin to logic 1.
In this mode, all the control signals are given out by the microprocessor
chip itself. There is a single microprocessor in the minimum mode system.
The remaining components in the system are latches, transceivers, clock
generator, memory and I/O devices. Some type of chip selection logic may
be required for selecting memory or I/O devices, depending upon the
address map of the system.
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Minimum mode operation in 8086:
Transceivers are the bidirectional buffers and sometimes they are called as
data amplifiers. They are required to separate the valid data from the time
multiplexed address/data signals.
The DEN signal indicates the direction of data, i.e. from or to the processor.
The system contains memory for the monitor and users program storage.
Usually, EPROM is used for monitor storage, while RAM for users
program
storage. A system may contain I/O devices.
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Maximum mode operation in 8086:
In the maximum mode, the 8086 is operated by strapping the MN/MX
pin to ground.
In this mode, the processor derives the status signal S2, S1, S0.
Another chip called bus controller derives the control signal using this
status information.
In the maximum mode, there may be more than one
microprocessor in the system configuration.
The components in the system are same as in the minimum
mode system.
The basic function of the bus controller chip IC8288 is to contro
signals
derive like RD and WR (for memory and I/O devices), DEN, DT/R, ALE letc.
using the information by the processor on the status lines.
The bus controller chip has input lines S2, S1, S0 and CLK. These inputs to
8288 are driven by CPU.
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Maximum mode operation in 8086:
95
Maximum mode operation in 8086:
• It derives the outputs ALE, DEN, DT/R, MRDC, MWTC, AMWC, IORC, IOWC
and AIOWC. The AEN, IOB and CEN pins are especially useful
for
multiprocessor systems.
• AEN and IOB are generally grounded. CEN pin is usually tied to +5V. The
significance of the MCE/PDEN output depends upon the status of the IOB
pin.
• If IOB is grounded, it acts as master cascade enable to control cascade
8259A, else it acts as peripheral data enable used in the multiple bus
configurations.
140
Maximum mode operation in 8086:
• INTA pin used to issue two interrupt acknowledge pulses to the interrupt
controller or to an interrupting device.
• IORC, IOWC are I/O read and I/O write command
command signals
respectively.
• These signals enable an IO interface to read or write the data from or to the
address port.
• The MRDC, MWTC are memory read command and memory write
command signals respectively and may be used as memory read or write
signals.
140
Maximum mode operation in 8086:
98
Maximum mode operation in 8086:
• R0, S1, S2 are set at the beginning of bus cycle.8288 bus controller will
output a pulse as on the ALE and apply a required signal to its DT / R pin
during T1.
• In T2, 8288 will set DEN=1 thus enabling transceivers, and for an input it will
activate MRDC or IORC. These signals are activated until T4. For an output,
the AMWC or AIOWC is activated from T2 to T4 and MWTC or IOWC is
activated from T3 to T4.
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Write Cycle Timing Diagram for Minimum
Mode
100
Bus Request and Bus Grant Timings in Minimum Mode
System
of 8086
101
Memory Read Timing Diagram in Maximum Mode of
8086
102
Memory Write Timing in Maximum mode of 8086
103
UNIT II
PROGRAMMING WITH 8086
MICROPROCESSOR
104
Assembly Language Programming
105
Assembly Language Programming
Assembly Language:
Alphanumeric equivalent of machine language Mnemonics more human-
oriented than 1’s and 0’s
Assembler:
Computer program that transliterates (one-to-one mapping) assembly
to machine language Computer’s native language is machine/assembly
language
106
Why Assembly Language Programming
107
Basic elements of 8086 assembly programming
language
160
8086 assembly programming language instructions
• Like we know instruction are the lines of a program that means an action
for the computer to execute.
In 8086, a normal instruction is made by an operation code and
sometimes
operands.
Structure:
Operation Code [Operand1 [, Operand2]]
• Operations
• The operation is usually logic or arithmetic, but we can also find
some
special operation like the Jump (JMP) operation.
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8086 assembly programming language instructions
• Operands
• Operands are the parameters of the operation in the instruction. They can
be use in 3 way:
• Immediate
• This means a direct access of a variable that have been declared in the
program.
• Register
• Here we use the content of a register to be a parameter.
• Memory
• Here we access to the content of a specific part of the memory using a
pointer
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SYNTAX OF 8086/8088 ASSEMBLY
LANGUAGE
• The language is not case sensitive.
• There may be only one statement per line. A statement may start in any
column.
• A statement is either an instruction, which the assembler translates into
machine code, or an assembler directive (pseudo-op), which instructs the
assembler to perform some specific task.
• Syntax of a statement:
{name} mnemonic {operand(s)} {; comment}
• The curly brackets indicate those items that are not present or are optional
in some statements.
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SYNTAX OF 8086/8088 ASSEMBLY
LANGUAGE
• The name field is used for instruction labels, procedure names, segment
names, macro names, names of variables, and names of constants.
• MASM 6.1 accepts identifier names up to 247 characters long. All
characters are significant, whereas under MASM 5.1, names are significant
to 31 characters only. Names may consist of letters, digits, and the
following 6 special characters: ? . @ _ $ % .If a period is used; it must be
the first character. Names may not begin with a digit.
• Instruction mnemonics, directive mnemonics, register names, operator
names and other words are reserved.
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Stac
k
• A stack is a container of objects that are inserted and removed according to
the last-in first-out (LIFO) principle. In the pushdown stacks only two
operations are allowed: push the item into the stack, and pop the item out
of the stack.
• A stack is a container of objects that are inserted and removed according to
the last-in first-out (LIFO) principle. In the pushdown stacks only two
operations are allowed: push the item into the stack, and pop the item out
of the stack. A stack is a limited access data structure - elements can be
added and removed from the stack only at the top. push adds an item to the
top of the stack, pop removes the item from the top.
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Stac
k
• A helpful analogy is to think of a stack of books; you can remove only the
top book, also you can add a new book on the top. A stack is a
recursive
data structure. Here is a structural definition of a Stack:
• A stack is either empty or it consists of a top and the rest which is a stack;
114
Applications
Mainly the following three basic operations are performed in the stack:
• Push: Adds an item in the stack. If the stack is full, then it is said to be an
Overflow condition.
• Pop: Removes an item from the stack. The items are popped in the
reversed order in which they are pushed. If the stack is empty, then it is
said to be an Underflow condition.
116
Stack Structure
117
Stack Structure
• If the stack top points to a memory location 52050H, it means that the
location 52050H is already occupied with the previously pushed data. The
next 16 bit push operation will decrement the stack pointer by two, so
that it will point to the new stack-top 5204EH and the decremented
contents of SP will be 204EH. This location will now be occupied by the
recently pushed data.
• Thus for a selected value of SS, the maximum value of SP=FFFFH and the
segment can have maximum of 64K locations. If the SP starts with an
initial value of FFFFH, it will be decremented by two whenever a 16-bit
data is pushed onto the stack.
118
Stack Structure
• After successive push operations, when the stack pointer contains 0000H,
any attempt to further push the data to the stack will result in stack
overflow.
• After a procedure is called using the CALL instruction, the IP is
incremented to the next instruction. Then the contents of IP, CS and flag
register are pushed automatically to the stack. The control is then
transferred to the specified address in the CALL instruction i.e. starting
address of the procedure. Then the procedure is executed.
119
Interrupt
s
Definition:
120
Interrupt
s
Need for Interrupt:
Interrupts are particularly useful when interfacing I/O devices that provide
or require data at relatively low data transfer rate.
Interrupt is a mechanism that allows hardware or software to suspend
normal execution on microprocessor in order to switch to interrupt service
routine for hardware / software. Interrupt can also describe as
asynchronous electrical signal that sent to a microprocessor in order to
stop current execution and switch to the execution signaled (depends on
priority). Whether an interrupt is prioritized or not depends on the
interrupt flag register which controlled by priority / programmable
interrupt
121
Interrupt Cycle of 8086
122
Interrupt Cycle of 8086
123
Hardware Interrupts
They are: (A) NMI (Non Maskable Interrupt) – It is a single pin non maskable
hardware interrupt which cannot be disabled. It is the highest priority
interrupt in 8086 microprocessor. After its execution, this interrupt
generates a TYPE 2 interrupt. IP is loaded from word location 00008 H and
CS is loaded from the word location 0000A H.
124
Hardware Interrupts
125
Software Interrupts
These are instructions that are inserted within the program to generate
interrupts.
126
Software Interrupts
127
Interrupt Vector Table (IVT) on
8086
128
Non Maskable Interrupt
129
Non Maskable Interrupt
130
Maskable Interrupt
• The 8086 has two hardware interrupt pins, i.e. ... NMI is a non-maskable
interrupt and INTR is a maskable interrupt having lower priority. One
moreinterrupt pin associated is INTA called interrupt acknowledge.
• The INTR is a maskable interrupt because the microprocessor will be
interrupted only if interrupts are enabled using set interrupt flag
instruction. It should not be enabled using clear interrupt Flag instruction.
• The INTR interrupt is activated by an I/O port. If the interrupt is enabled
and NMI is disabled, then the microprocessor first completes the current
execution and sends ‘0’ on INTA pin twice.
131
Maskable Interrupt
• The first ‘0’ means INTA informs the external device to get ready and
during the second ‘0’ the microprocessor receives the 8 bit, say X, from
the programmable interrupt controller.
• These actions are taken by the microprocessor −
• First completes the current instruction.
• Activates INTA output and receives the interrupt type, say X.
• Flag register value, CS value of the return address and IP value of the
return address are pushed on to the stack.
• IP value is loaded from the contents of word location X × 4
• CS is loaded from the contents of the next word location.
• Interrupt flag and trap flag is reset to 0
132
UNIT III
INTERFACING WITH
8086/88
133
Memory interfacing to 8086 (Static RAM and EPROM)
• Interface two 4Kx8 EPROMS and two 4Kx8 RAM chips with 8086.
select suitable maps.
134
Memory interfacing to 8086 (Static RAM and EPROM)
135
Memory interfacing to 8086 (Static RAM and EPROM)
136
8255- PROGRAMMABLE PERIPHERAL INTERFACE
• Port A(8bit)
84 191
8255- PROGRAMMABLE PERIPHERAL INTERFACE
Block
Diagram
The internal data bus and Outer pins D0-D7 pins are connected
in
internally.
86 193
8255- PROGRAMMABLE PERIPHERAL INTERFACE
Read/Write Control Logic
This is getting the input signals from control bus and Address
Control signal are RD andWR. Bus.
87 194
8255- PROGRAMMABLE PERIPHERAL INTERFACE
PORT A:
This is a 8-bit buffered I/O latch.
It can be programmed by mode 0 , mode 1, mode 2 .
PORT B:
This is a 8-bit buffer I/O latch.
It can be programmed by mode 0 and mode 1.
PORTC:
PC7-PC4: Upper nibble of port C lines. They may act as either output
latches or input buffers lines. This port also can be used for
generation of handshake lines in mode 1 or mode 2.
PC3-PC0: These are the lower port C lines, other details are the same
as PC7-PC4 lines.
PB0-PB7: These are the eight port B lines which are used lines
as latched output or buffered input lines in the same
way as port A.
91 199
8255- PROGRAMMABLE PERIPHERAL INTERFACE
144
8255- PROGRAMMABLE PERIPHERAL INTERFACE
Various modes of 8255:
These are two basic modes of operation of 8255. I/O mode and Bit Set-Reset
mode (BSR).
In I/O Mode:
The 8255 ports work as programmable I/O ports, while in BSR mode only port
C (PC0-PC7) can be used to set or reset its individual port bits.
Under the I/O mode of operation, further there are three modes of operation
of 8255, so as to support different types of applications, mode 0, mode 1 and
mode 2.
145
8255- PROGRAMMABLE PERIPHERAL INTERFACE
Mode 0 (Basic I/O mode): This mode is also called as basic input/output
Mode. This mode provides simple input and output capabilities using each
of the three ports. Data can be simply read from and written to the input
and output ports respectively, after appropriate initialization.
146
8255- PROGRAMMABLE PERIPHERAL INTERFACE
Mode 1: (Strobed input/output mode) in this mode the handshaking
control the input and output action of the specified port. Port C lines PC0-
PC2, provide strobe or handshake lines for port B.
This group which includes port B and PC0-PC2 is called as group B for
Strobed data input/output. Port C lines PC3-PC5 provides strobe lines for port
A.
This group including port A and PC3-PC5 from group A. Thus port C is
147
8255- PROGRAMMABLE PERIPHERAL INTERFACE
148
8255- PROGRAMMABLE PERIPHERAL INTERFACE
BSR Mode:
In this mode any of the 8-bits of port C can be set or reset depending on D0
of the control word. The bit to be set or reset is selected by bit select flags
149
8255 interfacing with 8086:
150
Stepper motor
Stepper motor is often used in computer systems. Normally DC and
AC
motors move smoothly in a circular fashion.
152
Stepper motor
DATA SEGMENT
PORTC EQU 8004H
CNTLPRT EQU
8006H DELAY EQU
14705
DATA ENDS
CODE SEGMENT
ASSUME CS: MOV
STAR CODE,AX,
DS:
T:
DATA DATA MOV
DS, AX MOV
AL, 80H
MOV DX,
CNTLPORT OUT
DX, AL
BACK: MOV AL, 33H
MOV DX,
PORTC OUT
SELF: DX, AL
ROR AL, 1
MOV CX,
CODE DELAY LOOP
ENDS END SELF
START DELAY LOOP
FOR 25Ms
JMP BACK
153
Digital to analog converter interfacing
154
Digital to analog converter interfacing
155
Digital to analog converter interfacing
converter
n ci
156
Pin Diagram of AD7523
• The supply range extends from +5V to +15V , while Vref may be anywhere
between -10V to +10V. The maximum analog output voltage will be +10V,
when all the digital inputs are at logic high state. Usually a Zener is
connected between OUT1 and OUT2 to save the DAC from negative
transients.
• An operational amplifier is used as a current to voltage converter at the
output of AD 7523 to convert the current output of AD7523 to a
proportional output voltage.
• It also offers additional drive capability to the DAC output. An external
feedback resistor acts to control the gain. One may not connect any
external feedback resistor, if no gain control is required.
157
Analog to Digital Converter Interfacing
159
Timing Diagram Of ADC
0808.
160
Interfacing ADC0808 with 8086
161
Programmable interrupt controller 8259A
162
Features of 8259 PIC microprocessor
165
Pin Description of 8086
166
keyboard /display controller8279
The Keyboard can be interfaced either in the interrupt or the polled mode.
In the Interrupt mode, the processor is requested service only if any key is
pressed, otherwise the CPU will continue with its main task.
In the Polled mode, the CPU periodically reads an internal flag of 8279 to
check whether any key is pressed or not with key pressure.
167
Architecture and Description
168
Architecture and Description….
• This unit controls the flow of data through the microprocessor. It is enabled
only when D is low. Its data buffer interfaces the external bus of the system
with the internal bus of the microprocessor. The pins A0, RD, and WR are
used for command, status or data read/write operations.
• Control and Timing Register and Timing Control
• This unit contains registers to store the keyboard, display modes, and
other operations as programmed by the CPU. The timing and control unit
handles the timings for the operation of the circuit.
169
8279 − Pin Description
170
Programmable communication interface 8251
USART
• Most of devices are parallel in nature. These devices transfer data
simultaneously on data lines. But parallel data transfer process is very
complicated and expensive. Hence in some situations the serial I/O mode
is used where one bit is transferred over a single line at a time. In this type
of transmission parallel word is converted into a stream of serial bits which
is known as parallel to serial conversion. The rate of transmission in serial
mode is BAUD, i.e., bits per second. The serial data transmission involves
starting, end of transmission, error verification bits along with the data.
171
Block Diagram of Serial I/O Interface
172
INTRODUCTION SERIAL COMMUNICATION
173
Introduction Serial Communication
This method is used when data transfer rates are very low or the data must
be transferred over long distances and also where the cost of cable and
synchronization difficulties makes parallel communication impractical.
174
8251a-usart-universal Synchronous/Asynchronous
Receiver/Transmitter
• A USART is also called a programmable communications interface
(PCI). When information is to be sent by 8086 over long distances, it is
• economical to send it on a single line. The 8086 has to convert parallel
data to serial data and then output it. Thus lot of microprocessor time is
required for such a conversion.
• Similarly, if 8086 receives serial data over long distances, the 8086 has to
internally convert this into parallel data before processing it. Again, lot of
time is required for such a conversion. The 8086 can delegate the job of
conversion from serial to parallel and vice versa to the 8251A USART
used in thesystem.
175
8251A-USART-Universal Synchronous/Asynchronous
Receiver/Transmitter
176
Features
177
Architecture 8251A
240
Pin
Diagram
179
8251A USART Interfacing With 8086
180
Recommended Standard -232c (RS-232C)
• RS-232 was first introduced in 1962 by the Radio Sector of the Electronic
Industries Association EIA. RS-232 (Recommended standard-232) is a
standard interface approved by the Electronic Industries Association (EIA)
for connecting serial devices. In other words, RS-232 is a long-established
standard that describes the physical interface and protocol for relatively
low-speed serial data communication between computers and related
devices. An industry trade group, the Electronic Industries Association
(EIA), defined it originally for teletypewriter devices.
181
Recommended Standard -232c (RS-232C)
• In 1987, the EIA released a new version of the standard and changed the
name to EIA-232-D. Many people, however, still refer to the standard as
RS- 232C, or just RS-232. RS-232 is the interface that your computer uses
to talk to and exchange data with your modem and other serial devices.
The serial ports on most computers use a subset of the RS- 232C standard.
182
Recommended Standard -232c (RS-232C)
183
Need For DMA
• Direct memory access (DMA) is a feature of modern computer systems that
allows certain hardware subsystems to read/write data to/from memory
without microprocessor intervention, allowing the processor to do other
work.
• Used in disk controllers, video/sound cards etc, or between memory
locations.
• Typically, the CPU initiates DMA transfer, does other operations while the
transfer is in progress, and receives an interrupt from the DMA controller
once the operation is complete.
• Can create cache coherency problems (the data in the cache may be
different from the data in the external memory after DMA)
184
DMA Data Transfer
Method
185
DMA Data Transfer
Method
• The I/O device asserts the appropriate DRQ signal for the channel.
• The DMA controller will enable appropriate channel, and ask the CPU to
release the bus so that the DMA may use the bus. The DMA requests the
bus by asserting the HOLD signal which goes to the CPU.
• The CPU detects the HOLD signal, and will complete executing the current
instruction. Now all of the signals normally generated by the CPU are placed
in a tri-stated condition (neither high or low) and then the CPU asserts the
HLDA signal which tells the DMA controller that it is now in charge of the
bus.
• The CPU may have to wait (hold cycles).
186
DMA Data Transfer
Method
• DMA activates its -MEMR, -MEMW, -IOR, -IOW output signals, and the
address outputs from the DMA are set to the target address, which will be
used to direct the byte that is about to transferred to a specific memory
location.
• The DMA will then let the device that requested the DMA transfer know
that the transfer is commencing by asserting the -DACK signal.
• The peripheral places the byte to be transferred on the bus Data lines.
• Once the data has been transferred, The DMA will de-assert the - DACK2
signal, so that the FDC knows it must stop placing data on the bus.
187
DMA Data Transfer
Method
• The DMA will now check to see if any of the other DMA channels have any
work to do. If none of the channels have their DRQ lines asserted, the DMA
controller has completed its work and will now tri-state the -MEMR, -
MEMW, -IOR, -IOW and address signals.
• Finally, the DMA will de-assert the HOLD signal. The CPU sees this, and de-
asserts the HOLDA signal. Now the CPU resumes control of the buses and
address lines, and it resumes executing instructions and accessing main
memory and the peripherals.
250
Features of 8257
• Here is a list of some of the prominent features of 8257 −
• It has four channels which can be used over four I/O devices.
• Each channel has 16-bit address and 14-bit counter.
• Each channel can transfer data up to 64kb.
• Each channel can be programmed independently.
• Each channel can perform read transfer, write transfer and verify
transfer operations.
• It generates MARK signal to the peripheral device that 128 bytes
have
• been transferred.
• It requires a single phase clock.
• Its frequency ranges from 250Hz to 3MHz.
189
Pin diagram of 8257
190
Block Diagram of 8257
191
Terminal Count
Register:
270
Mode Set Register:
193
Status
Register:
194
195
UNIT IV
8051
MICROCONTROLLER
196
Disadvantages of Microprocessor
197
Advantages of Microcontroller based System
⦿ Microcontroller
199
Block
Diagram
External
interrupts On-chip Timer/Counter
Bus Serial
4 I/O Ports Port
OSC Control
P0 P1 P2 P3 TxD RxD
Address/Data
200
Internal Block Diagram of 8051
280
Pin Diagram of 8051
202
Basic circuit of 8051
203
PORT 0-
Description
204
PORT 1 -
Description
205
PORT 2 -Description
– Or high byte of
the address bus for
external memory
design
206
PORT 3 - Description
P3.4 T0 Timer 0
P3.5 T1 Timer 1
207
8051 addressing
modes
208
Immediate addressing mode
MOV DPTR,#4532H
209
Register addressing
mode
Register mode involves the use of registers to hold the data
addressing
to be manipulated.
Ex :-
210
Direct addressing
mode
In direct addressing mode, the data is in a RAM memory location
whose address is known, and this address is given as a
part of the
Contrast thisinstruction.
with the immediate addressing mode in the operand
which
itself is provided with the instruction.
Ex:- MOV R0,40H //save content of RAM location 40h into
R0.
MOV 56H,A // save content of A RAM location
in 56H
211
Register indirect addressing mode
212
Indexed addressing
mode
Indexed addressing mode is widely used in accessing data elements of
look-
up table entries located in the program ROM space of the 8051.
213
Instruction set of 8051
214
Arithmetic instructions
215
Logical instructions
The logical instructions are the instructions which are used for performing
some operations like AND, OR, NOT, X- OR and etc., on the operands.
EX:
ANL A,Rn // AND register toaccumulator
ORL // OR register to accumulator
// Exclusive OR Reg toAcc
A,Rn
//Clear Accumulator
XRL A,Rn
// Complement Accumulator
CLR A
CPLA
216
Branch and Looping Instructions
These instructions are used for both branching as well as looping.
These instructions include conditional & unconditional jump or
loop
instructions.
EX:
JC // Jump if carry equal to one
JNC // Jump if carry equal to zero
JB // Jump if bit equal to one
JNB // Jump if bit equal to zero
JBC // Jump if bit equal to one and clearbit
217
Unconditional Jump Instructions
SJMP // Short
jump
LJMP // Long
jump
218
Writing “1” to Output Pin P1.X
Read Vcc
latch TB2
Load(L1) 2. output pin
is Vcc
1. write a 1 to thepin
1 P1.X
Internal D Q
CPU P1.X pin
bus 0 output
Write to Clk Q M1
1
latch
TB1
Read
pin
Writing “0” to Output Pin P1.X
Read Vcc
latch TB2
Load(L1) 2. output pin
1. write a 0 to thepin is ground
0 P1.X
Internal D Q
CPU P1.X pin
bus 1 output
Write to Clk Q M1
0
latch
TB1
Read
pin
Reading “High” at Input
Pin
Read Vcc 2.
latch MOVA,P1
TB2 external
1. write a 1 to the pin Load(L1 pin=High
MOV )
P1,#0FFH
1 1 P1.X pin
Internal CPUbus D Q
P1.X
0 M1
Write to Clk Q
latch
TB1
Read pin
3. Read pin=1 Readlatch=0
Write to latch=1
Reading “Low” at Input Pin
Read Vcc
latch 2.
TB2 MOVA,P1
1. write a 1 to external
Load(L1
thepin MOV ) pin=Low
TB1
Read pin
3. Read pin=1 Readlatch=0
Write to latch=1
A and B Registers
• B – address 0F0h
Add
Subtract
Increment
Decrement
Multiply
Divide
Decimal
adjust
Arithmetic Instructions
Mnemonic Description
ADD A, byte add A to byte, put result in A
ADDC A, byte add with carry
SUBB A, subtract withborrow
byte increment A
INC A increment byte in memory
INC byte increment data pointer
INC DPTR decrement
DEC A accumulator
DEC byte decrement byte
MUL AB multiply accumulator by b
DIV AB register divide accumulator by b
DA A register decimal adjust the
ADD
Instructions
add a, byte
addc a, byte
These instructions affect 3 bits in PSW:
C = 1 if result of add is greater than FF
AC = 1 if there is a carry out of bit 3
OV = 1 if there is a carry out of bit 7, but not from bit 6,or visa versa.
Increment and Decrement
INC A increment A
INC byte increment byte in memory
INC DPTR increment data pointer
DEC A decrement accumulator
DEC byte decrement byte
• CLR - clear
• RL – rotateleft
• RLC – rotate left through Carry
• RR – rotate right
• RRC – rotate right through Carry
• SWAP – swap accumulator
nibbles
UNIT V
8051
TIMERS/COUNTERS
229
TIMER/COUNTER
TMOD Address: 89 H
Timer/ Counter control logic:
Timer Mode-0:
In this mode, the timer is used as a 13-bit UP counter as follows.
The lower 5 bits of TLX and 8 bits of THX are used for the 13 bit count.
Upper 3 bits of TLX are ignored. When the counter rolls over from all 0's to
all 1's, TFX flag is set and an interrupt is generated.
Timer modes of operation
The input pulse is obtained from the previous stage. If TR1/0 bit is 1 and
Gate bit is 0, the counter continues counting up. If TR1/0 bit is 1 and Gate
bit is 1, then the operation of the counter is controlled by input. This mode
is useful to measure the width of a given pulse fed to input.
Timer Mode-
1:
This mode is similar to mode-0 except for the fact that the Timer
operates in 16-bit mode.
THX stores a constant value. In this mode when the timer overflows i.e. TLX
becomes FFH, it is fed with the value stored in THX. For example if we load THX
with 50H then the timer in mode 2 will count from 50H to FFH. After that 50H
is again reloaded. This mode is useful in applications like fixed time sampling
Control bits TR1 and TF1 are used by Timer-0 (higher 8 bits) (TH0) in Mode-3
while TR0 and TF0 are available to Timer-0 lower 8 bits(TL0).
Interrupts
– interrupts
– polling.
Interrupts
1. Reset
2. Timer 0 overflow
3. Timer 1 overflow
4. External Interrupt 0
5. External Interrupt 1
6. Serial Port events buffer full, buffer empty, etc)
Interrupt
Vectors
Each interrupt has a specific place in code memory where
program
execution (interrupt service routine) begins.
External Interrupt 0 : 0003h
Timer 0 overflow : 000Bh
External Interrupt 1 : 0013h
Timer 1 overflow 001Bh
:
Serial
: 0023h Note: that there
Timer 2 overflow(8052+) are only 8 memory
: 002bh locations between
vectors.
Interrupt Enable (IE)
register
All interrupt are disabled after reset
We can enable and disable them by
IE
Enabling an interrupt
by bit operation
Recommended in the middle of program
SETB EA SETB IE.7 ;Enable All
SETB ET0 ;Enable Timer0 over
SETB ET1 SETB IE.1 flow
SETB EX0 ;Enable Timer1 over
SETB IE.3
SETB EX1 flow
SETB ES SETB IE.0 ;Enable INT0
;Enable INT1
SETB IE.2 ;Enable Serial port
by mov instruction
Recommended in the SETB
first ofIE.4
program
• MOV IE, #10010110B
Disabling an interrupt
IP.7: reserved
IP.6: reserved
IP.5: timer 2 interrupt priority bit(8052
only)
IP.4: serial port interrupt priority
bit IP.3: timer 1 interrupt priority
bit IP.2: external interrupt 1
priority bit IP.1: timer 0 interrupt
priority bit IP.0: external interrupt
0 priority bit
SERIAL
COMMUNICATION
The serial port of 8051 is full duplex, i.e., it can transmit and receive
simultaneously.
The register SBUF is used to hold the data. The special function register
SBUF is physically two registers. One is, write-only and is used to hold data
to be transmitted out of the 8051 via TXD.
The other is, read-only and holds the received data from external sources
via RXD. Both mutually exclusive registers have the same address 099H.
8051 SERIAL DATA
COMMUNICATION
• A single microcontroller can serve several devices. There are two ways to
do that is interrupts or polling. In the interrupt method, whenever any
device needs its services, the device notifies the micro controller
interrupts whatever it is doing and serves the device.
• The program which is associated with the interrupt is called the
interrupt service routine (ISR) or Interrupt handler.
Each device has three sets of registers ─data buffer register(s), control
register(s) and status register
Device Addresses
Device control and status addresses and port address remains constant and
are not re-locatable in a program as the glue circuit (hardware) to accesses
these is fixed during the circuit design. There can be common addresses for
8051 SERIAL DATA COMMUNICATION AND PROGRAMMING
The processor, memory and devices are interfaced (glued) together using a
programmable circuit like GAL or FPGA. The circuit consists of the address
decoders as per the memory and device addresses allocated and the
needed latches multiplexers/ demultiplexers.
Device Addresses
There may be common addresses for control and status bits There can
be a control bits, which changes the function of a register at a device
address
Stepper Motor interacting with 8051
• Unipolar stepper motor generally has five or six wire, in which four wires
are one end of four stator coils, and other end of the all four coils is tied
together which represents fifth wire, this is called common wire.
• In Bipolar stepper motor there is just four wires coming out from two
sets of coils, means there are no common wire.
Stepper Motor interacting with 8051
• Stepper motor is made up of a stator and a rotator.