Embedded System

Embedded Computing System

Module1: Hardware Concepts -Application and characteristics of embedded
systems, Overview of Processors and hardware units in an embedded system,
General purpose processors,Microcontrollers:8051, Application- Specific Circuits
(ASICs), ASIP, FPGA,ARM-based System on a Chip(SoC), Network on Chip (NoC),
levels of hardware modeling, Verilog/VHDL, Sensors, A/D-D/A
converters,Actuators, Interfacing using RS-232,UART, USB, I2C, CAN bus,
Flexray, SRAM and DRAM, Flash memory.

Module2: Real-Time Operating Systems- Real-Time Task Scheduling: Some

important concepts, Types of real-time tasks and their characteristics, Task
scheduling, Clock-Driven scheduling, Hybrid schedulers,Event-Driven
scheduling, Earliest Deadline First (EDF) scheduling, Rate monotonic algorithm
(RMA).Commercial Real-time operating systems: Time services, Features of a
Real-time operating system, Unix-based Real-time operating systems, POSIX-RT,
A survey of contemporary Real- time operating systems,Microkernel based
systems, benchmarking real-time systems.

Module3: Embedded Application Development - UML 2.0, State charts, General

language characteristics,Hardware/Software Co-design, Hardware/software
partitioning, Testing embedded systems, Design for testability and Self-test.
 Books
 1. Frank Vahid and Tony Givargis, Embedded
Systems Design – A Unified Hardware
/Software Introduction , John Wiley, 2001
 2. David E.Simon, An Embedded Software
Primer, Pearson Education Asia, 1999
 What is embedded system
 An embedded system is a computer system
with a dedicated function within a larger
mechanical or electrical system, often with real-
time computing constraints.
 It is embedded as part of a complete device
often including hardware and mechanical parts.
 Embedded systems control many devices in
common use today. Ninety-eight percent of all
microprocessors are manufactured as
components of embedded systems.
An embedded system on a plug-in card with processor, memory,
power supply, and external interfaces
Embedded systems come in a variety of shapes
and sizes, from the largest multiple-rack data
storage or networking powerhouses to tiny
modules such as your personal MP3 player or
cellular handset. Following are some of the usual
characteristics of an embedded system:

 Contains a processing engine, such as a general-

purpose microprocessor
 Typically designed for a specific application or
purpose
 Includes a simple (or no) user interface, such as
an automotive engine ignition controller
 Often is resource-limited. For example, it might
Most commonly, embedded systems are resource-constrained
compared to the typical desktop PC.
Embedded systems often have limited memory, small or no hard-
drives, and sometimes no external network connectivity.
Frequently, the only user interface is a serial port and some LEDs.
These and other issues can present challenges to the embedded
system developer. With advancements in IOT, embedded
systems are getting much more complex.
Might have power limitations, such as a requirement to
operate from batteries
Not typically used as a general-purpose computing
platform
Generally has application software built in, not user-
selected
Chips with all intended application hardware and
software pre-integrated
Often is intended for applications without human
intervention
 Why we need to know about
Embedded system????
Do you know 70% of intelligent computing devices
are surrounding us?
One of the facts is our world will connect to more
than 50 billion devices by 2020.
Embedded System is also known as an
integrated system due to its combination of
hardware and software (also known as
Firmware).
 Embedded System VS General
Purpose System
Computing device like a microprocessor has
external peripherals (Real-time Clock, USB,
Ethernet, WiFi, Bluetooth etc.) connected to it
and are visible outside.
But an embedded device contains few or all the
peripherals inside the module, i.e. SOC (System
On Chip).
General Purpose Operating system

Multi-Tasking Environment
Generic algorithms had been implemented for
performing parallel tasks. They are meant for
faster processing.
Complex operations like 32 bit and 64-bit addition
and subtraction can be done.
Cannot respond and interact with the outside
analog world.
The cost is high due to memory (RAM, ROM)
availability.
 What is Embedded System?
As the name implies, it may be hardware or
software integrated to perform a particular
function.
It uses a Microcontroller/Microprocessor to
perform a single job.
It is a stand-alone device with no operating
system.
Examples may be a washing machine, Music
player, ATM, Vending machine, Data Logger etc.
Nowadays, Most of the devices run on the OS
(Operating System). So, what is the need for an
 The user needs smarter devices capable of
doing multiple jobs in less time.

Supports enough memory to run multiple

applications.

Reusable and Stable with more software

updates.
 Embedded Hardware
The core of any embedded target is the electronic
hardware – which resides on a Printed Circuit
Board.
The embedded development board is divided into
five modules.
Processor
Memory
Input devices
Output devices
Bus controllers.
 Hardware
Hardware is the fundamental resource of any
embedded device and choosing a particular
component depends on the requirement and
specification of the designer.
In the global market, there are many variants of
hardware produced for different applications.
Microcontroller (CPU)
System on Chip (SoC)
ASIC processor
DSP processor
 Microcontroller (CPU)
A Microcontroller is preferred to build small
applications with precise calculation.
Indeed, they have a limited amount of ram.
Some of the famous manufacturing companies
are Altera, Atmel, Renesas, Infineon, NXP and
much more.
Technically, a microcontroller is an intelligent
device that computes the tasks assigned by the
user in an efficient manner.
 System on Chip (SoC)
SoC comprises a CPU, Peripheral devices
(Timers, counters), Communication interfaces
(I²C, SPI, UART), and Power Management
Circuits on a single IC.

If your application should be more reliable with

higher performance and low-cost SoC is the
best choice. It supports one or more processor
cores.
 ASIC processor
ASIC means Application Specific Integrated
Circuit.

Firstly the chip was designed to use for a

particular application and owned by a single
company. So no copyrighting of the product is
allowed. Secondly, it consumes little power.
 DSP processor
You may wonder, these are the most used
processors for Audio and video applications.
DSP Processors removes the noise and improves
signal quality for your DVD player, Music player,
and Gaming consoles.

Note: There may be hundreds of

Microcontroller/Microprocessor present in the
embedded computing system.
 Input Devices
Input devices take input from the outside world.

Some of the examples of input devices are

sensors, switches, photo-diode, optocoupler etc.

They accept input from the user and respond

accordingly.
 Output Devices
The output devices are the indications or results
that occur due to input events from outside the
microcontroller.

Examples of output devices are LCD, LED,

Motors, Seven segment displays, Buzzer,
Relays etc.
 Bus controllers
The bus controller is a communication device that
transfers data between the components inside
an embedded system.

Some of the bus controllers are Serial Buses

(I2C, SPI, SMBus etc.), RS232, RS485 and
Universal Serial Bus.
 Memory
To store the data and deal with memory
management, memory devices like flash and SD
card, EEPROM is required.

Some of the memories used in the embedded

system are Non-Volatile RAM, Volatile RAM,
DRAM (Dynamic Random Access Memory) etc.
 Embedded Software
Software components are essential building
blocks of embedded systems. Embedded
software (sometimes called as firmware)
written for Device drivers
Operating system
Application Software
Error handling and debugging software.
Favorable Embedded Programming
languages
C
Why C for Embedded Systems?

Performance wise better.

Easy to use.
More reliable.
Directly interacts with the hardware.
 INTEL 8051 MICRCONTROLLER
The 8051 is based on an 8-bit CISC core with
Harvard architecture.
16-bit Program Counter
8-bit Processor Status Word (PSW)
8-bit Stack Pointer
Internal RAM of 128bytes
Special Function Registers (SFRs) of 128 bytes
32 I/O pins arranged as four 8-bit ports (P0 – P3)
Two 16-bit timer/counters : T0 and T1
 The salient features of 8051
Microcontroller are
i. 4 KB on chip program memory (ROM or
EPROM)).
ii. 8-bit data bus
iii. 16-bit address bus
iv. 32 general purpose registers each of 8 bits
v. Five Interrupts (3 internal and 2 external).
vi. One Microsecond instruction cycle with 12 MHz
Crystal.
vii. One full duplex serial communication port.
ARCHITECTURE & BLOCK DIAGRAM OF 8051
MICROCONTROLLER

The architecture of the 8051 microcontroller can

be understood from the block diagram.
It has Harward architecture with RISC (Reduced
Instruction Set Computer) concept.
The block diagram of 8051 microcontroller is
shown in the next slide.
8051 has 8-bit ALU which can perform all the 8-bit arithmetic and logical operations in
one machine cycle. The ALU is associated with two registers A & B
 A and B Registers
The A and B registers are special function registers
which hold the results of many arithmetic and
logical operations of 8051.
The A register is also called the Accumulator and
as it’s name suggests, is used as a general
register to accumulate the results of a large
number of instructions.
By default it is used for all mathematical operations
and also data transfer operations between CPU
and any external memory.
The B register is mainly used for multiplication and
 Program Status Register

The 8051 has a 8-bit PSW register which is also known as Flag register.
In the 8-bit register only 6-bits are used by 8051.
The two unused bits are user definable bits.
In the 6-bits four of them are conditional flags .
They are Carry –CY,
Auxiliary Carry-AC,
Parity-P,
and Overflow-OV .
These flag bits indicate some conditions that resulted after an
instruction was executed.
The bits PSW3 and PSW4 are denoted as RS0
and RS1 and these bits are used to select the
bank registers of the RAM location.
The meaning of various bits of PSW register is
shown.
CY

PSW.7 Carry Flag

AC PSW.6 Auxiliary
Carry Flag
FO PSW.5 Flag 0 available for
general purpose .
RS1 PSW.4 Register Bank
select bit 1
RS0 PSW.3 Register bank
select bit 0
 The R registers
The "R" registers are a set of eight registers that
are named R0, R1, etc. up to and including R7.
These registers are used as auxillary registers in
many operations.
The "R" registers are also used to temporarily
store values.
The selection of the register Banks and their
addresses are given below.
 Memory organization
The 8051 microcontroller has 128 bytes of
Internal RAM and 4kB of on chip ROM .
The RAM is also known as Data memory and the
ROM is known as program
memory.
The program memory is also known as Code
memory .This Code memory holds the actual
8051 program that is to be executed.
In 8051 this memory is limited to 64K .
Code memory may be found on-chip, as ROM or
Program Counter(PC) and Stack
Pointer Register (SP)

»?
 STACK in 8051 Microcontroller
The stack is a part of RAM used by the CPU to
store information temporarily. This information
may be either data or an address .
The CPU needs this storage area as there are
only limited number of registers.
The register used to access the stack is called the
Stack pointer which is an 8-bit register..
So,it can take values of 00 to FF H.
When the 8051 is powered up ,the SP register
contains the value 07.i.e the RAM location value
08 is the first location being used for the stack
There are two important instructions to handle this
stack.
One is the PUSH and the Other is the POP.
The loading of data from CPU registers to the
stack is done by PUSH and the loading of the
contents of the stack back into a CPU register is
done by POP.
 Example
MOV R6 ,#35 H
MOV R1 ,#21 H
PUSH 6
PUSH 1
 Memory organization
The 8051 microcontroller has 128 bytes of
Internal RAM and 4kB of on chip ROM .
The RAM is also known as Data memory and the
ROM is known as program
memory.
The program memory is also known as Code
memory .This Code memory holds the actual
8051 program that is to be executed.
In 8051 this memory is limited to 64K .
Code memory may be found on-chip, as ROM or
 Data Pointer Register(DPTR)
It is a 16-bit register which is the only user-
accessible.
DPTR, as the name suggests, is used to point to
data. It is used by a number of commands which
allow the 8051 to access external memory.
When the 8051 accesses external memory it will
access external memory at the address
indicated by DPTR.
This DPTR can also be used as two 8-registers
DPH and DPL.
SPECIAL FUNCTION REGISTERS
(SFRs)
In 8051 microcontroller there certain registers
which uses the RAM addresses from 80h to FFh
and they are meant for certain specific
operations .
These registers are called Special function
registers (SFRs).Some of these registers are bit
addressable also.
The list of SFRs and their functional names are
given below.
In these SFRs some of them are related to I/O
ports (P0,P1,P2 and P3) and some of them are
meant for control operations (TCON,SCON,
PCON..)
Remaining are the auxillary SFRs, in the sense
that they don't directly configure the 8051.
S.No Symbol Name of SFR
Address (Hex)
1 ACC* Accumulator
0E0
2 B* B-Register
0F0
3 PSW* Program Status
word register
0DO
4 SP Stack Pointer
S.No Symbol Name of SFR
Address (Hex)
6 P0* Port 0
80
7 P1* Port 1
90
8 P2* Port 2
0A
9 P3* Port 3
0B
S.No Symbol Name of SFR
Address (Hex)
15 TL0 Timer 0 Lower
byte
8A
16 TH1 Timer 1Higher
byte
8D
17 TL1 Timer 1 lower
Byte
 PARALLEL I /O PORTS
The 8051 microcontroller has four parallel I/O
ports , each of 8-bits .
So, it provides the user 32 I/O lines for connecting
the microcontroller to the peripherals.
The four ports are P0 (Port 0), P1(Port1) ,P2(Port
2) and P3 (Port3).
Upon reset all the ports are output ports.
In order to make them input, all the ports must be
set i.e a high bit must be sent to all the port pins.
This is normally done by the instruction “SETB”.
 PORT 0
Port 0 is an 8-bit I/O port with dual purpose. If
external memory is used, these port pins are
used for the lower address byte address/data
(AD 0 -AD 7 ), otherwise all bits of the port are
either input or output.
Unlike other ports, Port 0 is not provided with pull-
up resistors internally ,so for PORT0 pull-up
resistors of nearly 10k are to be connected
externally as shown
 Dual role of port 0
Port 0 can also be used as address/data
bus(AD0-AD7), allowing it to be used for both
address and data.
When connecting the 8051 to an external
memory, port 0 provides both address and data.
The 8051 multiplexes address and data through
port 0 to save the pins.
ALE indicates whether P0 has address or data.
When ALE = 0, it provides data D0-D7, and
when ALE =1 it provides address and data with
the help of a 74LS373 latch.
 Port 1
Port 1 occupies a total of 8 pins (pins 1 through
8). It has no dual application and acts only as
input or output port.
In contrast to port 0, this port does not need any
pull-up resistors since pull-up resistors
connected internally.
Upon reset, Port 1 is configured as an output port.
To configure it as an input port , port bits must be
set i.e a high bit must be sent to all the port pins.
This is normally done by the instruction “SETB”.
 Port 2
Port 2 is also an eight bit parallel port. (pins 21-
28). It can be used as input or output port.
As this port is provided with internal pull-up
resistors it does not need any external pull-up
resistors.
Upon reset, Port 2 is configured as an output port.
If the port is to be used as input port,all the port
bits must be made high by sending FF to the
port.
 Dual role of port 2
Port2 lines are also associated with the higher
order address lines A8-A15.
In systems based on the 8751, 8951, and
DS5000, Port2 is used as simple I/O port.. But,
in 8051-based systems, port 2 is used along
with P0 to provide the 16-bit address for the
external memory.
Since an 8051 is capable of accessing 64K bytes
of external memory, it needs a path for the 16
bits of the address.
While P0 provides the lower 8 bits via A0-A7, it is
 PORT 3
Port3 is also an 8-bit parallel port with dual
function.( pins 10 to 17). The port pins can be
used for I/O operations as well as for control
operations.
The details of these additional operations are
given below in the table.
Port 3 also do not need any external pull-up
resistors as they are provided internally similar
to the case of Port2 & Port 1.
Upon reset port 3 is configured as an output port .
If the port is to be used as input port, all the port
 Alternate Functions of Port 3
P3.0 and P3.1 are used for the RxD (Receive
Data) and TxD (Transmit Data) serial
communications signals.
Bits P3.2 and P3.3 are meant for external
interrupts.
Bits P3.4 and P3.5 are used for Timers 0 and 1
and P3.6 and P3.7 are used to provide the write
and read signals of external memories
connected in 8051 based systems
 Interrupt Structure
An interrupt is an external or internal event that
disturbs the microcontroller to inform it that a
device needs its service.
The program which is associated with the
interrupt is called the interrupt service routine
(ISR) or interrupt handler.
Upon receiving the interrupt signal the
Microcontroller , finish current instruction and
saves the PC on stack.
Jumps to a fixed location in memory depending
on type of interrupt Starts to execute the
 The 8051 microcontroller has FIVE
interrupts in addition to Reset. They
are
• Timer 0 overflow Interrupt
• Timer 1 overflow Interrupt
• External Interrupt 0(INT0)
• External Interrupt 1(INT1)
• Serial Port events (buffer full, buffer empty, etc)
Interrupt
 Each interrupt has a specific place in code memory where
program execution (interrupt service
routine) begins.

• External Interrupt 0: 0003 H

• Timer 0 overflow: 000B H
• External Interrupt 1: 0013 H
• Timer 1 overflow: 001B H
• Serial Interrupt : 0023 H
Upon reset all Interrupts are disabled & do not
respond to the Micro controller
These interrupts must be enabled by software in
order for the Micro controller to respond to them.
This is done by an 8-bit register called Interrupt
Enable Register (IE).
 Interrupt Enable Register

EA : Global enable/disable. To enable the interrupts this

bit must be set High.
---: Undefined-reserved for future use.
ET2 : Enable /disable Timer 2 overflow interrupt.
ES : Enable/disable Serial port interrupt.
ET1 : Enable /disable Timer 1 overflow interrupt.
EX1 : Enable/disable External interrupt1.
ET0 : Enable /disable Timer 0 overflow interrupt.
EX0 : Enable/disable External interrupt0
 Upon reset the interrupts have the following priority.(Top to
down). The interrupt with the
highest PRIORITY gets serviced first.

1. External interrupt 0 (INT0)

2. Timer interrupt0 (TF0)
3. External interrupt 1 (INT1)
4. Timer interrupt1 (TF1)
5. Serial communication (RI+TI)
Priority can also be set to “high” or “low” by 8-bit IP register.-
Interrupt priority register

IP.7: reserved
IP.6: reserved
IP.5: Timer 2 interrupt priority bit (8052 only)
IP.4: Serial port interrupt priority bit
IP.3: Timer 1 interrupt priority bit
IP.2: External interrupt 1 priority bit
IP.1: Timser 0 interrupt priority bit
IP.0: External interrupt 0 priority bit
 TIMERS in 8051 Microcontrollers
The 8051 microcontroller has two 16-bit timers
Timer 0 (T0) and Timer 1(T1) which can be used
either to generate accurate time delays or as
event counters.
These timers are accessed as two 8-bit registers
TLO, THO & TL1 ,TH1 because the 8051
microcontroller has 8-bit architecture.
 TIMER 0
The Timer 0 is a 16-bit register and can be treated
as two 8-bit registers (TL0 & TH0) and these
registers can be accessed similar to any other
registers like A,B or R1,R2,R3 etc...

The instruction Mov TL0,#07 moves the value 07

into lower byte of Timer0.

Similarly Mov R5,TH0 saves the contents of TH0

in the R5 register.
 TIMER 1
The Timer 1 is also a 16-bit register and can be
treated as two 8-bit registers (TL1 & TH1) and
these registers can be accessed similar to any
other registers like A,B or R1,R2,R3 etc...
The instruction MOV TL1,#05 moves the value 05
into lower byte of Timer1.
Similarly MOV R0,TH1 saves the contents of TH1
in the R0 register
 TMOD Register
The various operating modes of both the timers
T0 and T1 are set by an 8-bit register called
TMOD register.
In this TMOD register the lower 4-bits are meant
for Timer 0 and the higher 4-bits are meant for
Timer1.
 GATE
This bit is used to start or stop the timers by
hardware .When GATE= 1 ,the timers can be
started / stopped by the external sources.
When GATE= 0, the timers can be started or
stopped by software instructions like SETB TR0
or SETB TR1
 C/T (clock/Timer)
This bit decides whether the timer is used as
delay generator or event counter.
When C/T = 0 ,the Timer is used as delay
generator and if C/T=1 the timer is used as an
event counter.
The clock source for the time delay is the crystal
frequency of 8051.
 M1,M0 (Mode)
These two bits are the timer mode bits.
The timers of the 8051 can be configured in three
modes.Mode0, Mode1 and Mode2.
The selection and operation of the modes is
shown below.
 8051 timer TCON REGISTER
The second special function register is Timer
control register. It is an 8 bit register and each
bit has a special function. Bits, symbols and
functions of every bits of TCON register are as
follows

There are two external interrupts EX0 and EX1 to serve external
devices. Both these interrupts are active low. In 8051, P3.2 (INT0)
and P3.3 (INT1) pins are available for external interrupts 0 and 1
respectively.
TF1: Over flow flag for Timer1.
TF1 = 1, Set when timer rolls from all 1s to 0
TF1 = 0, Cleared to execute interrupt service
routine
TR1: Run control bit for timer1.
TR1 =1 Timer1 Turn On
TR1 =0Timer1 Turn Off
TF0: Over flow flag for timer0, same as TF1.
TR0: Runcontrol bit for Timer0, same as TR1.
 ADDRESSING MODES OF 8051
The way in which the data operands are accessed
by different instructions is known as the
addressing modes. There are various methods
of denoting the data operands in the instruction.
The 8051 microcontroller supports mainly 5
addressing modes. They are
1.Immediate addressing mode
2.Direct Addressing mode
3.Register addressing mode
4. Register Indirect addressing mode
 Immediate addressing mode
The addressing mode in which the data operand
is a constant and it is a part of the instruction
itself is known as Immediate addressing mode.
Normally the data must be preceded by a #
sign. This addressing mode can be used to
transfer the data into any of the registers
including DPTR.
MOV DPTR ,# 8245H :Move the data 8245 into
the data pointer register.
MOV P1,#21 H
 Direct addressing mode
The addressing mode in which the data operand
is in the RAM location (00 -7FH) and the
address of the data operand is given in the
instruction is known as Direct addressing mode.
The direct addressing mode uses the lower 128
bytes of Internal RAM and the SFRs
MOV R1, 42H : Move the contents of RAM
location 42 into R1 register
 Register addressing mode
The addressing mode in which the data operand
to be manipulated lies in one of the registers is
known as register addressing mode.
MOV A,R0 : Move the contents of the register R0
to the accumulator
 Register Indirect addressing mode
The addressing mode in which a register is used
as a pointer to the data memory block is known
as Register indirect addressing mode.
MOV A,@ R0 :Move the contents of RAM location
whose address is in R0 into A
 Indexed addressing mode
This addressing mode is used in accessing the
data elements of lookup table entries located in
program ROM space of 8051.
Ex : MOVC A,@ A+DPTR
The 16-bit register DPTR and register A are used
to form the address of the data element stored
in on-chip ROM.
Here C denotes code .In this instruction the
contents of A are added to the 16-bit DPTR
register to form the 16-bit address of the data
operand.
 COMMUNICATION
Data transfer between two electronic devices (Ex
Between a computer and microcontroller or a
peripheral device) is generally done in two ways

(i).Serial data Transfer

(ii).Parallel data Transfer
Serial communication uses only one or two data
lines to transfer data and is generally used for
long distance communication.
In serial communication the data is sent as one bit
at a time in a timed sequence on a single wire.
Serial Communication takes place in two
methods,Asynchronous data Transfer and
Synchronous data Transfer.
 Asynchronous data transfer
Allows data to be transmitted without the sender
having to send a clock signal to the receiver.
Instead, special bits will be added to each word in
order to synchronize the sending and receiving
of the data.
When a word is given to the UART for
Asynchronous transmissions, a bit called the
"Start Bit" is added to the beginning of each
word that is to be transmitted.
The Start Bit is used to alert the receiver that a
word of data is about to be sent, and to force the
clock in the receiver into synchronization with
After the Start Bit, the individual bits of the word of
data are sent .Here each bit in the word is
transmitted for exactly the same amount of time
as all of the other bits.
When the entire data word has been sent, the
transmitter may add a Parity Bit that the
transmitter generates.
The Parity bit may be used by the receiver to
perform simple error checking.
Then at least one Stop Bit is sent by the
transmitter. If the Stop Bit does not appear when
 Synchronous data transfer
In the Synchronous data transfer method the
receiver knows when to “read” the next bit
coming from the sender.
This is achieved by sharing a clock between
sender and receiver. In most forms of serial
Synchronous communication, if there is no data
available at a given time to transmit, a fill
character will be sent instead so that data is
always being transmitted.
Synchronous communication is usually more
efficient because only data bits are transmitted
between sender and receiver, however it will be
Devices that use serial cables for their
communication are split into two categories.
1. DTE (Data Terminal Equipment). Examples of
DTE are computers, printers & terminals.
2. DCE (Data Communication Equipment).
Example of DCE is modems.
 Parallel Data Transfer
Parallel communication uses multiple wires (bus)
running parallel to each other, and can transmit
data on all the wires simultaneously. i.e all the
bits of the byte are transmitted at a time.
So, speed of the parallel data transfer is
extremely high compared to serial data transfer.
An 8-bit parallel data transfer is 8-times faster
than serial data transfer.
Hence with in the computer all data transfer is
mainly based on Parallel data transfer.
But only limitation is due to the high cost ,this
SERIAL COMMUNICATION IN 8051
MICROCONTROLLER
The 8051 has two pins for transferring and
receiving data by serial communication.

These two pins are part of the Port3(P3.0 &P3.1) .

Serial communication is controlled by an 8-bit

register called SCON register,it is a bit
addressable register.
SCON (Serial control) register
M0 , SM1 : These two bits of SCON register
determine the framing of data by specifying the
number of bits per character and start bit and
stop bits. There are 4 serial modes.
SM0 SM1
0 0 : Serial Mode 0
0 1 : Serial Mode 1, 8 bit data,
1 0 : Serial Mode 2
1 1 : Serial Mode 3
REN (Receive Enable) also referred as SCON.4.
When it is high,it allows the 8051 to receive data
on the RxD pin.
So to receive and transfer data REN must be set
to 1.When REN=0,the receiver is disabled.
This is achieved as below SETB SCON.4 & CLR
SCON.4
TI (Transmit interrupt) is the D1 bit of SCON
register. When 8051 finishes the transfer of 8-bit
character, it raises the TI flag to indicate that it is
ready to transfer another byte.
The TI bit is raised at the beginning of the stop bit.
RI (Receive interrupt) is the D0 bit of the SCON
register. When the 8051 receives data serially
,via RxD, it gets rid of the start and stop bits and
places the byte in the SBUF register.
Then it raises the RI flag bit to indicate that a byte
has been received and should be picked up
 ARM7
The ARM7 core is a member of the ARM family of
general-purpose 32-bit microprocessors.
The ARM family offers high performance for very
low power consumption, and small size.
The ARM architecture is based on Reduced
Instruction Set Computer (RISC) principles. The
RISC instruction set, and related decode
mechanism are much simpler than those of
Complex Instruction Set Computer (CISC)
designs. This simplicity gives:
• a high instruction throughput
• an excellent real-time interrupt response
• a small, cost-effective, processor macrocell.
Fetch Instruction fetched from memory
Decode Decoding of registers used in instruction
Execute Register(s) read from register bank
Perform shift and ALU operations
Write register(s) back to register bank
 The instruction pipeline
The ARM7TDMI core uses a pipeline to increase
the speed of the flow of instructions to the
processor. This allows several operations to
take place simultaneously, and the processing
and memory systems to operate continuously.
A three-stage pipeline is used, so instructions are
executed in three stages:
•Fetch
•Decode
•Execute.
 The Arm CPU architecture was originally based upon Reduced
Instruction Set Computer (RISC) principles and incorporated:

A uniform register file, where instructions were not

restricted to acting on specific registers.

A load/store architecture, where data processing

operated only on register contents, and not directly
on memory contents.

Simple addressing modes, where all load/store

addresses were only determined from register
contents and instruction fields.
There are three architecture profiles:
A, R and M.
A-Profile (Applications) is used in complex
compute application areas, such as servers,
mobile phones and automotive head units.
R-Profile (Real-Time) is used where real-time
response is required. For example, safety critical
applications or those needing a deterministic
response, such as medical equipment or vehicle
steering, braking and signalling.
M-Profile (Microcontroller) is used where energy
efficiency, power consumption and size are
important. M-Profile is especially suitable for
deeply-embedded chips. Recently, simple IoT
 Von Neumann Architecture
 32-bit Data Bus
 32-bit Address Bus
 3-stage pipeline
 fetch, decode, execute
 37 32-bit registers
 32-bit ARM instruction set
 16-bit THUMB instruction set
 32x8 Multiplier Barrel Shifter
 The ARM7TDMI processor has two operating states:
ARM state which executes 32-bit, word aligned ARM instructions
THUMB state which can execute 16-bit, halfword aligned
THUMB instructions
 Entering THUMB state
BX instruction with the state bit (bit 0) set in the
operand register. Automatically on return from
an exception (IRQ, FIQ, ABORT, SWI,…), if the
exception was entered with the processor in
THUMB state.

 Entering ARM state

BX instruction with the state bit clear in the
operand register. Automatically on the
processor taking an exception. In this case, the
Saved Program Status Registers (SPSRs) The SPSR is used to store the current
value of the CPSR(current program status register) when an exception is taken so that
it can be restored after handling the exception. Each exception handling mode can
access its own SPSR.
ARM vector routine
 Memory access
The ARM7TDMI core has a Von Neumann
architecture, with a single 32-bit data bus
carrying both instructions and data. Only load,
store, and swap instructions can access data
from memory.
Data can be:
• 8-bit (bytes)
• 16-bit (halfwords)
• 32-bit (words).
Words must be aligned to 4-byte boundaries.
Halfwords must be aligned to 2-byte boundaries.
 Introduction to
Instruction Sets
 mclk A[31:0]
clock
control wait
Din[31:0]
eclk

configuration bigend Dout[31:0]

irq D[31:0] memory

interrupts ¼q interface
isy nc bl[3:0]
r/w
initialization reset mas[1:0]
mreq
enin
enout seq
lock
enouti
abe trans
ale MMU
mode[4:0] interface
bus ape abort
control dbe
tbe Tbit st ate
busen
highz ARM7TDMI tapsm[3:0]
busdis ir[3:0]
ecapclk core tdoen TAP
tck1 information
dbgrq
tck2
breakpt
screg[3:0]
dbgack
exec driv ebs
extern1 ecapclkbs
extern0 icapclkbs
debug dbgen highz
rangeout0 boundary
pclkbs scan
rangeout1 rstclkbs extension
dbgrqi sdinbs
commrx sdoutbs
commtx shclkbs
opc shclk2bs
coprocessor cpi
interface cpa TRST
TCK JTAG
cpb
TMS controls
Vdd TDI
power Vss TDO
 Multiplier Barrel Shifter
The ARM core contains a Barrel shifter which
takes a value to be shifted or rotated, an amount
to shift or rotate by and the type of shift or
rotate.
This can be used by various classes of ARM
instructions to perform comparatively complex
operations in a single instruction.
LSL |shift left by n bits;
--------------------------------------------------------
LSR |logical shift right by n bits;
--------------------------------------------------------
ASR |arithmetic shift right by n bits (the bits fed
into the top end of the operand are copies of
the
original top (or sign) bit);
 RT OS
Main goal of an RTOS scheduler:
meeting timing constraints e.g. deadlines

If you have five homework assignments and only

one is due in an hour, you work on that one

Fairness does not help you meet deadlines

 Do We Need OS for RTS?
Not always
Simplest approach: cyclic executive
loop
do part of task 1
do part of task 2
do part of task 3
end loop
 Cyclic Executive
Advantage:
Simple implementation
Low overhead
Very predictable

Disadvantages

Can’t handle sporadic events (e.g. interrupt)

Everything must operate in lockstep
 Real-Time Systems and OS
We need an OS
For convenience
Multitasking and threads
Cheaper to develop large RT systems
But - don’t want to loose ability to meet deadlines
(timing and resource constraints in general)
This is why RTOS comes into the picture
 Requirements on RTOS
Determinism
Responsiveness (quoted by vendors)
Fast process/thread switch
Fast interrupt response
User control over OS policies
Mainly scheduling, many priority levels
Memory support (especially embedded)
Reliability
 Basic functions of OS kernel
Process mangement
Memory management
Interrupt handling
Exception handling
Process Synchronization (IPC)
Process schedulling
 Process, Thread and Task
A process is a program in execution.
A thread is a “ lightweight ” process, in the sense
that different threads share the same address
space, with all code, data, process status in the
main memory, which gives Shorter creation and
context switch times, and faster IPC
Tasks are implemented as threads in RTOS.
 Basic functions of RTOS kernel
Task mangement
Interrupt handling
Memory management
no virtual memory for hard RT tasks
Exception handling (important)
Task synchronization
Avoid priority inversion
Task scheduling
Time management
Micro-kernel architecture
 Basic functions of RTOS kernel
Task mangement
Interrupt handling
Memory management
Exception handling
Task synchronization
Task scheduling
Time management
 Task: basic notion in RTOS
Task = thread (lightweight process)
A sequential program in execution
It may communicate with other tasks
It may use system resources such as memory
blocks
We may have timing constraints for tasks
 Typical RTOS Task Model
Each task a triplet: (execution time,
period,deadline)
Usually, deadline = period
Can be initiated any time during the period
 Task Classification (1)
Periodic tasks: arriving at fixed frequency, can be
characterized by 3 parameters (C,D,T) where
C = computing time
D = deadline
T = period (e.g. 20ms, or 50HZ)
Often D=T, but it can be D<T or D>T

Also called Time-driven tasks, their activations are

generated by timers
 Task Classification (2)
Non-Periodic or aperiodic tasks = all tasks that
are not periodic, also known as Event-driven,
their activations may be generated by external
interrupts

Sporadic tasks = aperiodic tasks with minimum

interarrival time T min (often with hard deadline)
worst case = periodic tasks with period T min
 Task states (1)
Ready
Running
Waiting/blocked/suspended ...
Idling
Terminated
 TCB (Task Control Block)
Id
Task state (e.g. Idling)
Task type (hard, soft, background ...)
Priority
Other Task parameters
period
comuting time (if available)
Relative deadline
Absolute deadline
Context pointer
Pointer to program code, data area, stack
Pointer to resources (semaphors etc)
Pointer to other TCBs (preceding, next, waiting queues etc)
 Basic functions of RT OS
Task management

Interrupt handling
Memory management
Exception handling
Task synchronization
Task scheduling
Time management
 Task management
Task creation: create a newTCB
Task termination: remove the TCB
Change Priority: modify the TCB
...
State-inquiry: read the TCB
 Task management
Challenges for an RTOS
Creating an RT task, it has to get the memory without
delay: this is difficult because memory has to be
allocated and a lot of data structures, code segment
must be copied/initialized
The memory blocks for RT tasks must be locked in
main memory to avoid access latencies due to
swapping
Changing run-time priorities is dangerous: it may
change the run-time behaviour and predictability of
the whole system
 Basic functions of RT OS
Task management
Interrupt handling
Memory management
Exception handling
Task synchronization
Task scheduling
Time management
 Interrupts
Interrupt: environmental event that demands
attention
Example: “byte arrived” interrupt on serial channel

Interrupt routine: piece of code executed in

response to an interrupt
Handling an Interrupt
 Interrupt Service Routines
Most interrupt routines:
Copy peripheral data into a buffer
Indicate to other code that data has arrived
Acknowledge the interrupt (tell hardware)
Longer reaction to interrupt performed outside
interrupt routine
E.g., causes a process to start or resume running
 Interrupt Handling
Types of interrupts
Asynchronous (or hardware interrupt) by
hardware event (timer, network card ...) the
interrupt handler as a separated task in a
different context.
Synchronous (or software interrupt, or a trap) by
software instruction (swi in ARM, int in Intel
80x86), a divide by zero, a memory
segmentation fault, etc. The interrupt handler
runs in the context of the interrupting task
 Interrupt latency
The time delay between the arrival of interrupt
and the start of corresponding ISR.

Modern processors with multiple levels of caches

and instruction pipelines that need to be reset
before ISR can start might result in longer
latency.

The ISR of a lower-priority interrupt may be

blocked by the ISR of a high-priority
 Basic functions of RT OS
Task mangement
Interrupt handling
Memory management
Exception handling
Task synchronization
Task scheduling
Time management
 Memory Management/Protection
Standard methods
Block-based, Paging, hardware mapping for
protection
No virtual memory for hard RT tasks
Lock all pages in main memory
Many embedded RTS do not have memory
protection – tasks may access any blocks –
Hope that the whole design is proven correct
and protection is unnecessary
to achive predictable timing
to avoid time overheads
Most commercial RTOS provide memory
protection as an option
Run into ”fail-safe” mode if an illegal access trap
occurs
Useful for complex reconfigurable systems
 Basic functions of RT OS
Task mangement
Interrupt handling
Memory management
Exception handling
Task synchronization
Task scheduling
Time management
 Exception handling
Exceptions e.g missing deadline, running out of
memory, timeouts, deadlocks
Error at system level, e.g. deadlock
Error at task level, e.g. timeout
Standard techniques:
System calls with error code
Watch dog
Fault-tolerance (later)
However, difficult to know all senarios
Missing one possible case may result in disaster
 Watch-dog
A task, that runs (with high priority) in parallel with
all others
If some condition becomes true, it should react …
Loop
begin
• ....
end
until condition
The condition can be an external event, or some
flags
Watch-dog (to monitor whether the application
task is alive)
Loop
if flag==1 then
{
• next :=system_time;
• flag :=0
}
else if system_time> next+20s then WARNING;
sleep(100ms)
end loop
 Task Synchronization
Synchronization primitives
Semaphore : counting semaphore and binary
semaphore
A semaphore is created with initial_count, which is
the number of allowed holders of the
semaphore lock. (initial_count=1: binary sem)
Sem_wait will decrease the count; while
sem_signal will increase it. A task can get the
semaphore when the count > 0; otherwise,
block on it.
Mutex : similar to a binary semaphore, but mutex
has an owner .
a semaphore can be “waited for” and “signaled”
by any task,
while only the task that has taken a mutex is
allowed to release it.
Spinlock : lock mechanism for multi-processor
systems,
A task wanting to get spinlock has to get a lock
shared by all processors.
Read/write locks : protect from concurrent write,
while allow concurrent read
Many tasks can get a read lock; but only one task
can get a write lock.
Before a task gets the write lock, all read locks
have to be released.
Barrier : to synchronize a lot of tasks,
they should wait until all of them have reached a
certain “barrier.”
 Task Synchronization
Challenges for RTOS
Critical section (data, service, code) protected by
lock mechanism e.g. Semaphore etc. In a
RTOS, the maximum time a task can be
delayed because of locks held by other tasks
should be less than its timing constraints.
Race condition – deadlock, livelock, starvation
Some deadlock avoidance/prevention
algorithms are too complicate and
indeterministic for real-time execution. Simplicity
is preferred, like
 IPC: Data exchanging
Semaphore
Shared variables
Bounded buffers
FIFO
Mailbox
Message passing
Signal
Task states
 Priority-based Scheduling
Typical RTOS based on fixed-priority preemptive
scheduler
Assign each process a priority
At any time, scheduler runs highest priority
process ready to run
Process runs to completion unless preempted
 Scheduling algorithms
Sort the READY queue acording to
Priorities (HPF)
Execution times (SCF)
Deadlines (EDF)
Arrival times (FIFO)
Classes of scheduling algorithms
Preemptive vs non preemptive
Off-line vs on-line
Static vs dynamic
Event-driven vs time-driven
 Priority-based scheduling in RTOS
static priority
A task is given a priority at the time it is created,
and it keeps this priority during the whole
lifetime.
The scheduler is very simple, because it looks at
all wait queues at each priority level, and starts
the task with the highest priority to run.
dynamic priority
The scheduler becomes more complex because it
has to calculate task’s priority on-line, based on
dynamically changing parameters.
Earliest-deadline-first (EDF) --- A task with a closer
deadline gets a higher scheduling priority.
Rate-monotonic scheduling
A task gets a higher priority if it has to run more
frequently.
This is a common approach in case that all tasks are
periodic . So, a task that has to run every n
 Time management
A high resolution hardware timer is programmed to
interrupt the processor at fixed rate – Time
interrupt
Each time interrupt is called a system tick (time
resolution):
Normally, the tick can vary in microseconds (depend on
hardware)
The tick may (not necessarily) be selected by the user
All time parameters for tasks should be the multiple of
the tick
Note: the tick may be chosen according to the given
task parameters
Time interrupt routine
RT linux