LTC1261 Switched Capacitor Regulated Voltage Inverter

FEATURES
s s s s s s s s s s

DESCRIPTIO

Regulated Negative Voltage from a Single Positive Supply Can Provide Regulated 5V from a 3V Supply REG Pin Indicates Output is in Regulation Low Output Ripple: 5mV Typ Supply Current: 600A Typ Shutdown Mode Drops Supply Current to 5A Up to 15mA Output Current Adjustable or Fixed Output Voltages Requires Only Three or Four External Capacitors Available in SO-8 Packages

APPLICATI
s s s s

GaAs FET Bias Generators Negative Supply Generators Battery-Powered Systems Single Supply Applications

The LTC1261 is a switched-capacitor voltage inverter designed to provide a regulated negative voltage from a single positive supply. The LTC1261CS operates from a single 3V to 8V supply and provides an adjustable output voltage from 1.25V to 8V. An on-chip resistor string allows the LTC1261CS to be configured for output voltages of 3.5V, 4V, 4.5V or 5V with no external components. The LTC1261CS8 is optimized for applications which use a 5V or higher supply or which require low output voltages. It requires a single external 0.1F capacitor and provides adjustable and fixed output voltage options in 8-pin SO packages. The LTC1261CS requires one or two external 0.1F capacitors, depending on input voltage. Both versions require additional external input and output bypass capacitors. An optional compensation capacitor at ADJ/COMP can be used to reduce the output voltage ripple. Each version of the LTC1261 will supply up to 12mA output current with guaranteed output regulation of 5%. The LTC1261 includes an open-drain REG output which pulls low when the output is within 5% of the set value. Output ripple is typically as low as 5mV. Quiescent current is typically 600A when operating and 5A in shutdown. The LTC1261 is available in a 14-pin narrow body SO package and an 8-pin SO package.
, LTC and LT are registered trademarks of Linear Technology Corporation.

TYPICAL APPLICATION
4V Generator with Power Valid
5V 5V C1 1F C2 0.1F 1 2 VCC SHDN 8 10k POWER VALID VOUT = 4V AT 10mA
SHDN OUT

Waveforms for 4V Generator with Power Valid

0V

7 REG C1 + LTC1261-4 3 6 OUT C1 4 GND COMP 5 C3* 100pF

4V 5V 0V 5V POWER VALID 0V
LTC1261 TA01

C4 3.3F

*OPTIONAL

U
0.2mS/DIV
LTC1261 TAO2

UO

LTC1261 ABSOLUTE
(Note 1)

AXI U

RATI GS

PACKAGE/ORDER I FOR ATIO

TOP VIEW VCC 1 C1+ 2 C1 3 GND 4 8 7 6 5 SHDN REG OUT ADJ (COMP*)

Supply Voltage (Note 2)............................................ 9V Output Voltage (Note 5) .............................. 0.3V to 9V Total Voltage, VCC to VOUT (Note 2) ........................ 12V Input Voltage SHDN Pin ................................. 0.3V to VCC + 0.3V REG Pin ............................................... 0.3V to 12V ADJ, RO, R1, RADJ ............... VOUT 0.3V to VCC + 0.3V Output Short-Circuit Duration ......................... Indefinite Operating Temperature Range Commercial ............................................ 0C to 70C Extended Commercial (Note 7) .......... 40C to 85C Storage Temperature Range ................ 65C to 150C Lead Temperature (Soldering, 10 sec)................. 300C

ORDER PART NUMBER LTC1261CS8 LTC1261CS8-4 LTC1261CS8-4.5 S8 PART MARKING 1261 12614 126145 ORDER PART NUMBER LTC1261CS

S8 PACKAGE 8-LEAD PLASTIC SO *FOR FIXED VERSIONS

TJMAX = 150C, JA = 150 C/W

TOP VIEW NC 1 C1+ 2 C1 C2+ 3 4 14 VCC 13 SHDN 12 REG 11 OUT 10 ADJ 9 8 RADJ R1

C2 5 GND 6 R0 7

S PACKAGE 14-LEAD PLASTIC SO

TJMAX = 150C, JA = 110C/W

Consult factory for Industrial or Military grade parts.

ELECTRICAL CHARACTERISTICS
SYMBOL VREF IS PARAMETER Reference Voltage Supply Current CONDITIONS

VCC = 3V to 6.5V, TA = 25C unless otherwise specified.

0C TA 70C MIN
q

TYP 1.24 600 900 5 550 65 0.1 8 15 0.01

MAX 1.28 1000 1500 20

40C TA 85C (Note 7) MIN TYP MAX 1.20 1.24 600 900 5 550 65 0.1 8 15 0.01 1.28 1500 2000 20

UNITS V A A A kHz % V mA mA A V V A s

1.20

No Load, SHDN Floating, Doubler Mode No Load, SHDN Floating, Tripler Mode No Load, VSHDN = VCC

q q q

fOSC PEFF VOL IREG IADJ VIH VIL IIN tON

Internal Oscillator Frequency Power Efficiency REG Output Low Voltage REG Sink Current Adjust Pin Current SHDN Input High Voltage SHDN Input Low Voltage SHDN Input Current Turn-On Time

IREG = 1mA VREG = 0.8V, VCC = 3.3V VREG = 0.8V, VCC = 5.0V VADJ = 1.24V

q q q q q q

0.8 5 8 1 2 0.8 20

0.8

5 8 2

1 0.8 25

VSHDN = VCC IOUT = 15mA

5 500

5 500

W W

LTC1261

ELECTRICAL CHARACTERISTICS
Doubler Mode. VCC = 5V 10%, C1 = 0.1F, C2 = 0 (Note 4), COUT = 3.3F unless otherwise specified.
0C TA 70C SYMBOL PARAMETER VOUT Output Regulation (Note 2) ISC VRIP Output Short-Circuit Current Output Ripple Voltage CONDITIONS (Note 2) 1.24V VOUT 4V, 0 IOUT 8mA 1.24V VOUT 4V, 0 IOUT 7mA 4V VOUT 5V, 0 IOUT 8mA (Note 6) VOUT = 0V IOUT = 5mA, VOUT = 4V MIN
q q q

TYP 1 2 60 5

MAX 5

40C TA 85C (Note 7) MIN TYP MAX 1 2 60 5 5 125

125

UNITS % % % mA mV

LTC1261CS Only. Tripler Mode. VCC = 2.7V, C1 = C2 = 0.1F (Note 4), COUT = 3.3F unless otherwise specified.
0C TA 70C SYMBOL VOUT ISC VRIP PARAMETER Output Regulation Output Short-Circuit Current Output Ripple Voltage CONDITIONS (Note 2) 1.24V VOUT 4V, 0 IOUT 5mA VOUT = 0V IOUT = 5mA, VOUT = 4V MIN
q q

TYP 1 60 5

MAX 5 125

40C TA 85C (Note 7) MIN TYP MAX 1 5 60 125 5

UNITS % mA mV

LTC1261CS Only. Tripler Mode. VCC = 3.3V 10%, C1 = C2 = 0.1F (Note 4), COUT = 3.3F unless otherwise specified.
0C TA 70C SYMBOL PARAMETER VOUT Output Regulation (Note 2) ISC Output Short-Circuit Current VRIP Output Ripple Voltage CONDITIONS (Note 2) 1.24V VOUT 4.5V, 0 IOUT 6mA 4.5V VOUT 5V, 0 IOUT 3.5mA VOUT = 0V IOUT = 5mA, VOUT = 4V MIN
q q q

TYP 1 2 35 5

MAX 5 5 75

40C TA 85C (Note 7) MIN TYP MAX 1 5 2 35 75 5

UNITS % % mA mV

LTC1261CS Only. Tripler Mode. VCC = 5V 10%, C1 = C2 = 0.1F (Note 4), COUT = 3.3F unless otherwise specified.
0C TA 70C SYMBOL PARAMETER VOUT Output Regulation ISC VRIP Output Short-Circuit Current Output Ripple Voltage CONDITIONS (Note 2) 1.24V VOUT 4V, 0 IOUT 12mA 4V VOUT 5V, 0 IOUT 10mA VOUT = 0V IOUT = 5mA, VOUT = 4V MIN
q q q

TYP 1 2 35 5

MAX 5 5 75

40C TA 85C (Note 7) MIN TYP MAX 1 5 2 5 35 75 5

UNITS % % mA mV

The q denotes specifications which apply over the full operating temperature range. Note 1: The Absolute Maximum Ratings are those values beyond which the life of a device may be impaired. Note 2: All currents into device pins are positive; all currents out of device pins are negative. All voltages are referenced to ground unless otherwise specified. Note 3: All typicals are given at TA = 25C. Note 4: C1 = C2 = 0.1F means the specifications apply to tripler mode where VCC VOUT = 3VCC (LTC1261CS only; the LTC1261CS8 cannot be connected in tripler mode) with C1 connected between C1+ and C1 and C2 connected between C2 + and C2 . C2 = 0 implies doubler mode where VCC VOUT = 2VCC; for the LTC1261CS this means C1 connects from C1+

to C2 with C1 and C2 + floating. For the LTC1261CS8 in doubler mode, C1 connects from C1+ to C1 ; there are no C2 pins. Note 5: Setting output to < 7V will exceed the absolute voltage maximum rating with a 5V supply. With supplies higher than 5V, the output should never be set to exceed VCC 12V. Note 6: For output voltages below 4.5V the LTC1261 may reach 50% duty cycle and fall out of regulation with heavy load or low input voltages. Beyond this point, the output will follow the input with no regulation. Note 7: C grade device specifications are guaranteed over the 0C to 70C temperature range. In addition, C grade device specifications are assured over the 40C to 85C temperature range by design or correlation, but are not production tested.

LTC1261 TYPICAL PERFORMANCE CHARACTERISTICS

Output Voltage vs Output Current
3.5 3.6 3.7
OUTPUT VOLTAGE (V)

TA = 25C
OUTPUT VOLTAGE (V)

3.8 3.9 4.0 4.1 4.2 4.3 4.4 4.5 0 1 2 3 4 5 6 7 8 OUTPUT CURRENT (mA) 9 10 VCC = 5V DOUBLER MODE VCC = 3.3V TRIPLER MODE

3.8 3.9 4.0 4.1 4.2 4.3 4.4 4.5 5.0 5.2 5.4 5.6 5.8 6.0 6.2 6.4 6.6 6.8 7.0 SUPPLY VOLTAGE (V)
LT1261 TP02

OUTPUT VOLTAGE (V)

Maximum Output Current vs Supply Voltage

50
MAXIMUM OUTPUT CURRENT (mA)

VOUT = 4V 5% TA = 25C

TRIPLER MODE 30 DOUBLER MODE 20

SUPPLY CURRENT (A)

SUPPLY CURRENT (A)

40

10 3.0 3.5 4.0 4.5 5.0 5.5 6.0 SUPPLY VOLTAGE (V) 6.5 7.0

TEST CIRCUITS
Doubler Mode
5V 1 VCC SHDN 8
2 0.1F 3

10F

2 0.1F

7 REG C1 + LTC1261-4 3 6 OUT C1 4 GND COMP 5

U W
LT1261 TP01
LTC1261 TPC04

(See Test Circuits) Output Voltage (Tripler Mode) vs Supply Voltage

3.5 3.6 3.7 3.8 3.9 4.0 4.1 4.2 4.3 4.4 4.5 3 4 6 5 SUPPLY VOLTAGE (V) 7
LTC1261 TPC03

Output Voltage (Doubler Mode) vs Supply Voltage

3.5 3.6 3.7

TA = 85C TA = 25C TA = 40C

TA = 85C TA = 25C TA = 40C

Supply Current vs Supply Voltage

1200 1000 900 800 TRIPLER MODE 700 600 500 3.0 3.5 4.0 4.5 5.0 5.5 6.0 6.5 7.0 7.5 8.0 SUPPLY VOLTAGE (V)
LTC1261 TPC05

Supply Current vs Temperature

1200 VOUT = 4V 1000 900 800 700 600 500 40 20 VCC = 3.3V TRIPLER MODE

VOUT = 4V TA = 25C

VCC = 5V DOUBLER MODE

DOUBLER MODE

40 20 60 0 TEMPERATURE (C)

80

100

LTC1261 TPC06

Tripler Mode
VIN = 3.3V 14 C1 + VCC ADJ 10 10F

VOUT = 4V 5%

3.3F
LTC1261 TCO1

9 C1 RADJ LTC1261CS 8 4 C2+ R1 5 C2 R0 OUT GND 6 7 11 VOUT = 4V 5%

0.1F

+
LTC1261 TC02

3.3F

LTC1261

PIN FUNCTIONS
Pin numbers are shown as (LTC1261CS/LTC1261CS8). NC (Pin 1/NA): No Internal Connection. C1+ (Pin 2/ Pin 2): C1 Positive Input. Connect a 0.1F capacitor between C1+ and C1. With the LTC1261CS in doubler mode, connect a 0.1F capacitor from C1+ to C2 . C1 (Pin 3/Pin 3): C1 Negative Input. Connect a 0.1F capacitor from C1+ to C1. With the LTC1261CS in doubler mode only, C1 should float. C2 + (Pin 4/NA): C2 Positive Input. In tripler mode connect a 0.1F capacitor from C2 + to C2 . This pin is used with the LTC1261CS in tripler mode only; in doubler mode this pin should float. C2 (Pin 5/NA): C2 Negative Input. In tripler mode connect a 0.1F capacitor from C2 + to C2 . In doubler mode connect a 0.1F capacitor from C1+ to C2 . GND (Pin 6/Pin 4): Ground. Connect to a low impedance ground. A ground plane will help to minimize regulation errors. R0 (Pin 7/NA): Internal Resistor String, 1st Tap. See Table 2 in the Applications Information section for information on internal resistor string pin connections vs output voltage. R1 (Pin 8/NA): Internal Resistor String, 2nd Tap. RADJ (Pin 9/NA): Internal Resistor String Output. Connect this pin to ADJ to use the internal resistor divider. See Table 2 in the Applications Information section for information on internal resistor string pin connections vs output voltage. ADJ (COMP for fixed versions) (Pin 10/Pin 5): Output Adjust/Compensation Pin. For adjustable parts this pin is used to set the output voltage. The output voltage should be divided down with a resistor divider and fed back to this pin to set the regulated output voltage. The resistor divider can be external or the internal divider string can be used if it can provide the required output voltage. Typically the resistor string should draw 10A from the output to minimize errors due to the bias current at the adjust pin. Fixed output parts have the internal resistor string connected to this pin inside the package. The pin can be used to trim the output voltage if desired. It can also be used as an optional feedback compensation pin to reduce output ripple on both adjustable and fixed output voltage parts. See Applications Information section for more information on compensation and output ripple. OUT (Pin 11/Pin 6): Negative Voltage Output. This pin must be bypassed to ground with a 1F or larger capacitor; it must be at least 3.3F to provide specified output ripple. The size of the output capacitor has a strong effect on output ripple. See the Applications Information section for more details. REG (Pin 12/Pin 7): This is an open drain output that pulls low when the output voltage is within 5% of the set value. It will sink 8mA to ground with a 5V supply. The external circuitry must provide a pull-up or REG will not swing high. The voltage at REG may exceed VCC and can be pulled up to 12V above ground without damage. SHDN (Pin 13/Pin 8): Shutdown. When this pin is at ground the LTC1261 operates normally. An internal 5A pull-down keeps SHDN low if it is left floating. When SHDN is pulled high, the LTC1261 enters shutdown mode. In shutdown the charge pump stops, the output collapses to 0V and the quiescent current drops to 5A typically. VCC (Pin 14/Pin 1): Power Supply. This requires an input voltage between 3V and 6.5V. Certain combinations of output voltage and operating mode may place additional restrictions on the input voltage. VCC must be bypassed to ground with at least a 0.1F capacitor placed in close proximity to the chip. See the Applications Information section for details.

LTC1261
APPLICATIONS INFORMATION
MODES OF OPERATION The LTC1261 uses a charge pump to generate a negative output voltage that can be regulated to a value either higher or lower than the original input voltage. It has two modes of operation: a doubler inverting mode, which can provide a negative output equal to or less than the positive power supply and a tripler inverting mode, which can provide negative output voltages either larger or smaller in magnitude than the original positive supply. The tripler offers greater versatility and wider input range but requires four external capacitors and a 14-pin package. The doubler offers the SO-8 package and requires only three external capacitors. Doubler Mode Doubler mode allows the LTC1261 to generate negative output voltage magnitudes up to that of the supply voltage, creating a voltage between VCC and OUT of up to two times VS. In doubler mode the LT1261 uses a single flying capacitor to invert the input supply voltage, and the output voltage is stored on the output bypass capacitor between switch cycles. The LTC1261CS8 is always configured in doubler mode and has only one pair of flying capacitor pins (Figure 1a). The LTC1261CS can be configured in doubler mode by connecting a single flying capacitor between the C1+ and C2 pins. C1 and C2 + should be left floating (Figure 1b). Tripler Mode The LTC1261CS can be used in a tripler mode which can generate negative output voltages up to twice the supply voltage. The total voltage between the VCC and OUT pins can be up to three times VS. For example, tripler mode can be used to generate 5V from a single positive 3.3V supply. Tripler mode requires two external flying capacitors. The first connects between C1+ and C1 and the second between C2 + and C2 (Figure 1c). Because of the relatively high voltages that can be generated in this mode, care must be taken to ensure that the total input-to-output voltage never exceeds 12V or the LTC1261 may be damaged. In most applications the output voltage will be kept in check by the regulation loop. Damage is possible however, with supply voltages above 4V in tripler mode and above 6V in doubler mode. As the input supply voltage rises the allowable output voltage drops, finally reaching 4V with an 8.5V supply. To avoid this problem use doubler mode whenever possible with high input supply voltages.
1 2 3 1 2 C1 3 4 a.) LTC1261CS8 DOUBLER MODE C1+ C1 8 C1 7 LTC1261 6 5 4 5 6 7 b.) LTC1261CS DOUBLER MODE C1+ C1 C2+ LTC1261 C2 14 13 12 C1 11 10 C2 9 8 1 2 3 4 5 6 7 c.) LTC1261CS TRIPLER MODE
LTC1261 F01

14 C1+ C1 C2+ LTC1261 C2

13 12 11 10 9 8

Figure 1. Flying Capacitor Connections

THEORY OF OPERATION A block diagram of the LTC1261 is shown in Figure 2. The heart of the LTC1261 is the charge pump core shown in the dashed box. It generates a negative output voltage by first charging the flying capacitors between VCC and ground. It then stacks the flying capacitors on top of each other and connects the top of the stack to ground forcing the bottom of the stack to a negative voltage. The charge on the flying capacitors is transferred to the output bypass capacitor, leaving it charged to the negative output voltage. This process is driven by the internal clock. Figure 2 shows the charge pump configured in tripler mode. With the clock low, C1 and C2 are charged to VCC by S1, S3, S5 and S7. At the next rising clock edge, S1, S3, S5 and S7 open and S2, S4 and S6 close, stacking C1 and C2 on top of each other. S2 connects C1+ to ground, S4 connects C1 to C2+ and C2 is connected to the output by S6. The charge in C1 and C2 is transferred to COUT, setting it to a negative voltage. Doubler mode works the same way except that the single flying capacitor (C1) is connected between C1+ and C2 . S3, S4 and S5 dont do anything useful in doubler mode. C1 is charged initially by S1 and S7 and connected to the output by S2 and S6.

LTC1261

APPLICATIONS INFORMATION
VCC

CLK 550kHz

S Q R S2

+
COMP 1

60mV VREF = 1.24V 1.18V

VOUT

The output voltage is monitored by COMP1 which compares a divided replica of the output at ADJ (COMP for fixed output parts) to the internal reference. At the beginning of a cycle the clock is low, forcing the output of the AND gate low and charging the flying capacitors. The next rising clock edge sets the RS latch, setting the charge pump to transfer charge from the flying capacitors to the output capacitor. As long as the output is below the set point, COMP1 stays low, the latch stays set and the charge pump runs at the full 50% duty cycle of the clock gated through the AND gate. As the output approaches the set voltage, COMP1 will trip whenever the divided signal exceeds the internal 1.24V reference relative to OUT. This resets the RS latch and truncates the clock pulses, reducing the amount of charge transferred to the output capacitor and regulating the output voltage. If the output exceeds the set point, COMP1 stays high, inhibiting the RS latch and disabling the charge pump.

S1

S5

OUT

+
C1+ C1 C1

C2+ S4 C2 C2

124k S6 226k

COUT RADJ*

R1* INTERNALLY CONNECTED FOR FIXED OUTPUT VOLTAGE PARTS

S3

S7

100k

R0*

50k ADJ/COMP

+
COMP 2

REG

*LTC1261CS14 ONLY
LTC1261 F02

Figure 2. Block Diagram

COMP2 also monitors the divided signal at ADJ but it is connected to a 1.18V reference, 5% below the main reference voltage. When the divided output exceeds this lower reference voltage indicating that the output is within 5% of the set value, COMP2 goes high turning on the REG output transistor. This is an open drain N-channel device capable of sinking 5mA with a 3.3V VCC and 8mA with a 5V VCC. When in the off state (divided output more than 5% below VREF) the drain can be pulled above VCC without damage up to a maximum of 12V above ground. Note that the REG output only indicates if the magnitude of the output is below the magnitude of the set point by 5% (i.e., VOUT > 4.75V for a 5V set point). If the magnitude of the output is forced higher than the magnitude of the set point ( i.e., to 6V when the output is set for 5V) the REG output will stay low.

LTC1261

APPLICATIONS INFORMATION
OUTPUT RIPPLE Output ripple in the LTC1261 comes from two sources; voltage droop at the output capacitor between clocks and frequency response of the regulation loop. Voltage droop is easy to calculate. With a typical clock frequency of 550kHz, the charge on the output capacitor is refreshed once every 1.8s. With a 15mA load and a 3.3F output capacitor, the output will droop by: To prevent this from happening, an external capacitor can be connected from ADJ (or COMP for fixed output parts) to ground to compensate for external parasitics and increase the regulation loop bandwidth (Figure 3). This sounds counterintuitive until we remember that the internal reference is generated with respect to OUT, not ground.
TO CHARGE PUMP RESISTORS ARE INTERNAL FOR FIXED OUTPUT PARTS

1.8s ILOAD t = 15mA = 8.2mV 3.3F COUT

This can be a significant ripple component when the output is heavily loaded, especially if the output capacitor is small. If absolute minimum output ripple is required, a 10F or greater output capacitor should be used. Regulation loop frequency response is the other major contributor to output ripple. The LTC1261 regulates the output voltage by limiting the amount of charge transferred to the output capacitor on a cycle-by-cycle basis. The output voltage is sensed at the ADJ pin (COMP for fixed output versions) through an internal or external resistor divider from the OUT pin to ground. As the flying capacitors are first connected to the output, the output voltage begins to change quite rapidly. As soon as it exceeds the set point COMP1 trips, switching the state of the charge pump and stopping the charge transfer. Because the RC time constant of the capacitors and the switches is quite short, the ADJ pin must have a wide AC bandwidth to be able to respond to the output in time. External parasitic capacitance at the ADJ pin can reduce the bandwidth to the point where the comparator cannot respond by the time the clock pulse finishes. When this happens the comparator will allow a few complete pulses through, then overcorrect and disable the charge pump until the output drops below the set point. Under these conditions the output will remain in regulation but the output ripple will increase as the comparator hunts for the correct value.
COMP 1 R1

) )

) )

CC 100pF ADJ/COMP

REF

+ 1.24V

R2 VOUT
LTC1261 F03

Figure 3. Regulator Loop Compensation

The feedback loop actually sees ground as its output, thus the compensation capacitor should be connected across the top of the resistor divider, from ADJ (or COMP) to ground. By the same token, avoid adding capacitance between ADJ (or COMP) and VOUT. This will slow down the feedback loop and increase output ripple. A 100pF capacitor from ADJ or COMP to ground will compensate the loop properly under most conditions. OUTPUT FILTERING If extremely low output ripple (< 5mV) is required, additional output filtering is required. Because the LTC1261 uses a high 550kHz switching frequency, fairly low value RC or LC networks can be used at the output to effectively filter the output ripple. A 10 series output resistor and a 3.3F capacitor will cut output ripple to below 3mV (Figure 4). Further reductions can be obtained with larger filter capacitors or by using an LC output filter.

LTC1261

APPLICATIONS INFORMATION
5V 1F 2 0.1F 3 C1
+

VCC OUT 6

10 VOUT = 4V

LTC1261CS8-4 C1 COMP GND 4

LTC1261 F04

+
100pF

3.3F

3.3F

Figure 4. Output Filter Cuts Ripple Below 3mV

CAPACITOR SELECTION Capacitor Sizing The performance of the LTC1261 can be affected by the capacitors it is connected to. The LTC1261 requires bypass capacitors to ground for both the VCC and OUT pins. The input capacitor provides most of LTC1261s supply current while it is charging the flying capacitors. This capacitor should be mounted as close to the package as possible and its value should be at least five times larger than the flying capacitor. Ceramic capacitors generally provide adequate performance but avoid using a tantalum capacitor as the input bypass unless there is at least a 0.1F ceramic capacitor in parallel with it. The charge pump capacitors are somewhat less critical since their peak currents are limited by the switches inside the LTC1261. Most applications should use 0.1F as the flying capacitor value. Conveniently, ceramic capacitors are the most common type of 0.1F capacitor and they work well here. Usually the easiest solution is to use the same capacitor type for both the input bypass and the flying capacitors. In applications where the maximum load current is welldefined and output ripple is critical or input peak currents need to be minimized, the flying capacitor values can be tailored to the application. Reducing the value of the flying capacitors reduces the amount of charge transferred with each clock cycle. This limits maximum output current, but also cuts the size of the voltage step at the

output with each clock cycle. The smaller capacitors draw smaller pulses of current out of VCC as well, limiting peak currents and reducing the demands on the input supply. Table 1 shows recommended values of flying capacitor vs maximum load capacity.
Table 1. Typical Max Load (mA) vs Flying Capacitor Value at TA = 25C, VOUT = 4V
FLYING CAPACITOR VALUE (F) 0.1 0.047 0.033 0.022 0.01 MAX LOAD (mA) MAX LOAD (mA) VCC = 5V DOUBLER MODE VCC = 3.3V TRIPLER MODE 22 16 8 4 1 20 15 11 5 3

The output capacitor performs two functions: it provides output current to the load during half of the charge pump cycle and its value helps to set the output ripple voltage. For applications that are insensitive to output ripple, the output bypass capacitor can be as small as 1F. To achieve specified output ripple with 0.1F flying capacitors, the output capacitor should be at least 3.3F. Larger output capacitors will reduce output ripple further at the expense of turn-on time. Capacitor ESR Output capacitor Equivalent Series Resistance (ESR) is another factor to consider. Excessive ESR in the output capacitor can fool the regulation loop into keeping the output artificially low by prematurely terminating the charging cycle. As the charge pump switches to recharge the output a brief surge of current flows from the flying capacitors to the output capacitor. This current surge can be as high as 100mA under full load conditions. A typical 3.3F tantalum capacitor has 1 or 2 of ESR; 100mA 2 = 200mV. If the output is within 200mV of the set point this additional 200mV surge will trip the feedback comparator and terminate the charging cycle. The pulse dissipates quickly and the comparator returns to the correct state, but the RS latch will not allow the charge pump to respond until the next clock edge. This prevents the charge

LTC1261

APPLICATIONS INFORMATION
pump from going into very high frequency oscillation under such conditions but it also creates an output error as the feedback loop regulates based on the top of the spike, not the average value of the output (Figure 5). The resulting output voltage behaves as if a resistor of value CESR (IPK/IAVE) was placed in series with the output. To avoid this nasty sequence of events connect a 0.1F ceramic capacitor in parallel with the larger output capacitor. The ceramic capacitor will eat the high frequency spike, preventing it from fooling the feedback loop, while the larger but slower tantalum or aluminum output capacitor supplies output current to the load between charge cycles.
CLOCK

LOW ESR OUTPUT CAP

VOUT

HIGH ESR OUTPUT CAP

VOUT

Figure 5. Output Ripple with Low and High ESR Capacitors

Note that ESR in the flying capacitors will not cause the same condition; in fact, it may actually improve the situation by cutting the peak current and lowering the amplitude of the spike. However, more flying capacitor ESR is not necessarily better. As soon as the RC time constant approaches half of a clock period (the time the capacitors have to share charge at full duty cycle) the output current capability of the LTC1261 will begin to diminish. For 0.1F flying capacitors, this gives a maximum total series resistance of:
1 1 tCLK = 1 / 0.1F = 9.1 2 CFLY 2 550kHz

) ) )

10

Most of this resistance is already provided by the internal switches in the LTC1261 (especially in tripler mode). More than 1 or 2 of ESR on the flying capacitors will start to affect the regulation at maximum load. RESISTOR SELECTION Resistor selection is easy with the fixed output versions of the LTC1261 no resistors are needed! Selecting the right resistors for the adjustable parts is only a little more difficult. A resistor divider should be used to divide the signal at the output to give 1.24V at the ADJ pin with respect to VOUT (Figure 6). The LTC1261 uses a positive reference with respect to VOUT, not a negative reference with respect to ground (Figure 2 shows the reference connection). Be sure to keep this in mind when connecting the resistors! If the initial output is not what you expected, try swapping the two resistors.
6 (4*) R1

VSET VOUT AVERAGE COMP1 OUTPUT

GND
VSET VOUT AVERAGE

LTC1261 ADJ

10 (5*)

R2
COMP1 OUTPUT
LTC1261 F05

OUT

11 (6*) *LTC1261CS8

VOUT = 1.24V

R1 + R2 R2

LTC1261 F06

Figure 6. External Resistor Connections

The 14-pin adjustable parts include a built-in resistor string which can provide an assortment of output voltages by using different pin-strapping options at the R0, R1, and RADJ pins (Table 2). The internal resistors are roughly 124k, 226k, 100k, and 50k (see Figure 2) giving output options of 3.5V, 4V, 4.5V, and 5V. The resistors are carefully matched to provide accurate divider ratios, but the absolute values can vary substantially from part to part. It is not a good idea to create a divider using an external resistor and one of the internal resistors unless the output voltage accuracy is not critical.

LTC1261

APPLICATIONS INFORMATION
Table 2. Output Voltages Using the Internal Resistor Divider
PIN CONNECTIONS ADJ to RADJ ADJ to RADJ, R0 to GND ADJ to RADJ, R1 to R0 ADJ to RADJ, R1 to GND ADJ to R1 ADJ to R0 ADJ to GND OUTPUT VOLTAGE 5V 4.5V 4V 3.5V 1.77V 1.38V 1.24V

There are some oddball output voltages available by connecting ADJ to R0 or R1 and shorting out some of the internal resistors. If one of these combinations gives you the output voltage you want, by all means use it! The internal resistor values are the same for the fixed output versions of the LTC1261 as they are for the adjust-

TYPICAL APPLICATIONS N
3.3V Input, 4.5V Output GaAs FET Bias Generator

VBAT 3.3V 1F SHUTDOWN 14 2 0.1F 3 C1 + VCC 13 SHDN 10k

12 C1 REG LTC1261 11 4 OUT C2+ 5 NC 8 C2 R1 R0 7 ADJ RADJ GND 6 10 9 100pF

0.1F

able. The output voltage can be trimmed, if desired, by connecting external resistance from the COMP pin to OUT or ground to alter the divider ratio. As in the adjustable parts, the absolute value of the internal resistors may vary significantly from unit to unit. As a result, the further the trim shifts the output voltage the less accurate the output voltage will be. If a precise output voltage other than one of the available fixed voltages is required, it is better to use an adjustable LTC1261 and use precision external resistors. The internal reference is trimmed at the factory to within 3.5% of 1.24V; with 1% external resistors the output will be within 5.5% of the nominal value, even under worst case conditions. The LTC1261 can be internally configured with nonstandard fixed output voltages. Contact the Linear Technology Marketing Department for details.

P-CHANNEL POWER SWITCH

4.5V BIAS

3.3F

GaAs TRANSMITTER

LTC1261 TA03

11

LTC1261
TYPICAL APPLICATIONS N
5V Input, 4V Output GaAs FET Bias Generator
P-CHANNEL POWER SWITCH VBAT SHUTDOWN 5V 1 2 1F 0.1F VCC SHDN 8 10k

VBAT = 8.4V (7 NiCd CELLS) SHUTDOWN 1 2 1F 0.1F VCC SHDN 8

1mV Ripple, 5V Input, 4V Output GaAs FET Bias Generator

P-CHANNEL POWER SWITCH VBAT SHUTDOWN 5V 1 2 1F 0.1F VCC SHDN 8 10k

12

U
4

7 C1+ REG LTC1261-4 6 3 OUT C2 GND COMP 5 100pF

4V BIAS

3.3F

GaAs TRANSMITTER

LTC1261 TA04

7 Cells to 1.24V Output GaAs FET Bias Generator

P-CHANNEL POWER SWITCH

10k

7 C1+ REG LTC1261 6 3 OUT C2 4 GND ADJ 5

1.24V BIAS

3.3F

GaAs TRANSMITTER

LTC1261 TA05

7 C1+ REG LTC1261-4 6 3 OUT C2 4 GND COMP 5 100pF

100H 10F

4V BIAS

10F

GaAs TRANSMITTER

LTC1261 TA06

LTC1261

TYPICAL APPLICATIONS N
High Supply Voltage, 5V Output GaAs FET Bias Generator
P-CHANNEL POWER SWITCH 8V VBAT 12V 1N4733A 5.1V 1F SHUTDOWN 14 2 0.1F 3 C1 + VCC 13 SHDN 10k

0.1F

Low Output Voltage Generator

5V 1F 1 VCC ADJ 2 0.1F C1+ LTC1261 3 C1 OUT GND 4 6 1N5817 5

100pF

12 C1 REG LTC1261 11 4 OUT C2+ 5 NC 8 C2 R1 R0 7 NC ADJ RADJ GND 6 10 9 100pF

5V BIAS

3.3F

GaAs TRANSMITTER

LTC1261 TA07

5V Supply Generator
3V VCC 7V 1F

RS

14 2 0.1F C1 + VCC ADJ 10 100pF

124k VOUT = VCC 10A (RS + 124k) = 0.5V (RS = 426k) 3.3F = 1V (RS = 476k)
LTC1261 TA10

9 C1 RADJ LTC1261 8 4 C2+ R1 3 5 C2 R0 OUT GND 6 7 11

NC NC 5V 5% AT 10mA

0.1F

3.3F
LTC1261 TA09

Minimum Parts Count 4V Generator

1 2 1F 0.1F

5V

VCC

SHDN

7 REG C1 + LTC1261-4 3 6 OUT C1 4 GND COMP 5

VOUT = 4V at 10mA

3.3F
LTC1261 TA12

13

LTC1261

TYPICAL APPLICATIONS N
This circuit uses the LTC1261CS8 to generate a 1.24V output at 20mA. Attached to this output is a 312 resistor to make the current/voltage conversion. 4mA through 312 generates 1.24V, giving a net 0V output. 20mA through 312 gives 6.24V across the resistor, giving a net 5V output. If the 4mA to 20mA source requires an operating voltage greater than 8V, it should be powered from a separate supply; the LTC1261 can then be powered from any convenient supply, 3V VS 8V. The Schottky diode prevents the external voltage from damaging the LTC1261 in shutdown or under fault conditions. The LTC1261s reference is trimmed to 3.5% and the resistor adds 1% uncertainty, giving 4.5% total output error.

1.24V Generator for 4mA-20mA to 0V-5V Conversion

4mA TO 20mA SENSOR

14

OPTIONAL INPUT PROTECTION DIODES

8V 1F 0V TO 5V 5% C1+ 2 0.1F 3

312 1% 1.24V

1 6 VCC OUT

+
1N5817

3.3F 5

LTC1261 ADJ GND 4 C1

LTC1261 TA11

LTC1261

PACKAGE DESCRIPTION

0.010 0.020 45 (0.254 0.508) 0.008 0.010 (0.203 0.254) 0 8 TYP

0.016 0.050 0.406 1.270

*DIMENSION DOES NOT INCLUDE MOLD FLASH. MOLD FLASH SHALL NOT EXCEED 0.006" (0.152mm) PER SIDE **DIMENSION DOES NOT INCLUDE INTERLEAD FLASH. INTERLEAD FLASH SHALL NOT EXCEED 0.010" (0.254mm) PER SIDE

0.010 0.020 45 (0.254 0.508) 0.008 0.010 (0.203 0.254)

0 8 TYP

0.016 0.050 0.406 1.270

*DIMENSION DOES NOT INCLUDE MOLD FLASH. MOLD FLASH SHALL NOT EXCEED 0.006" (0.152mm) PER SIDE **DIMENSION DOES NOT INCLUDE INTERLEAD FLASH. INTERLEAD FLASH SHALL NOT EXCEED 0.010" (0.254mm) PER SIDE

Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights.

Dimensions in inches (millimeters) unless otherwise noted.

S8 Package 8-Lead Plastic Small Outline (Narrow 0.150)

(LTC DWG # 05-08-1610)
0.189 0.197* (4.801 5.004) 8 7 6 5

0.228 0.244 (5.791 6.197)

0.150 0.157** (3.810 3.988)

1 0.053 0.069 (1.346 1.752)

0.004 0.010 (0.101 0.254)

0.014 0.019 (0.355 0.483)

0.050 (1.270) TYP

SO8 0996

S Package 14-Lead Plastic Small Outline (Narrow 0.150)

(LTC DWG # 05-08-1610)
0.337 0.344* (8.560 8.738) 14 13 12 11 10 9 8

0.228 0.244 (5.791 6.197)

0.150 0.157** (3.810 3.988)

0.053 0.069 (1.346 1.752)

0.004 0.010 (0.101 0.254)

0.014 0.019 (0.355 0.483)

0.050 (1.270) TYP

S14 0695

15

LTC1261

TYPICAL APPLICATION
5V Input, 0.5V Output GaAs FET Bias Generator

VBAT SHUTDOWN 5V 1 2 1F 0.1F VCC SHDN 8 42.2k 10k

RELATED PARTS
PART NUMBER
LTC1550/LTC1551 LTC1429 LT1121

DESCRIPTION
Low Noise Switched Capacitor Regulated Voltage Inverter Clock Synchronized Switched Capacitor Regulated Voltage Inverter Micropower Low Dropout Regulators with Shutdown

16

Linear Technology Corporation

1630 McCarthy Blvd., Milpitas, CA 95035-7417 q (408) 432-1900 FAX: (408) 434-0507q TELEX: 499-3977 q www.linear-tech.com

U
4

P-CHANNEL POWER SWITCH

7 C1+ REG LTC1261 6 3 OUT C2 GND ADJ 5 100pF 12.4k

0.5V BIAS 5.5%

3.3F

GaAs TRANSMITTER

LTC1261 TA08

COMMENTS
GaAs FET Bias with Linear Regulator 1mV Ripple GaAs FET Bias 0.4V Dropout Voltage at 150mA, Low Noise, Switched Capacitor Regulated Voltage Inverter

1261fa LT/TP 0198 REV A 4K PRINTED IN USA

LINEAR TECHNOLOGY CORPORATION 1994