16 PSK

ELECTRONIC COMMUNICATIONS SYSTEMS
PART 12-4
Fall 2001
ENZO PATERNO
DIGITAL COMMUNICATIONS
Fall 2001
ENZO PATERNO
PHASE SHIFT
KEYING
Fall 2001
ENZO PATERNO
EIGHT PHASE SHIFT KEYING (8-PSK) M-ARY CODING SCHEME WITH M = 8, N = 3 EIGHT OUTPUT PHASES ARE POSSIBLE THE INPUT BINARY DATA IS COMBINED INTO GROUPS OF 3 (N = 3) BITS CALLED TRIBITS
TRIBIT CODE: 000 = PHASE 1, 001 = PHASE 2, 010 = PHASE 3 011 = PHASE 4, 100 = PHASE 5, 101 = PHASE 6 110 = PHASE 7, 111 = PHASE 8 1 SYMBOL = 1 PHASE = 3 BITS
BAUD RATE = 1/3 BIT RATE (SYMBOLS PER SEC) (BITS PER SEC)
Fall 2001
ENZO PATERNO
8-PSK MODULATOR
PULSE AMPLITUDE MODULATED SIGNAL (4 LEVELS)
2-input DAC
BIT SPLITTER (SERIAL TO PARALLEL)
fb 3
Fall 2001
2-input DAC
PULSE AMPLITUDE MODULATED SIGNAL (4 LEVELS)
ENZO PATERNO
8-PSK MODULATOR
I CHANNEL TRUTH TABLE
Q CHANNEL TRUTH TABLE
PAM SIGNAL (4 LEVELS)
I, Q DETERMINE POLARITY; 0 = - , 1 = +
C , C DETERMINE THE LEVEL; 1 = 1.307v, 0 = 0.541v

Fall 2001
2 LEVELS + 2 POLARITIES GIVE 4 CONDITIONS ENZO PATERNO

6
8-PSK GENERATION: TRIBIT = 000
0.541 sin(2fct )
0
000 0 - 0.541v
1 - 1.307v
1.307 cos(2fct )
NOTE: BECAUSE C , C NOT THE SAME, I-CHANNEL PAM WILL NEVER EQUAL Q-CHANNEL PAM
Fall 2001 7
ENZO PATERNO
8-PSK GENERATION: OUTPUT PHASES TRIBIT CODE: 000
0.541 sin(ct ) 1.307 cos(ct ) 1.41 sin(ct 112 .5 )

PROOF:
sin( X Y ) sin X cosY cos X sin Y
1.41sin(2fct 112.5 ) 1.41sin(2fct ) cos( 112.5) 1.41cos(2fct ) sin(112.5) 1.41(.383) sin(2fct ) 1.41(.924) cos(2fct ) 0.541sin(2fct ) 1.307 cos(2fct )
0 0 0 ==> -112.5 degrees
Fall 2001
ENZO PATERNO
8-PSK GENERATION: OUTPUT PHASES

TRIBIT CODE BETWEEN ADJACENT PHASES FOLLOWS THE GRAYCODE (RESULTS IN ONLY A SINGLE BIT ERROR FOR UNDESIRED PHASE SHIFTS)
Fall 2001
ENZO PATERNO
FOR QPSK: 4 OUTPUT PHASES (+45, +135, -45, -135) THE SEPARATION BETWEEN ADJACENT PHASORS IS 360/4 = 90 degrees. FOR 8-PSK: 8 OUTPUT PHASES. THE SEPARATION BETWEEN PHASES IS 360/8 = 45 degrees. A 8-PSK SIGNAL CAN UNDERGO A +/- 22.5 degrees PHASE SHIFT DURING TRANSMISSION AND STILL RETAIN ITS INTEGRITY.
Fall 2001
ENZO PATERNO
10
FOR 8-PSK, EACH PHASOR IS EQUAL IN MAGNITUDE (1.41v) THE TRIBIT CODE INFORMATION IS CONTAINED ONLY IN THE PHASE OF THE SIGNAL
Fall 2001
ENZO PATERNO
11
OUTPUT PHASE VERSUS TIME FOR 8-PSK MODULATOR

Fall 2001
ENZO PATERNO
12
BANDWITH CONSIDERATION OF 8-PSK C I SERIAL Q PARALLEL I or Q or C tb tb tb tb
1 BIT RATE BEFORE SPLITTER = fb (SERIAL) tb 1 fb REPETITION RATE BEFORE SPLITTER fr (SERIAL) 2tb 2 1 fb BIT RATE AFTER SPLITTER = (PARALLEL) 3tb 3 1 f b REPETITION RATE AFTER SPLITTER fr (PARALLEL) 2 ( 3 ) t b 6 Fall 2001 13 ENZO PATERNO
BANDWITH CONSIDERATION OF 8-PSK
fb 3
fb fr 6
Fall 2001
ENZO PATERNO
14
8-PSK GENERATION: BAUD RATE
FOR 8-PSK, THERE IS ONE CHANGE IN PHASE AT THE OUTPUT FOR EVERY THREE DATA INPUT BITS. (A GROUP OF THREE BITS = 1 PHASE = 1 SYMBOL) THUS, THE BAUD RATE = 1/3 BIT RATE =
fb 3
Fall 2001
ENZO PATERNO
15
v8 psk (t ) sin(2fct )X sin(2frt ) fc REFERENCE CARRIER FREQUENCY

X = +/- 1.307 OR +/- 0.541
fb fr 6
REPETITION RATE (FUNDAMENTAL FREQUENCY OF I or Q or C CHANNEL BITS) IT IS 1/6 THE BIT RATE
1 1 (sin X )(sinY ) cos(X Y ) cos(X Y ) 2 2
X X vpsk (t ) cos2 ( fc fr )t cos2 ( fc fr )t 2 2

LOWER SIDE FREQUENCY
Fall 2001
UPPER SIDE FREQUENCY

16
ENZO PATERNO
B
LSB USB
fc fr
LSF
fb fr 6
fb fr 6
fc
DSB-SC MODULATION
fc fr
USF
fb fb B 2 fr 2 6 3
Fall 2001
ENZO PATERNO
17
EXAMPLE FOR AN 8-PSK MODULATOR WITH A CARRIER FREQUENCY OF 70 MHz AND AN INPUT BIT RATE OF 10 Mbps, DETERMINE a) THE LSF b) USF c) B d) BAUD RATE
fc 70 MHz fb 10 MHz fb fr ; fb 6 fr 6 10 MHz fr 1.667 MHz 6 LSF fc fr 70 1.667 68.333 MHz USF fc fr 70 1.667 71.667 MHz fb B 3.33 MHz 3 Fall 2001 18
ENZO PATERNO
EXAMPLE
3.33 MHz
LSB USB
1.667 MHz
1.667 MHz
68.333 MHz 70 MHz

LSF
71.667 MHz
USF
BAUD RATE = 1/3 BIT RATE = 3.33 MEGABAUD
Fall 2001
ENZO PATERNO
19
8-PSK RECEIVER
Fall 2001
ENZO PATERNO
20
SIXTEEN PHASE SHIFT KEYING (16-PSK) M-ARY CODING SCHEME WITH M = 16, N = 4 SIXTEEN OUTPUTS PHASES ARE POSSIBLE THE INPUT BINARY DATA IS COMBINED INTO GROUPS OF 4 (N = 4) BITS CALLED QUADBITS
QUADBIT CODE: 0000 = PHASE 1 .. 1111 = PHASE 16,

1 SYMBOL = 1 PHASE = 4 BITS BAUD RATE = 1/4 BIT RATE (SYMBOLS PER SEC) (BITS PER SEC)
WITH 16-PSK, THE ANGULAR SEPARATION BETWEEN AJDACENT PHASES IS 360/16 = 22.5 degrees. FOR INTEGRITY TO REMAIN, PHASE SHIFT max = +/- 11.25 degrees Fall 2001 21 ENZO PATERNO
Fall 2001
ENZO PATERNO
22

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ELECTRONIC COMMUNICATIONS SYSTEMS

I CHANNEL TRUTH TABLE

Q CHANNEL TRUTH TABLE

PAM SIGNAL (4 LEVELS)

C , C DETERMINE THE LEVEL; 1 = 1.307v, 0 = 0.541v

2 LEVELS + 2 POLARITIES GIVE 4 CONDITIONS ENZO PATERNO

8-PSK GENERATION: TRIBIT = 000

8-PSK GENERATION: OUTPUT PHASES TRIBIT CODE: 000

0.541 sin(ct ) 1.307 cos(ct ) 1.41 sin(ct 112 .5 )

sin( X Y ) sin X cosY cos X sin Y

8-PSK GENERATION: OUTPUT PHASES

8-PSK GENERATION: OUTPUT PHASES

8-PSK GENERATION: OUTPUT PHASES

8-PSK GENERATION: OUTPUT PHASES

OUTPUT PHASE VERSUS TIME FOR 8-PSK MODULATOR

BANDWITH CONSIDERATION OF 8-PSK C I SERIAL Q PARALLEL I or Q or C tb tb tb tb

BANDWITH CONSIDERATION OF 8-PSK

8-PSK GENERATION: BAUD RATE

BANDWITH CONSIDERATION OF 8-PSK

v8 psk (t ) sin(2fct )X sin(2frt ) fc REFERENCE CARRIER FREQUENCY

1 1 (sin X )(sinY ) cos(X Y ) cos(X Y ) 2 2

X X vpsk (t ) cos2 ( fc fr )t cos2 ( fc fr )t 2 2

UPPER SIDE FREQUENCY

BANDWITH CONSIDERATION OF 8-PSK

68.333 MHz 70 MHz

BAUD RATE = 1/3 BIT RATE = 3.33 MEGABAUD

QUADBIT CODE: 0000 = PHASE 1 .. 1111 = PHASE 16,

16-PSK GENERATION: OUTPUT PHASES

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