s5-948 Overview

SIMATIC S5
S5-135U/155U CPU 922/CPU928/CPU 928B/CPU 948
List of Operations
Order No. 6ES5 997-3UA22, Release 03
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Copyright Siemens AG 1993 All Rights Reserved

Order No.: 6ES5 997-3UA22 Order from: Elektronikwerk Karlsruhe Printed in the Federal Republic of Germany
Contents
Page
Explanatory Notes on the List of Operations Explanatory Notes on the Operands Explanatory Notes on the Formal Operands (Block Parameters) Basic Operations
Boolean Logic Operations Set/Reset Operations/Binary Load Operations Transfer Operations Timer Operations Counter Operations Arithmetic Operations Comparison Operations Block Call Operations Block End Operations Null Operations Stop Operation Display Construction Operations
1 3 7 10
10 16 20 28 34 36 38 42 48 52 54 54 54
Supplementary Operations
Logic Operations Digital Operations Bit Test Operations Set/Reset Operations Timer and Counter Operations Load and Transfer Operations Conversion Operations Shift and Rotate Operations Jump Operations Other Operations
56
56 56 58 62 66 70 74 76 78 80
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Page
System Operations
Load and Transfer Operations Arithmetic Operations Jump Operations Other Operations Set Operations Register to Register Transfer Operations Load, Transfer and Arithmetic Operations with the Base Address Register Access to local, word-oriented memory Test/set Busy location (global area) Access to global, byte-oriented memory Access to global, word-oriented memory Open page Test/set Busy location (page area) Access to byte-oriented pages Access to word-oriented pages
86
86 94 96 96 100 102 102 106 106 108 110 110 110 112 114
Machine Code Listing Alphabetical Index of Operations

(with Machine Code)
116 131 144 146

146 148 150 154 156
Explanatory Notes on the Condition Codes List of Organization Blocks

OBs for Program Processing OBs for Start-up Procedures OBs for Handling Controller Errors in the CPU 922/928/928B OBs for Handling Controller Errors in the CPU 948 OBs with Special Functions
II
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Explanatory Notes on the List of Operations

Abbreviations ACCU 1 ACCU 2 ACCU 3 ACCU 4 ACCU 1-H ACCU 2-H ACCU 3-H ACCU 4-H ACCU 1-L ACCU 2-L ACCU 3-L ACCU 4-L Condition codes CC0/CC1 OV Explanations The four 32-bit accumulators
The high word of the four 32-bit accumulators
The low word of the four 32-bit accumulators
Condition codes 0/1 (see pages 119, 120) Overflow; this condition code is set e.g. if the number range is exceeded during arithmetic operations. Stored overflow; this condition code is set if at least one arithmetic operation causes an overflow (for detection of arithmetic errors). The condition code is set/reset depending on the statement. Condition code is set Condition code is reset Condition code is not affected (see Explanatory Notes on the Condition Codes) Symbolic label with up to 4 characters. The first character must be a letter (see page 7ff).
OS
Y 1 0 N
Formal operand
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Abbreviations PI
Explanations Process Image memory areas for data that are read from the I/Os and/or transferred to the I/Os. The I/O image remains in these memory areas during one program cycle and is updated prior to the next. The binary logic and set/reset operations always use the PI. Process Image of Inputs/Outputs Binary Result of Logic Operation (1 bit) Command execution depends on the RLO Y Y The statement is executed only if RLO = "1". The statement is executed only on the leading edge of the RLO (RLO changes from "0" to "1"). The statement is executed only after the RLO changes from "1" to "0" (falling edge). The statement is always executed. Command affects the RLO Y RLO is set to "1" or "0". Please refer to the function description of the corresponding statement for explanation on how the new RLO is formed. RLO is set to "1". RLO does not change. The RLO does not change. The RLO cannot be combined any further. If a command which reloads the RLO is followed by a binary logic operation, the scan result is reloaded and a new RLO is started. The RLO can be combined further. Statement List method of representation in STEP 5.
PII/PIQ RLO RLO-dependent command flow?
N RLO reset?
1 N RLO reloaded? Y
N STL
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Explanatory Notes on the Operands

Permissible Value Range for Operands CPU BN C D DB Byte constant (fixed-point no.) Counter Data bit Data block all all all 922/ 928/ 928B 948 DD DH DL DR DW DX Data double word Double word constant (hexadecimal) Data word (left-hand byte) Data word (right-hand byte) Data word (in a DB or DX) Data block (extension) all all1) all all all 922/ 928 Range -128 to +127 0 to 255 0.0 to 255.15 3 to 255 2 to 255 0 to 254 0 to FFFF FFFF 0 to 255 0 to 255 0 to 255 1 to 255 32 32 8 8 16 8 1 Size in Bits
Abbr Description
928B/ 3 to 255 948 F FB FD FW FX Flag Function block Flag double word Flag word Function block (extension) all all all all all 0.0 to 255.7 0 to 255 0 to 252 0 to 254 0 to 255 1 32 16 -
1) CPU 922 from version 09

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Abbr Description
Permissible Value Range for Operands CPU Range 0 to 255 0.0 to 127.0 0 to 127 0 to 124 0 to 126 0 to 255 0 to 999 -32768 to +32767 0,1701412 .10 39 to 0,1469368 .10 -38 0 to FFFF Arbitrary bit pattern ASCII characters 0.0 to 999.3 0 to 255 (per byte) 1 to 39
Size in Bits 8 1 8 32 16 8 16 16 32
FY I IB ID IW KB KC KF KG
Flag byte Input (in PII) Input byte (in PII) Input double word (in PII) Input word (in PII) Constant (1 byte) Constant (count) Constant (fixed-point number) Constant (floating-point number) Constant (hexadecimal code) Constant (2-byte bit pattern) Constant (2 characters) Constant (time) Constant (2 bytes) Organization block Operating system special function
all all all all all all all all all
KH KM KS KT KY OB OB
all all all all all all
16 16 16 16 16 -
922/ 928/ 110 to 255 928B 948 121 to 255 0 to 254
OW
Word of the extended I/O area (without PII/PIQ update) Byte of the extended I/O area (without PII/PIQ update)
all
16
OY
all
0 to 255
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Abbr Description
Permissible Value Range for Operands CPU Range 0 to 255
Size in Bits 16
PB PW
Program block Peripheral word of - digital inputs (direct reading of the PII) - analog inputs/digital inputs (without PII update) - digital outputs (with PIQ update) - analog outputs/digital outputs (without PIQ update) Peripheral byte of - digital inputs (direct reading of the PII) - analog inputs/digital inputs (without PII update) - digital outputs (with PIQ update) - analog outputs/digital outputs (without PIQ update Output (with PIQ update) Output byte (with PIQ update) Output double word (with PIQ update) Output word (with PIQ update) Interface data area Extended interface data area System data area Extended system data area
all all
0 to 126 128 to 254 0 to 126 128 to 254 all 0 to 127 128 to 255 0 to 127 128 to 255 all all all all all all all all 0.0 to 127.0 0 to 127 0 to 124 0 to 126 0 to 255 0 to 255 0 to 255 0 to 255 1 8 32 16 16 16 16 16 8
PY
Q QB QD QW RI RJ RS RT
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Abbr Description
Permissible Value Range for Operands CPU Range n/a n/a 0.0 to 1023.7 0.0 to 4095.7 0 to 255 n/a n/a 0 to 1020 0 to 4092 n/a n/a 0 to 1022 0 to 4094 n/a n/a 0 to 1023 0 to 4095 0 to 255
Size in Bits
Flag, additional (S flag)
922 928 928B 948
SB SD
Sequence block Flag double word, additional (S flag double word)
all 922 928 928B 948
32
SW
Flag word, additional (S flag word)
922 928 928B 948
16
SY
Flag byte, additional (S flag byte)
922 928 928B 948
Timer
all
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Explanatory Notes on the Formal Operands (Block Parameters)

A maximum of 126 different formal operands (nos. 1 to 126) can be programmed per FB/FX. Parameter Type I, Q Data Type BI BY W D for an operand with bit address for an operand with byte address for an operand with word address for an operand with double word address for a binary pattern (16 bits) for 2-byte serial absolute value numbers from 0 to 255 for a 4 digit hexadecimal number for a character (max. 2 alphanum. characters) for a time in BCD with time base 1.0 to 999.3 for a count value in BCD from 0 to 999 for a fixed-point number from -32768 to +32767 for a floating-point number from 0,1701412 . 10 39 to 0,1469368 . 10 -38 Actual Operands Permitted I, Q, F IB, QB, FY, DL, DR, PY, OY IW, QW, FW, DW, PW, OW ID, QD, FD, DD
KM KY
Constants
KH KS
KT
KC
KF
KG
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Parameter Type B
Data Type Type specification not permitted
Actual Operands Permitted DB Data blocks: statement C DB is executed Function blocks (permitted without parameters only) are called unconditionally: JU FB Organization blocks are called unconditionally: JU OB Program blocks are called unconditionally : JU PB Sequence blocks are called unconditionally: JU SB
FB
OB
PB
SB
T C
Type specification not permitted Type specification not permitted
T C
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Intentionally blank!
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Basic Operations
Permissible for all blocks
OperaOperands tion STL C C 1 Condition codes affected C C 0 O V RLO 1 dep. 2 affect. O 3 reload S 1 2 3 Execution = Operation with this CPU 922 CPU 928 times in s not possible CPU CPU 928B CPU 948 Function
Boolean Logic Operations

All logic operations generate a result (RLO). The first RLO in a string of logic operations generates the new RLO from the signal status scanned. All subsequent logic operations generate the new RLO from the signal status scanned, and gate it with the old RLO. The string of logic operations is terminated by an operation that reloads the RLO (e.g., set/reset operation). A A A I 0.0 to 127.7 N N N N N N N N N N N N N N N N N N N N N N N N N N N N N N N N N N N N N N N N N Y N Y N Y N Y N Y N Y N Y N Y N Y N Y N N N N N N N N N N 37-38 20-25 19-23 20-25 20-25 29 0.9 0.9 0.9 0.9 3.4 0.57 0.57 0.57 0.57 20-25 20-25 20-25 0.9 0.9 0.9 0.57 0.57 0.57 3.7 0.39 0.77 0.18 0.18 0.18 0.18 Scan S flag for "1" and combine with RLO through logic AND 0.18 0.18 0.18 Scan input for "1" and combine with RLO through logic AND Scan output for "1" and combine with RLO through logic AND Scan flag for "1" and combine with RLO through logic AND
Q 0.0 to 127.7 F 0.0 to 255.7 S 0.0 to 1023.7
A S 0.0 to 4095.7 A A A AN AN D 0.0 to 255.15 T 0 to 255 C 0 to 255 I 0.0 to 127.7
Scan a bit in the data block (DB/DX) for "1" and combine with RLO through logic AND Scan a time for "1" and combine with RLO through logic AND Scan a counter for "1" and combine with RLO with RLO through logic AND Scan input for "0" and combine with RLO through logic AND Scan output for "0" and combine with RLO through logic AND
Q 0.0 to 127.7
10
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Basic Operations
Boolean Logic Operations (continued)

AN F 0.0 to 255.7 S 0.0 to 1023.7 AN S 0.0 to 4095.7 AN AN AN O O O D 0.0 to 255.15 T 0 to 255 C 0 to 255 I 0.0 to 127.7 N N N N N N N N N N N N N N N N N N N N N N N N N N N N N N N N N N N N N N N N N Y N Y N Y N Y N Y N Y N Y N Y N Y N Y N N N N N N N N N N 35-38 28 3.4 36-41 22 18-20 19-21 19-21 19-21 29 0.9 0.9 0.9 0.9 0.9 3.4 0.57 0.57 0.57 0.57 0.57 3.7 0.39 0.77 Scan S flag for "1" and combine with RLO through logic OR 0.39 0.77 0.18 0.18 0.18 0.18 0.18 N N N N N N N N N Y N Y N N 20-25 0.9 0.57 3.7 Scan S flag for "0" and combine with RLO through logic AND 0.18 Scan flag for "0" and combine with RLO through logic AND
Scan a bit in the data block (DB/DX) for "0" and combine with RLO through logic AND Scan a time for "0" and combine with RLO through logic AND Scan a counter for "0" and combine with RLO through logic AND Scan input for "1" and combine with RLO through logic OR Scan output for "1" and combine with RLO through logic OR Scan flag for "1" and combine with RLO through logic OR
Q 0.0 to 127.7 F 0.0 to 257.7 S 0.0 to 1023.7
O S 0.0 to 4095.7 O D 0.0 to 255.15
Scan a bit in the data block (DB/DX) for "1" and combine with RLO through logic OR
12
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Basic Operations

O O ON ON ON T 0 to 255 C 0 to 255 I 0.0 to 127.7 N N N N N N N N N N N N N N N N N N N N N N N N N N N N N N N N N N N N N N N N N N N N N Y N Y N Y N Y N Y N Y N Y N Y N Y N Y N Y N N N N N N N N N N Y 35-37 19-21 16-20 12-14 28 0.9 0.9 0.8 3.4 0.57 0.57 0.57 18-21 17-20 18-21 18-21 18-21 0.9 0.9 0.9 0.9 0.9 0.57 0.57 0.57 0.57 0.57 3.7 0.39 0.77 0.18 0.18 0.18 Scan S flag for "0" and combine with RLO through logic OR 0.18 0.18 0.18 0.18 0.18 Scan a time for "1" and combine with RLO through logic OR Scan a counter for "1" and combine with RLO through logic OR Scan input for "0" and combine with RLO through logic OR Scan output for "0" and combine with RLO through logic OR Scan flag for "0" and combine with RLO through logic OR
Q 0.0 to 127.7 F 0.0 to 255.7 S 0.0 to 1023.7
ON S 0.0 to 4095.7 ON ON ON O D 0.0 to 255.15 T 0 to 255 C 0 to 255 -
Scan a bit in the data block (DB/DX) for "0" and combine with RLO through logic OR Scan a time for "0" and combine with RLO through logic OR Scan a counter for "0" and combine with RLO through logic OR Combine AND operations through logic OR
14
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Basic Operations

A( O( ) N N N N N N N N N N N N N Y N Y N Y Y Y N 20 21 20-22 1.2 1.2 1.2 0.57 0.57 0.57 0.18 0.18 0.18 Combine expressions enclosed with parentheses (8 levels) through logic AND Combine expressions enclosed with parentheses (8 levels) through logic OR Right parenthesis (End of operation in parentheses)
Set/Reset Operations, Binary

S S S I 0.0 to 127.7 N N N N N N N N N N N N N N N N N N N N N N N N N N N N N N N N Y Y Y Y Y Y Y Y N N N N N N N N Y Y Y Y Y Y Y Y 35-37 18-22 18-22 28 1.2 1.2 0.63 0.63 0.63 19-21 19-21 19-21 1.2 1.2 1.2 0.63 0.63 0.63 3.9 The S flag is set to "1" if the RLO is "1" S 0.0 to 4095.7 S R R D 0.0 to 255.15 I 0.0 to 127.7 0.48 0.77 0.32 0.32 The bit in the data block (DB/DX) is set to "1" if the RLO is "1" The input of the process image is reset to "0" if the RLO is "1" The output of the process image is reset to "0" if the RLO is "1" 0.32 0.32 0.32 The input of the process image is set to "1" if the RLO is "1" The output of the process image is set to "1" if the RLO is "1" The flag is set to "1" if the RLO is "1"
Q 0.0 to 127.7 F 0.0 to 255.7 S 0.0 to 1023.7
Q 0.0 to 127.7
16
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Basic Operations
Set/Reset Operations, Binary (continued)

R F 0.0 to 127.7 S 0.0 to 1023.7 R S 0.0 to 4095.7 R = = = D 0.0 to 255.15 I 0.0 to 127.7 N N N N N N N N N N N N N N N N N N N N N N N N N N N N N N N N Y Y N N Y Y Y Y Y Y Y Y 37 29 3.4 33-38 20 20 20 27 1.2 1.2 1.2 3.4 0.63 0.63 0.63 3.9 The value of the RLO is assigned to the S flag S 0.0 to 4095.7 = D 0.0 to 255.15 N N N N 0.48 0.77 The value of the RLO is assigned to the bit in the data block (DB/DX) 0.48 0.77 0.32 0.32 0.32 The bit in the data block (DB/DX) is reset to "0" if the RLO is "1" The value of the RLO is assigned to the input in the process image The value of the RLO is assigned to the output in the process image The value of the RLO is assigned to the flag N N N N N N N N Y Y N N Y Y 18-22 1.2 0.63 3.9 The S flag is reset to "0" if the RLO is "1" 0.32 The flag is reset to "0" if the RLO is "1"
N N N N N N N N
Q 0.0 to 127.7 F 0.0 to 255.7 S 0.0 to 1023.7
18
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Basic Operations
Load Operations
The original contents of ACCU 1 are passed on to ACCU 2 before the byte, word or double word addressed is loaded into ACCU 1. During byte and word operations, the high bits (not loaded) of ACCU 1 are deleted (bits 8 to 31 for byte operations, bits 16 to 31 for word operations). If you use ACCU 3 and ACCU 4, you must insert the "ENT" operation from the supplementary operation set to restore the accumulator contents. L L IB IW 0 to 127 0 to 126 N N N N N N N N N N N N N N 22 22 12 13 0.81 0.94 0.18 0.50 Load an input byte from the PII into ACCU 1-L Load an input word from the PII into ACCU 1-L: byte n bits 8-15, byte n+1 bits 0-7 Load an input double word from the PII into ACCU 1: byte n bits 24-31, byte n+1 bits 16-23, byte n+2 bits 8-15, byte n+3 bits 0-7 Load an output byte from the PIQ into ACCU 1-L Load an output word from the PIQ into ACCU 1-L: byte n bits 8-15, byte n+1 bits 0-7 Load an output double word from the PIQ into ACCU 1: byte n bits 24-31, byte n+1 bits 16-23, byte n+2 bits 8-15, byte n+3 bits 0-7 Load a flag byte into ACCU 1-L Load a flag word into ACCU 1-L: byte n bits 8-15, byte n+1 bits 0-7
ID
0 to 244
N N
24
16
1.6
0.71
L L
QB 0 to 127 QW 0 to 126
N N
N N
N N
N N
N N N N
N N
21 22
12 12
0.81 0.94
0.18 0.50
QD 0 to 124
N N
24
16
1.6
0.71
L L
FY
0 to 255
N N
N N
N N
N N
N N N N
N N
22 22
12 12
0.81 0.94
0.18 0.50
FW 0 to 254
20
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Basic Operations
Load Operations (continued)

L FD 0 to 252 N N N N N N N 24 16 1.6 0.71 Load a flag double word into ACCU 1: byte n bits 24-31, byte n+1 bits 16-23, byte n+2 bits 8-15, byte n+3 bits 0-7
SY 0 to 1023 L SY 0 to 4095 SW 0 to 1022 L SW 0 to 4094 SD 0 to 1020 L SD 0 to 4092 DH 0 to FFFF FFFF DL 0 to 255
N N N N N N
N N N N N N
N N N N N N
N N N N N N
N N N N N N N N N N N N
N N N N N N 20.11)
2.4 Load an S flag byte into ACCU 1-L 0.39 2.5 0.59 3.1 0.77 Load an S flag word into ACCU 1-L: Byte n bits 8-15,byte n+1 bits 0-7
Load an S flag double word into ACCU 1: byte n bits 24-31, byte n+1 bits 16-23, byte n+2 bits 8-15, byte n+3 bits 0-7 Load a constant (hexadecimal code as double word) into ACCU 1 Load the left byte of a data word of the current data block into ACCU 1-L
N N
15
1.7
0.57
N N
24
14
1.7
0.50
1)
Operation possible from version 09 onwards.
22
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Basic Operations
OperaOperands tion STL C C 1 Condition codes affected C C 0 O V RLO 1 dep. 2 affect. O 3 reload S 1 2 3 Execution = Operation with this CPU 922 CPU 928 time in s not possible CPU CPU 928B CPU 948 Function

L L L L L DR 0 to 255 DW 0 to 255 DD 0 to 254 KB 0 to 255 N N N N N N N N N N N N N N N N N N N N N N N N N N N N N N N N N N N 24 24 25 19 20 14 14 17 8 14 1.7 1.5 2.0 0.63 1.2 0.50 0.50 0.68 0.18 0.39 Load the right byte of a data word of the current data block into ACCU 1-L Load a data word of the current data block into ACCU 1-L Load a flag double word into ACCU 1: word n bits 16-31, word n+1 bits 0-7 Load a constant (1-byte number) into ACCU 1-L Load a constant (count in BCD) into ACCU 1-L Load a constant (fixed-point number) into ACCU 1-L Load a constant (floating point number) into ACCU 1-L Load a constant (hexadecimal code) into ACCU 1-L Load a constant (bit pattern) into ACCU 1-L
KC 0 to 999 KF -32768 to +32767
N N
20
14
1.2
0.39
L L
KG (see page 4) N KH 0 to FFFF KM bit pattern, 16 bit KS (2 ASCII characters) N
N N
N N
N N
N N N N
N N
21 20
15 14
1.7 1.2
0.57 0.39
N N
20
14
1.2
0.39
N N
20
14
1.2
0.39
Load a constant (2 characters in ASCII format) into ACCU 1-L Load a constant time (time in BCD) into ACCU 1-L
KT KY
0.0 to 999.3 N 2 bytes N 0 to 255 each
N N
20
14
1.2
0.39
N N
20
14
1.2
0.39
Load a constant (2-byte number) into ACCU 1-L
24
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Basic Operations

L PY 0 to 255 N N N N N N N 30 1) 31 1) 301) 311) 16 1) 1.4 1) 2.1 1) 1.4 1) 2.1 1) 1.7 1)
1)
Load a peripheral byte from the digital/analog inputs into ACCU 1-L Load a peripheral word from the digital/analog inputs into ACCU 1-L: byte n bits 8-15, byte n+1 bits 0-7 Load a byte of the extended I/O area into ACCU 1-L Load a word of the extended I/O area into ACCU 1-L: byte n bits 8-15, byte n+1 bits 0-7 Load a time in binary code into ACCU 1-L Load a count in binary code into ACCU 1-L Load a time in BCD into ACCU 1-L (including binary-BCD conversion) Load a count in BCD into ACCU 1-L (including binary-BCD conversion)
PW 0 to 254
N N
211)
2.69
OY 0 to 255
N N
161)
1.7 1) 2.7 1)
OW 0 to 254
N N
211)
L L LC LC
T C T C
0 to 255 0 to 255 0 to 255 0 to 255
N N N N
N N N N
N N N N
N N N N
N N N N N N N N
N N N N
25 24 38 35
14 14 16 15
0.81 0.81 3.7 3.7
0.30 0.30 0.39 0.39
1)
Execution time for single processing operation and for immediate bus access in multiprocessing operations. I/Os acknowledge within 0.1 s or proportionally longer execution time for longer acknowledgement time.
26
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Basic Operations
Transfer Operations
The contents of ACCU 1 are transferred to the operand specified. T IB 0 to 127 N N N 0 N N N 15 11 0.75 0.18 Transfer the contents of ACCU 1-L (bits 0-7) to an input byte (into the PII) Transfer the contents of ACCU 1-L (bits 0-7) to an input word (into PII): bits 8-15 byte n, bits 0-7 byte n+1 Transfer the contents of ACCU 1 to an input double word (into the PII): bits 24-31 byte n, bits 16-23 byte n+1, bits 8-15 byte n+2, bits 0-7 byte n+3 Transfer the contents of ACCU 1-L (bits 0-7) to an output byte (into the PIQ) Transfer the contents of ACCU 1-L (bits 0-7) to an output word (into the PIQ): bits 8-15 byte n, bits 0-7 byte n+1 Transfer the contents of ACCU 1 to an output double word (into the PIQ): bits 24-31 byte n, bits 16-23 byte n+1, bits 8-15 byte n+2, bits 0-7 byte n+3 Transfer the contents of ACCU 1-L to a flag byte (bits 0-7) Transfer the contents of ACCU 1-L to a flag word: bits 8-15 byte n, bits 0-7 byte n+1 Transfer the contents of ACCU 1 to a flag double word: bits 24-31 byte n, bits 16-23 byte n+1, bits 8-15 byte n+2, bits 0-7 byte n+3
IW
0 to 126
N N
15
11
0.88
0.41
ID
0 to 124
N N
20
15
1.9
0.59
QB 0 to 127
N N
15
11
0.75
0.18
QW 0 to 126
N N
15
11
0.88
0.41
QD 0 to124
N N
20
15
1.9
0.59
T T
FY
0 to255
N N
N N
N N
0 0
N N N N
N N
15 15
11 11
0.75 0.88
0.18 0.41
FW 0 to 254
FD
0 to 252
N N
20
15
1.9
0.59
28
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Basic Operations
Transfer Operations (continued)

SY T SY 0 to 4095 N N N N N N N N N N N N N N N N N N N N N N N N 0 0 0 0 0 0 0 0 N N N N N N N N N N N N N N N N N N N N N N N N 22 22 22 15 14 14 1.5 1.4 1.4 3.4 0.59 0.68 0.68 0.41 2.3 0.41 0.39 0 to 1023 N N N 0 N N N 2.3 Transfer the contents of ACCU 1-L to an S flag byte (bits 0-7)
SW 0 to 1022 T SW 0 to 4094 SD 0 to 1020 T SD 0 to 4092 T T T DL 0 to 255
Transfer the contents of ACCU 1-L to an S flag word: bits 8-15 byte n, bits 0-7 byte n+1 Transfer the contents of ACCU 1 to an S flag double word: bits 24-31 byte n, bits 16-23 byte n+1, bits 8-15 byte n+2, bits 0-7 byte n+3 Transfer the contents of ACCU 1-L (bits 0-7) to a data word (left byte) in a DB/DX Transfer the contents of ACCU 1-L (bits 0-7) to a data word (right byte) in a DB/DX Transfer the contents of ACCU 1-L (bits 0-15) to a data word in a DB/DX Transfer the contents of ACCU 1 to a data double word in a DB/DX: bits 16-31 word n, bits 0-15 word n+1
DR 0 to 255 DW 0 to 255
DD 0 to 254
N N
25
18
1.9
0.59
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Basic Operations
Transfer Operations (continued)

PY T PY 128 to 255 N N N 0 N N N 27
1)
0 to 127
N N
27
1)
15
1)
2.0 1) 1.21)
1.6 1) 1.5 1)
Transfer the contents of ACCU 1-L (bits 0-7) to a peripheral byte of the digital or analog outputs. The PIQ is also corrected. Transfer the contents of ACCU 1-L (bits 0-7) to a peripheral byte of the digital or analog outputs. Transfer the contents of ACCU 1-L (bits 0-15) to a peripheral word of the digital or analog outputs: bits 8-15 byte n; bits 0-7 byte n+1 The PIQ is also corrected.
14
1)
PW 0 to 126 T PW 128 to 254
N N
30
1)
21
1)
3.2
1)
2.6 1)
N N
30
1)
18
1)
2.0 1)
2.4 1)
Transfer the contents of ACCU 1-L (bits 0-15) to a peripheral word of the digital or analog outputs: bits 8-15 byte n; bits 0-7 byte n+1 Transfer the contents of ACCU 1-L (bits 0-7) to a byte of the extended periphery of the digital or analog outputs (no process image). Transfer the contents of ACCU 1-L to a word of the extended periphery of the digital or analog outputs (no process image): bits 8-15 byte n; bits 0-7 byte n+1
OY 0 to 255
N N
23
1)
14
1)
1.2 1)
1.5 1)
OW 0 to 254
N N
26
1)
18
1)
2.0 1)
2.4 1)
1)
Execution time for single processing operation and for immediate bus access in multiprocessing operation. I/Os acknowledge within 0.1 s or proportionally longer execution time for longer acknowledgement time.
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Basic Operations
Timer Operations
SP T 0 to 255 N N N N Y N Y 20/ 42 1) 21/ 43 1) 20/ 45 1) 21/ 46 1) 22/ 44 1) 14/ 18 2) 1.2/ 18 1) 1.2/ 18 1) 1.2/ 18 1) 1.2/ 18 1) 1.2/ 18 1) 12/ 15 2) 3.6 0.18 Start timer (stored in ACCU 1-L) as pulse (start timer with continuous enable) Start timer (stored in ACCU 1-L) as extended pulse (start timer with one-shot enable)
SE
T 0 to 255
Y N
3.6
0.18
SD
T 0 to 255
Y N
3.6
0.18
Start timer (stored in ACCU 1-L) as ON delay
SS
T 0 to 255
Y N
3.6
0.18
Start timer (stored in ACCU 1-L) as stored ON delay
SF
T 0 to 255
Y N
3.6
0.18
Start timer (stored in ACCU 1-L) as OFF delay
T 0 to 255
1.4
0.18
Reset timer
1) 2)
Time applies when "S5 time is not started/S5 time is started". Time applies when RLO = 0 / RLO = 1.
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Basic Operations
Counter Operations
CU C 0 to 255 N N N N Y N Y 18/ 23 1) 18/ 24 1) 17/ 38 1) 12/ 16 2) 1.2/ 14 1) 1.2/ 14 1) 16/ 23 1) 12/ 14 2) 2.1 0.18 Counter counts up 1
CD
C 0 to 255
Y N
2.0
0.18
Counter counts down 1
C 0 to 255
Y N
3.8
0.18
Set counter with the value stored in ACCU 1-L (BCD number from 0 to 999)
C 0 to 255
1.4
0.18
Reset counter
1) 2)
Time applies when "S5 time is not started/S5 time is started". Time applies when RLO = 0 / RLO = 1.
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Basic Operations
Arithmetic Operations
The result (numerical value) of an arithmetic operation is stored in ACCU 1. All other accumulator contents change as follows: For +F, -F, xF, ACCU-2-L: ACCU-3-L: ACCU-4-L: :F: = ACCU-3-L = ACCU-4-L = ACCU-4-L For +G, -G, xG, :G, +D, -D: ACCU 2: = ACCU 3 ACCU 3: = ACCU 4 ACCU 4: = ACCU 4
The original contents of ACCU 2-L or ACCU 2 are lost. Whether the result is <0, >0 or =0 can be evaluated via CC0 and CC1 (see Explanatory Notes on the Condition Codes). Fixed-point numbers, 16 bits +F -F xF Y Y Y Y Y Y Y Y Y Y Y Y N N N N N N N N N 26-32 26-33 36-39 15-18 15-20 20-21 0.94 0.94 7.9 0.55 0.55 3.2 Add two fixed-point numbers: (ACCU 1-L) + (ACCU 2-L) Subtract one fixed-point number from another: (ACCU 2-L) - (ACCU 1-L) Multiply one fixed-point number by another: (ACCU 1-L) x (ACCU 2-L) Divide one fixed-point number by another: (ACCU 2-L) : (ACCU 1-L). ACCU 1-L: result; ACCU 2-H: remainder
:F
N N
27-50
13-24
10.4
3.8
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Basic Operations
Arithmetic Operations (continued)

Floating-point numbers, 32 bits When performing arithmetic operations with a 16-bit mantissa (default), the eight low bits are set to "0". 30-33
1) 2)
+G
N N
56-86
31-56
9.1
3.3
Add two floating-point numbers: ACCU 1 + ACCU 2
30-42
1) 2)
-G
N N
56-86
31-47
9.1
3.5
Subtract one floating-point number from another: ACCU 1 - ACCU 2
29-39
1) 2)
12.1 1) 20.5 2) 5.2
xG
N N
52-74
30-66
Multiply one floating-point number by another: ACCU 1 x ACCU 2
28-42
1) 2)
15.6 1) 23.3 2) 6.3
:G
N N
51-81
31-69
Divide one floating-point number by another: ACCU 2: ACCU 1; Result: ACCU 1-L: mantissa low ACCU 1-H: mantissa high and exponent
1) 2)
Time in the case of 16-bit mantissa (default) Time in the case of 24-bit mantissa
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Basic Operations
Comparison Operations
The contents of ACCU 2 (operand) are compared with the contents of ACCU 1 (operand 2). The RLO is set to "1" if the comparison condition is fulfilled or to "0" if it is not fulfilled. Whether the contents of ACCU 2 are <, > or = those in ACCU 1, can be evaluated via CC0 and CC1 (see Explanatory Notes on the Condition Codes). Fixed-point numbers, 16 bits !=F ><F >F >=F <F <=F Y Y Y Y Y Y Y Y Y Y Y Y 0 0 0 0 0 0 0 0 0 0 0 0 N Y N Y N Y N Y N Y N Y N N N N N N 18 18 18 18 18 18 14-15 14-15 13-14 14-15 14-15 14-15 0.88 0.88 0.88 0.88 0.88 0.88 0.30 0.30 0.30 0.30 0.30 0.30 Compare two fixed-point numbers for equal to: if ACCU 2-L = ACCU 1-L, the RLO is "1" Compare two fixed-point numbers for not equal to: if ACCU 2-L ACCU 1-L, the RLO is "1" Compare two fixed-point numbers for greater than: if ACCU 2-L > ACCU 1-L, the RLO is "1" Compare two fixed-point numbers for greater than or equal to: if ACCU 2-L ACCU 1-L, the RLO is "1" Compare two fixed-point numbers for less than: if ACCU 2-L < ACCU 1-L, the RLO is "1" Compare two fixed-point numbers for less than or equal to: if ACCU 2-L ACCU 1-L, the RLO is "1"
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Basic Operations
Comparison Operations (continued)

Floating-point numbers !=G ><G >G Y Y Y Y Y Y 0 0 0 0 0 0 N Y N Y N Y N N N 19-27 19-27 19-27 17-19 17-18 16-18 1.9 1.9 1.9 1.4 1.4 1.4 Compare two floating-point numbers for equal to: if ACCU 2 = ACCU 1, the RLO is "1" Compare two floating-point numbers for not equal to: if ACCU 2 ACCU 1, the RLO is "1" Compare two floating-point numbers for greater than: if ACCU 2 > ACCU 1, the RLO is "1" Compare two floating-point numbers for greater than or equal to: if ACCU 2 ACCU 1, the RLO is "1" Compare two floating-point numbers for less than: if ACCU 2 < ACCU 1, the RLO is "1" Compare two floating-point numbers for less than or equal to: if ACCU 2 ACCU 1, the RLO is "1"
>=G
N Y
19-27
17-19
1.9
1.4
<G <=G
Y Y
Y Y
0 0
0 0
N Y N Y
N N
19-27 19-27
17-19 17-19
1.9 1.9
1.4 1.4
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Basic Operations
Comparison Operations (continued)

Fixed-point double words, 32 bits !=D ><D >D Y Y Y Y Y Y 0 0 0 0 0 0 N Y N Y N Y N N N 19-24 19-24 19-24 15-16 15-16 14-16 1.6 1.6 1.6 0.52 0.52 0.52 Compare two fixed-point double words for equal to: if ACCU 2 = ACCU 1, the RLO is "1" Compare two fixed-point double words for not equal to: if ACCU 2 ACCU 1, the RLO is "1" Compare two fixed-point double words for greater than: if ACCU 2 > ACCU 1, the RLO is "1" Compare two fixed-point double words for greater than or equal to: if ACCU 2 ACCU 1, the RLO is "1" Compare two fixed-point double words for less than: if ACCU 2 < ACCU 1, the RLO is "1" Compare two fixed-point double words for less than or equal to: if ACCU 2 ACCU 1, the RLO is "1"
>=D
N Y
19-24
15-17
1.6
0.52
<D <=D
Y Y
Y Y
0 0
0 0
N Y N Y
N N
19-24 19-24
15-16 15-17
1.6 1.6
0.52 0.52
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Basic Operations
OperaOperands tion STL A N Z 1 Condition codes affected A N Z 0 O V RLO 1 dep. 2 affect. O 3 reload S 1 2 3 Execution = Operation with this CPU 922 CPU 928 times in s not possible CPU CPU 928B CPU 948 Function
Block Call Operations

JU PB 0 to 255 N N N 0 N N Y 35 28 3.7 1.5/ 6.0 5) 1.5/ 6.0 5) 1.5/ 6.0 5) 1.5/ 6.0 5) 1.5/ 6.0 5)
2)
Unconditional program block call
JU
FB 0 to 255
N N
34
28
3.7
Unconditional function block call
DOU FX 0 to 255
N N
41
32
4.8
Unconditional extended function call
JU
SB 0 to 255
N N
35
28
3.7
Unconditional sequence block call
JU
OB 1 to 39
N
1)
N
1)
N
1)
0
1)
N N
1)
39
2)
28
2)
4.1
2)
Unconditional organization block call Unconditional call of a special function organization block of the operating system Conditional program block call (if RLO is "1")
JU
OB 40 to 255
JC
PB 0 to 255
03) Y
12/ 35 4) 12/ 35 4)
0.8/ 27 4) 2.8/ 28 4)
3.7
1.6/ 6.1 5) 1.6/ 6.1 5)
JC
FB 0 to 255
03) Y
3.7
Conditional function block call (if RLO is "1")
1)
The condition codes are set or not set according to the special function executed (see Programming Guide Special Function OBs) For execution times see List of Special Functions, page 130ff.
3) 4) 5)
The Os bit remains unchanged if RLO = 0 (not for CPU 948). Time applies when RLO =0 / RLO = 1. Time applies when "interruption at block limits".
2)
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Basic Operations
Block Call Operations (continued)

DOC FX 0 to 255 N N N 01) Y 1 Y 19/ 43 2) 12/ 35 2) 12/ 41 2)
5)
14/ 41 2) 0.8/ 27 2) 0.8/ 28 2)

5)
4.8
1.6/ 6.1 6) 1.6/ 6.1 6) 1.6/ 6.1 6)

5)
Conditional extended function block call (if RLO is "1")
JC
SB 0 to 255
01) Y
3.7
Conditional sequence block call (if RLO is "1")
JC
OB 1 to 39
N
3)
N
3)
N
3)
01) Y
3)
4.1
5)
Conditional organization block call Conditional call of special function organization block of the operating system
JC
OB 110 to 255 DB 2 to 255
14) Y N N N N N
N N N N N
N N N N N
N N N N N
N N N N N
N N N N N N N N N N
0.91 Call a data block 22 28 22 2.7 1.0 Call an extended data block 19 1.9
C DB 3 to 255 DX 1 to 255 CX DX 2 to 255 DX 3 to 255
1) 2) 3)
The OS bit remains unchanged if RLO = 0 (not for CPU 948). Time applies when RLO = 0 / RLO = 1. The condition codes are set or not set according to the special function executed (see Programming Guide Special Function OBs).
4)
Only if the RLO = 0 before the OB is called, otherwise the RLO can be influenced according to the special function executed (see Programming Guide - Special Function OBs). For execution times see List of Special Functions, page 156ff. Time applies when "interruption at block limits".
5) 6)
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Basic Operations
Block Call Operations (continued)

DB 2 to 255 G DB 3 to 255 DX 1 to 255 GX DX 2 to 255 DX 3 to 255 N N N N N N N N N N N N N N N N N N N N N N N N N N N N 67 67 48 76 493 Generate an extended data block. The number of its data words must be stored in ACCU 1 (max. 4091 DW) 48 76 N N N N N N N 498 Generate a data block. The number of its data words must be stored in ACCU 1 (max. 4091 DW)
Block End Operations

BE N N N 0 N N Y 26 12/ 27 2) 26 11 0.8/ 19 2) 11 3.8 2.0 Block end (termination of a block)
BEC
01) Y
3.8
2.1
Block end, conditional (if RLO is "1")
BEU
N N
3.8
2.0
Block end, unconditional
1) 2)
The OS bit remains unchanged if RLO = 0 (not for CPU 948). Time applies when RLO = 0 / RLO = 1.
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Basic Operations
Null Operations
NOP 0 NOP 1 N N N N N N N 9 1.0 0.57 0.18 No operation (all bits set to 0)
N N
0.8
0.57
0.18
No operation (all bits set to 1)
Stop Operation
Direct transition to "STOP" mode STP N N N N N N N CPU 948: transition to communication stop (operating mode SMOOTH STOP), program processing aborted at cycle end or by the system program
Display Construction Operations

BLD BLD BLD BLD BLD BLD 0 - 255 130 131 132 133 255 N N N N N N N N N N N N N N N N N N N N N N N N N N N N N N N N N N N N N N N N N N 9 9 9 9 9 9 0.8 0.8 0.8 0.8 0.8 0.8 0.57 0.57 0.57 0.57 0.57 0.57 0.18 0.18 0.18 0.18 0.18 0.18 Display construction statement/NOP for the programmable controller Display construction operation for the programmer: generate blank line by carriage return Display construction operation for the programmer: switch over to statement list (STL) Display construction operation for the programmer: switch over to control system flowchart CSF) Display construction operation for the programmer: switch over to ladder diagram (LAD) Display construction operation for the programmer: terminate segment
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Permissible only in function blocks
Binary Logic Operations

A= AN= O= ON= Formal operand N Formal operand N Formal operand N Formal operand N N N N N N N N N N N N N N Y N Y N Y N Y N N N N 24 24 24 24
1)
24 24 24 24
1)
2.4 1) 2.4 1) 2.4 1) 2.4 1)
0.91 1) 0.91 1) 0.91 1) 0.91 1)
AND operation: scan a formal operand for "1" (parameter type: I, Q, T, C; data type: BI) AND operation: scan a formal operand for "0" (parameter type: I, Q, T, C; data type: BI) OR operation: scan a formal operand for "1" (parameter type: I, Q, T, C; data type: BI) OR operation: scan a formal operand for "0" (parameter type: I, Q, T, C; data type: BI)
1)
1)
1)
1)
1)
1)
Digital Operations
The result (= "0" or "0") can be evaluated via CC0 and CC1 (see Explanatory Notes on the Condition Codes) Combine contents of ACCU 2 and ACCU 1 (word operation) through logic AND: result is stored in ACCU 1 Combine contents of ACCU 2 and ACCU 1 (word operation) through logic OR: result is stored in ACCU 1 Combine contents of ACCU 2 and ACCU 1 (word operation) through logic EXOR: result is stored in ACCU 1
AW
N N
16
11
0.57
0.18
OW
N N
16
11
0.57
0.18
XOW
N N
16
11
0.57
0.18
1)
The execution time of the substituted operation must be added.
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Bit Test Operations

These operations scan the status of a bit and update it in the RLO. TB TB TB TB TB TB I 0.0 to 127.7 N N N N N N N N N N N N N N N N N N N N N N Y N Y N Y N Y N Y N Y N N N N N N 0.48 0.48 0.48 0.48 0.48 0.77 Scan an input bit for signal status "1" Scan an output bit for signal status "1" Scan a flag bit for signal status "1" Scan a bit of a timer word for signal status "1" Scan a bit of a counter word for signal status "1" Scan a bit of a data word (DB/DX) for signal status "1" Scan a bit in the RI area for signal status "1"
Q 0.0 to 127.7 F 0.0 to 255.7
T 0.0 to 255.15 N C 0.0 to 255.15 N D 0.0 to 255.15 N RI 0.0 to 255.15 RJ 0.0 to 255.15 RS 0.0 to 255.15 RT 0.0 to 255.15
TB
N Y
0.48
TB
N Y
0.48
Scan a bit in the RJ area for signal status "1"
TB
N Y
0.48
Scan a bit in the RS area for signal status "1"
TB
N Y
0.48
Scan a bit in the RT area for signal status "1"
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Bit Test Operations (continued)

These operations scan the status of a bit and update it in the RLO. TBN TBN TBN TBN TBN TBN I 0.0 to 127.7 N N N N N N N N N N N N N N N N N N N N N N Y N Y N Y N Y N Y N Y N N N N N N 0.48 0.48 0.48 0.48 0.48 0.77 Scan an input bit for signal status "0" Scan an output bit for signal status "0" Scan a flag bit for signal status "0" Scan a bit of a timer word for signal status "0" Scan a bit of a counter word for signal status "0" Scan a bit of a data word (DB/DX) for signal status "0" Scan a bit in the RI area for signal status "0"
Q 0.0 to 127.7 F 0.0 to 255.7
T 0.0 to 255.15 N C 0.0 to 255.15 N D 0.0 to 255.15 N RI 0.0 to 255.15 RJ 0.0 to 255.15 RS 0.0 to 255.15 RT 0.0 to 255.15
TBN
N Y
0.48
TBN
N Y
0.48
Scan a bit in the RJ area for signal status "0"
TBN
N Y
0.48
Scan a bit in the RS area for signal status "0"
TBN
N Y
0.48
Scan a bit in the RT area for signal status "0"
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Set/Reset Operations
S= RB= RD= == SU SU SU SU SU Formal operand N Formal operand N Formal operand N Formal operand N I 0.0 to 127.7 N N N N N N N N N N N N N N N N N N N N N N N N N N N N Y Y Y N N N Y Y Y Y Y Y Y Y Y 25 25
1)
23 22 13 23
1)
1.9 1) 1.9 1) 1.9 1) 1.9 1)
0.64 1) 0.64 1) 0.64 1) 0.64 1) 0.48 0.48 0.48 0.48 0.48
Binary setting of a formal operand (parameter type: I, Q; data type: BI) Binary resetting of a formal operand (parameter type: I, Q; data type BI) Digital resetting of a formal operand for timers and counters (parameter type: T, C) Assignment of the RLO to a formal operand parameter type: I, Q; data type: BI) Set an input bit (in the PII) unconditionally Set an output bit (in the PIO) unconditionally Set a flag bit unconditionally Set a bit of a timer word unconditionally Set a bit of a counter word unconditionally
1)
1)
14 1) 25
1)
1)
1)
Q 0.0 to 127.7 N F T 0.0 to 255.7 N 0.0 to 255.15 N
C 0.0 to 255.15 N
1)
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Set/Reset Operations (continued)

SU D 0.0 to 255.15 N RI 0.0 to 255.15 RJ 0.0 to 255.15 I 0.0 to 127.7 N N N N N Y 0.77 Set a bit of a data word (DB/DX) unconditionally
SU
N N
0.48
Set a bit in the RI area unconditionally
SU
N N
0.48
Set a bit in the RJ area unconditionally
RU RU RU RU RU RU
N N N
N N N N N N
N N N N N N
N N N N N N
Y Y Y Y Y Y
0.48 0.48 0.48 0.48 0.48 0.77
Reset an input bit (in the PII) unconditionally Reset an output bit (in the PIO) unconditionally Reset a flag bit unconditionally Reset a bit of a timer word unconditionally Reset a bit of a counter word unconditionally Reset a bit of a data word (DB/DX) unconditionally
Q 0.0 to 127.7 F 0.0 to 255.7
T 0.0 to 255.15 N C 0.0 to 255.15 N D 0.0 to 255.15 N RI 0.0 to 255.15 RJ 0.0 to 255.15
RU
N N
0.48
Reset a bit in the RI area unconditionally
RU
N N
0.48
Reset a bit in the RJ area unconditionally
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Timer and Counter Operations

SP= Formal operand N N N N Y N Y 14
2)
16
2)
1.9 2)
0.64
2)
Start timer specified as formal operand as pulse with the value stored in ACCU 1-L (parameter type: T) Start timer specified as formal operand as ON delay with the value stored in ACCU 1-L (parameter type: T) Start timer specified as formal operand as extended pulse with the value stored in ACCU 1-L or set counter specified as formal operand with the count stored in ACCU 1-L (parameter type: T, C) Start timer specified as formal operand as stored ON delay with the value stored in ACCU 1-L or increment a counter specified as formal operand (parameter type: T, C) Start timer specified as formal operand as stored OFF delay with the value stored in ACCU 1-L or decrement a counter specified as formal operand (parameter type: T, C) Enable formal operand (timer/counter) for cold restart (for description see FR T or FR C); (parameter type: T, C)
SD=
Formal operand N
Y N
14
2)
16
2)
1.9 2)
0.64 2)
SEC= Formal operand N
Y N
14
2)
15
2)
1.9
2)
0.64 2)
SSU= Formal operand N
Y N
14
2)
16
2)
1.9 2)
0.64 2)
SFD= Formal operand N
1)
14
2)
16
2)
1.9 2)
0.64
2)
FR=
Formal operand N
Y N
12
2)
13
2)
1.9 2)
0.64 2)
1) 2)
The RLO is evaluated according to the executed operation. The execution time of the substituted operation must be added.
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Timer and Counter Operations (continued)

FR T 0 to 255 N N N N Y N
1) 1)
19/22
15/16
1.6
0.18
Enable timer for cold restart. The operation is executed only on the leading edge of the RLO (change from "0" to "1"). The timer is restarted if the RLO is "1" at the time of the start operation. Enable a counter for setting or counting up or down. This operation is executed only on the leading edge of the RLO (change from "0" to "1"). The counter is restarted if the RLO = "1" at the time of the set operation. The counter is counted up or down if the RLO = "1" at the time of the "counting up" (CU) or "counting down" (CD) operation.
FR
C 0 to 255
Y N
1)
1)
17/22
16/18
1.6
0.18
1)
Time applies when RLO = "0"/RLO = "1".
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Load and Transfer Operations

Load operations: the value in ACCU 1 is shifted and stored in ACCU 2. Zeros are supplied for unused bits in ACCU 1.
1) 1)
L=
Formal operand N
N N
19
16
2.1 1) 1.9 1)
0.64 1)
The value of the formal operand is loaded into ACCU 1 (parameter type: I, Q, T, C; data type: BY, D, W) Load formal operand in BCD into ACCU 1 (parameter type: T, C) Load the bit pattern of a formal operand into ACCU 1 parameter type: D; data type: KF, KH, KM, KY, KS, KT, KC) The value of the formal operand is loaded into ACCU 1 (parameter type: D; data type: KG) The contents of ACCU 1 are transferred to the formal operand (parameter type: I, Q; data type: BY, D, W) Load a word from the interface data range (RI) into ACCU 1-L Load a word from the extended interface data area range into ACCU 1-L Load a word from the system data area into ACCU 1-L Load a word from the extended system data area into ACCU 1-L
LD=
Formal operand N
N N
14
1)
14
1)
0.64 1)
LW=
Formal operand N
N N
5 1)
15
1)
0.5 1)
0.50 1)
LDW= Formal operand N
N N
5 1)
1)
18
1)
0.5 1) 2.1 1)
0.68 1) 0.64 1)
T=
Formal operand N
N N
18
15
1)
L L L L
RI 0 to 255 RJ 0 to 255 RS 0 to 255 RT 0 to 255
N N N N
N N N N
N N N N
N N N N
N N N N N N N N
N N N N
23
13 13
0.68 0.68 0.68 0.68
0.18 0.18 0.18 0.18
23
13 13
1)
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Load and Transfer Operations (continued)

Load operations: the value in ACCU 1 is shifted and stored in ACCU 2. Zeros are supplied for unused bits in ACCU 1. T T T T RI 0 to 255 RJ 0 to 255 RS 60 to 63 RT 0 to 255 N N N N N N N N N N N N 0 0 0 0 N N N N N N N N N N N N 15 15 11 11 11 11 0.57 0.57 0.57 0.57 0.18 0.18 0.18 0.18 Transfer the contents of ACCU 1-L to a word in the interface data area Transfer the contents of ACCU 1-L to a word of the extended interface data area Transfer the contents of ACCU 1-L to a word in the system data area Transfer the contents of ACCU 1-L to a word of the extended system data area
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Conversion Operations
The data in ACCU 1 is converted. CFW CSW N Y N Y N Y N Y N N N N N N 12 15 25-34
1)
9 11 13-19
1)
0.57 0.57
0.18 0.18
Form ones complement of ACCU 1-L (bits 0-15) Form twos complement of ACCU 1-L (bits 0 - 15). Result can be evaluated via CC0/CC1 and OV Form twos complement of ACCU 1-L (bits 0 - 31). Result can be evaluated via CC0/CC1 and OV Convert a 16-bit fixed point from BCD into binary Convert a 16-bit fixed point from binary into BCD
CSD
N N
0.94
0.43
DEF DUF
N N
N N
N N
N Y
N N N N
N N
34 37 68-100
1)
14 15
1.9 3.3
0.30 0.43
DED
N N
31
7.7
0.48
Convert a 32-bit fixed point from BCD into binary
DUD
N N
60-79
1)
19-35
1)
9.8
0.62
Convert a 32-bit fixed point from binary into BCD
FDG
N N
25-54
1)
18-36
1)
5.2
2.6
Convert a fixed-point number (32 bits) into a floating-point number Convert a floating-point number into a fixed-point number (32 bits)
GFD
N N
33-64
1)
15-20
1)
4.4
1.5
1)
The time is dependent on the date in ACCU 1(non-linear).
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Shift and Rotate Operations

The data in ACCU 1 is shifted or rotated. The bit shifted or rotated last can be evaluated via CC0 and CC1. 0-151) 12-19
2)
SLW
N N
6-12
2)
1.9
0.32
Shift the contents of ACCU 1-L (word) to the left by the value n specified in the parameter (n = 0 to 15). Positions becoming vacant are padded with zeros. Shift the contents of ACCU 1-L (word) to the right by the value n specified in the parameter (n = 0 to 15). Positions becoming vacant are padded with zeros. Shift the contents of ACCU 1 (double word) to the left by the value specified in the parameter (n = 0 to 32) Positions becoming vacant are padded with zeros. Shift the contents of ACCU 1-L (word) including its sign to the right by the value n specified in the parameter (n = 0 to 15). Positions becoming vacant are padded with the sign (bit 15) Shift the contents of ACCU 1 (double word) to the right by the value n specified in the parameter (n = 0 to 32). Positions becoming vacant are padded with the sign (bit 32) Rotate ACCU 1 to the left (32 bits wide) from position 0 to 32 Rotate ACCU 1 to the right (32 bits wide) from position 0 to 32
SRW
0-151)
N N
11-18
2)
6-12
2)
2.0
0.32
SLD
0-32
1)
N N
23-36
2)
7-23
2)
2.6
0.48
SSW
0-15 1)
N N
21-24
2)
7-13
2)
2.1
0.32
SSD
0-321)
N N
26-38
2)
7-25
2)
3.5
0.48
RLD
0-321)
N N
27-44
2)
6-26
2)
2.6
0.48
RRD
1)
0-321)
N N
26-44
2)
7-26
2)
2.7
0.48
With the operand = "0" an NOP operation is executed; the condition codes are not affected. The time is dependent on the size of the (non-linear) operand.
2)
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OperaOperands tion STL C C 1 Condition codes affected C C 0 O V RLO Execution = Operation with this CPU 922 CPU 928 times in s not possible CPU CPU 928B CPU 948 Function
1 dep. 2 affect. O 3 reload S 1 2 3
Jump Operations
The jump operations are executed depending on the RLO (only operation JC) or CC0/CC1 and the OV and OS bits (see Evaluation of CC0 and CC1, page 120) Symbolic address max. 4 characters Symbolic address max. 4 characters Symbolic address max. 4 characters
JU=
N N
10
1.5
1.0
0.59
Unconditional jump to a symbolic address
JC=
13
1/2
1)
1.0
0.4/0.8
1)
Conditional jump to a symbolic address, executed only if RLO = 1; if RLO = "0", it is set to "1" Jump if result is "0": the jump is only made if CC1 = 0 and CC0 = 0 Jump if result "0": the jump is only made if CC1 = 0 and CC0 = 1 or CC1 = 1 and CC0 = 0 or CC1 = 1 and CC0 = 0
2)
JZ=
N N
12
11/12
1)
1.4
0.4/0.8
1)
JN=
Symbolic address max. 4 characters
N N
12
10/13
1)
1.4
0.4/0.8
1)
JP=
Symbolic address max. 4 characters Symbolic address max. 4 characters Symbolic address max. 4 characters Symbolic address max. 4 characters
N N
13
10/13
1)
1.4
0.4/0.8
1)
Jump if result > "0": the jump is only made if CC1 = 1 and CC0 = 0 Jump if result < "0": the jump is only made if CC1 = 0 and CC0 = 1 Jump on "overflow": the jump is only made if the OV bit is set. Jump on "stored overflow": the jump is only made if the OS bit is set
JM=
N N
13
12/14
1)
1.4
0.4/0.8
1)
JO=
N N
12
11/14
1)
1.4
0.4/0.8
1)
JOS=
N N
17
13/14
1)
1.3
0.7/0.9
1)
1)
Jump condition: fulfilled/not fulfilled
2)
If CC 1 = "1" and CC 0 ="1", not executed for CPU 948 79
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IA RA IAE RAE N N N N N N N N N N N N N N N N N N N N N N N N N N N N 12 12 25 25 52 52 0.30 0.30 0.32 0.32 Disable interrupt: process interrupts are no longer serviced Enable interrupt: cancels the effect of IA Disable addressing error Enable addressing error: cancels the effect of IAE Disable output command: PIQ is no longer affected, i.e., the outputs are no longer changed by the S Q, R Q, =Q, T PY, T PW operations. Enable output command: cancels the effect of BAS
BAS
0.50
BAF
0.50
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Other Operations (continued)

D I ENT 0-255 0-255 0-312) N N N N N N N N N N N N N N N N N N N N N 11 11 26 9 9 8 0.57 0.57 0.75 4.1 3) 0.18 0.18 0.39 3.0 3) Decrement the low byte (bits 0 to 7) of ACCU 1 by the value n (n=0 to 255) (without carry) Increment the low byte (bits 0 to 7) of ACCU 1 by the value n (n=0 to 255) (without carry) The contents of the accumulators are restored1). Set semaphore with the number specified (operation applicable exclusively in multiprocessor mode) Enable semaphore with the number specified (operation applicable exclusively in multiprocessor mode)
SED
N N
32-37
23
SEE
0-312)
N N
32-36
23
4.1 3)
3.1 3)
1)
New value of := ACCU 1 := ACCU 2 := ACCU 3 := ACCU 4 := The original contents of ACCU
Old value of ACCU 1 ACCU 2 ACCU 2 ACCU 3 4 are lost.
2) 3)
Semaphore locations on the coordinator module Add the waiting time for the bus allocation
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OperaOperands tion STL C C 1 Condition codes affected C C 0 O V RLO 1dep. 2 affect. O 3 reload S 1 2 3 Execution = Operation with this CPU 922 CPU 928 times in s not possible CPU CPU 928B CPU 948 Function

DO= Formal operand
1) 1) 1) 1) 1) 1) 1)
12-15
2)
15
2)
1.7 2)
0.82
2)
Call block as formal operand (only C DB, JU PB/FB/SB/OB can be substituted) Process data word: the following operation is executed with the parameter specified in the data word 3) Process flag word: the following operation is executed with the parameter specified in the flag word 3)
DO
DW 0 to 255
N N
20-26
12-26
3.3
0.84 2)
DO
FW 0 to 254
N N
19-25
23-26
3.2
0.75 2)
1)
The condition codes are evaluated and changed according to the operation executed. The execution time of the substituted operation must be added. The following operations are possible: - A.., AN.., O.., ON.., S.., R..,=.. with the areas I, Q, F and S, - FR T, R T, SF T, SR T, SP T, SS T, SE T, FR C, R C, S C, CD C, CU C, - L.., T.. with the areas P, O, I, Q, F, S, D, RI, RJ, RS and RT, - L T, L C, - LC T, LC C, - JU=, JC=, JZ=, JN=, JP=, JM=, JO=, - SLW, SRW, - D, I, SED, SEE, - C DB, JU.., JC.., G DB, GX DX, CX DX, DOC FX, DOU FX
2)
3)
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System Operations
3)
Load and Transfer Operations

LIR Register no. 0 to 15 Register no. 0 to 15 N N N N N N N 26-35 2-23 45-51
2)
0.9-2.1 Load register with the contents of a memory word 2) addressed by ACCU 11) 0.7-1.9 Transfer register contents into the memory word 2) addressed by ACCU 11)
TIR
N N
26-38
5-19
36-50
2)
1)
Registers for LIR and TIR (register width = 16 bits) Reg.-No. 0 1 2 3 5 6 ACCU 1-H ACCU 1-L ACCU 2-H ACCU 2-L BSP (only on CPU 922/948) DBA Register designation high word ACCU 1 low word ACCU 1 high word ACCU 2 low word ACCU 2 Block Stack Pointer Start address of the current data block (address of the first DW) Length of the current data block (number of data words) high word ACCU 3 low word ACCU 3 high word ACCU 4 low word ACCU 4 Step Address Counter
2) Execution time for single processing operation and for immediate bus access in multiprocessing operation. l/Os acknowledge within 0.1 s or proportionally longer execution time for longer acknowledgement time. 3) Differences in the CPU 948: The operations LIR/TIR operate with 20 bit absolute addresses.
Specifying the address in ACCU 1: ACCU-1-H:Bit no. 15 to 4= 0 Bit no. 3 to 0= address bits nos. 19 to 16 ACCU-1-L:Bit no. 15 to 0= address bits nos. 15 to 0
DBL (not on CPU 922) ACCU 3-H ACCU 3-L ACCU 4-H ACCU 4-L SAC (not on CPU 948)
9 10 11 12 15
- Access to the 8-bit memory: LIR: the high byte of the register is loaded with FFH (except on CPU 948, S flag and I/Os) TIR: the high byte of the register is lost 86
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System Operations
3)

Register name 1) Load the specified 32 bit register with the contents by ACCU 1-H/L 1.1-3.2 of a memory word n addressed 2) and the following word n+1 3): register HIGH = memory word n register LOW = memory word n+1 Transfer the contents of the specified 32 bit by 1.0-2.4 register into the memory word n addressed 2) ACCU 1-H/L and the following word n+1 3): memory word n = register HIGH memory word n+1 = register LOW
2) Execution time for single processing operation and for immediate bus access in multiprocessing operation. l/Os acknowledge within 0.1 s or proportionally longer execution time for longer acknowledgement time. 3)
LDI
N N
TDI
Register name 1)
N N
1)
Registers for LDI and TDI (register width = 32 bits) Reg.-No. A1 A2 SA BA BR Register designation ACCU 1 ACCU 2 SAC = STEP address counter BA register (block start address, bit no. 0 to 19) BR register (block address register, bit no. 0 to 19)
Specifying the address in ACCU 1:
ACCU-1-H:Bit no. 15 to 4= 0 Bit no. 3 to 0= address bits nos. 19 to 16 ACCU-1-L:Bit no. 15 to 0= address bits nos. 15 to 0
- Access to the 8-bit memory: LDI: the HIGH byte of the register is loaded with FFH (except on CPU 948, S flag and I/Os) TDI: the high byte of the register is lost
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System Operations
OperaOperands tion STL C C 1 Condition codes affected C C 0 O V RLO 1 dep. 2 affect. O 3 reload S 1 2 3 Execution = Operation with this CPU 922 CPU 928 times in s not possible CPU CPU 928B CPU 948 Function (only CPU 922/928/928B)

TNB Length of area 0 to 255 N N N 01) N N N 54 1530 66 1226 1001258
2)
Block transfer 0 to 255 bytes3): End address of target area in ACCU 1-L End address of source area in ACCU 2-L Block transfer 0 to 255 words3): End address of target area in ACCU 1-L End address of source area in ACCU 2-L
TNW
Length of area 0 to 255
01) N N
55 3010
65 2340
952400
2)
1) 2)
With CPU 928/928B the OS bit is not influenced by TNB 0/TNW 0. Execution time for single processing operation and for bus access in multiprocessing operation. I/Os acknowledge within 0.1 s or proportionally longer execution time for longer acknowledgement time.
3)
Block transfer operations function decrementally, i.e., the number of words/bytes specified is transferred starting with the end address. Source area and target area must be located completely within one of the following memory areas: Address area 0000 - 7FFF (16 bit) 8000 - DD7F (16 bit) DD80 - E3FF (16 bit) E400 - E7FF (8 bit) E400 - E7FF (16 bit) E800 - EDFF (16 bit) AC00 - EDFF (16 bit) EE00 - EFFF (8 bit) F000 - FFFF (8 bit) A conversion takes place in case of block transfers between 8 and 16 bit memory areas. Two bytes are converted into a word and vice versa. CPU 922 CPU 928 CPU 928B
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System Operations
OperaOperands tion STL C C 1 Condition codes affected C C 0 O V RLO 1 dep. 2 affect. O 3 reload S 1 2 3 Execution = Operation with this CPU 922 CPU 928 times in s not possible CPU CPU 928B CPU 948 Function (only CPU 948)

The block transfer operations of the CPU 948 listed below function with 20 bit absolute addresses. Only these operations can be interrupted by timeout (QVZ) and power failure (NAU). 2-250 TNW Length of area 0 to 255 N N N 0 N N N
1)
Block transfer in words in the 16 bit memory area 2)
3-560 3-180 TXB N N N 0 N N N

1)
5-480 3-180 TXW N N N 0 N N N

1)
Block transfer from the 8 bit to the 16 bit memory area 2): The byte from address n is transferred into the high byte, the byte from address n+1 is transferred into the low byte of the target date. Block transfer from the 16 bit to the 8 bit memory area 2): The high byte of the source date is transferred into the byte with address n, the low byte of the source date is transferred into the byte with address n+1.
5-480
1)
Execution time for single processing operation and for immediate bus access in multiprocessing operation. I/Os acknowledge within 0.1 s or proportionally longer execution time for longer acknowledgement time. Address area of the CPU 948 0 0000 to E FBFF (16 bit) E A000 to E AFFF (8 bit - S flag) E FC00 to E FFFF (8 bit) F 0000 to F FFFF (8/16 bit)
2)
Block transfer operations function decrementally, i.e., the number of words specified is transferred starting with the end address. The end address of the target area (20 bit) must be located in ACCU 1, the end address of the source area (20 bit) must be located in ACCU 2. Both the source and the target area must be completely within a memory area listed in the table. For TXB and TXW ACCU 3 must contain the block length (number of words, 0 to 127). A conversion takes place in case of block transfers between 8 and 16 bit memory areas. Two bytes are converted into a word and vice versa.
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System Operations
Arithmetic Operations
ADD BN -128 to + 127 KF - 32768 to + 32767 DH 0 to FFFF FFFF N N N N N N N 12 11 0.57 0.18 Add byte constant (fixed-point number) to contents of ACCU 1-L (operation includes sign change); ACCUs 2 to 4 remain unchanged Add fixed-point constant (word) to contents of ACCU 1-L; ACCUs 2 to 4 remain unchanged Add fixed-point constant (double word) to contents of ACCU 11); ACCUs 2 to 4 remain unchanged Add two double word fixed-point numbers 2): ACCU 1 + ACCU 2; result can be evaluated via CC0/CC1 Subtract two double word fixed-point numbers 2): ACCU 2 - ACCU 1; result can be evaluated via CC0/CC1
ADD
N N
13
12
1.2
0.39
ADD
N N
20.2 1)
14
1.7
0.57
+D
N N
38-41
1)
17-19
1.6
0.64
-D
N N
42-46
1)
20-23
1.6
0.62
1) 2)
Operation possible from version 09 For changes to ACCU 2 and ACCU 3 see Arithmetic Operations, page 38
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System Operations
Jump Operation
JUR - 32768 to + 32767 N N N N N N N 15 11 1.2 0.68 Any jump within a function block
Other Operations
DI 1) 1) 1) 1) 1) 1) 1)
15-19
2)
18
2)
1.7 2) 0.93 2) 0.88
1.1 2)
Execute an operation 3) whose operation code is stored in a formal operand. The number of the formal operand must be stored in ACCU 1.
DO TAK
RS 60 to 63 -
1)
1)
1)
1)
1)
1)
1)
16 2) 24
17 9
2)
3) 0.71 2) Execute an operation whose operation code is stored in the system data
N N
0.18 2) Swap the contents of ACCU 1 and ACCU 2.
1)
The codes are evaluated and changed according to the operation executed. The execution time of the operation must be added.
3)
2)
The following operations are possible: - A.., AN.., O.., ON.., S.., R.., =.. with the areas I, Q, F, and S, - FR T, R T, SF T, SR T, SP T, SS T, SE T, FR C, R C, S C, CD C, CU C, - L.., T.. with the areas P, O, I, Q, F, S, D, RI, RJ, RS and RT, - L T, L C, - LC T, LC C, - JU=, JC=, JZ=, JN=, JP=, JM=, JO=, - SLW, SRW, - D, I, SED, SEE, - C DB, JU.., JC.., G DB, GX DX, CX DX, DOC FX, DOU FX
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System Operations

STS STW SIM LIM N N N N N N N N N N N N N N N N N N N N N N N N N N N N 2.0 1) 0.48 0.18 Stop operation with direct transition to SMOOTH STOP mode (communication capability with CPs) Stop operation resulting in HARD STOP mode (can only be reset by POWER OFF/ POWER ON) Set interrupt mask (bit pattern in ACCU 1 - 32 bit) Load interrupt mask (32 bit) into ACCU 1
1)
Add the time for the ISTACK operation (approx. 6.5 s)
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System Operations
Set Operations
SU RS 60.0 to 63.15 RT 0.0 to RT 255.15 RS 60.0 to 63.15 RT 0.0 to RT 255.15 N N N N N N Y 0.48 Set a bit in the RS area unconditionally
SU
N N
0.48
Set a bit in the RT area unconditionally
RU
N N
0.48
Reset a bit in the RS area unconditionally
RU
N N
0.48
Reset a bit in the RT area unconditionally
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System Operations
OperaOperands tion STL C C 1 Condition codes affected C C 0 O V RLO 1 dep. 2 affect. O 3 reload S 1 2 3 Execution = Operation with this CPU 922 CPU 928 times in s not possible CPU CPU 928B CPU 948 Function (only for CPU 928/928B)
Register to Register Transfer Operations

These operations transfer the contents of one register into another register. MAS MAB MSA MSB MBA N N N N N N N N N N N N N N N N N N N N N N N N N N N N N N N N N N N 9 12 11 11 12 0.88 0.62 0.69 0.69 0.62 Transfer the contents of ACCU 1 (bits 20 to 2 14) into the step address counter (SAC) Transfer the contents of ACCU 1 (bits 20 to 2 31) into the base address register (BR) Transfer the contents of the step address counter (SAC) into ACCU 1 Transfer the contents of the step address counter (SAC) into the base address register (BR) 1) Transfer the contents of the base address register (BR) into ACCU 1 Transfer the contents of the base address register (BR) (bits 20 to 2 14) into the step address counter (SAC)
MBS
N N
10
0.88
Load, Transfer and Arithmetic Operations with the

The base address register (32 bits) allows address arithmetic and indirect load and transfer operations without using the accumulators for addressing. The following applies: Absolute address = contents of base address register + constant MBR 0 to FF FFF - 32768 to + 32767 N N N N N N N 15
Base Address Register
1.1
Load a 20-bit constant into the base address register 2) Add a 16-bit constant to the contents of the base address register
ABR
N N
14
1.1
1)
The bits 2 15 to 231 are set to "0".
2)
The bits 2 20 to 2 31of the BR register are set to "0".
. 102
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103
System Operations
OperaOperands tion STL C C 1 Condition codes affected C C 0 O V RLO 1 dep. 2 affect. O 3 reload S 1 2 3 Execution = Operation with this CPU 922 CPU 928 times in s not possible CPU CPU 928B CPU 948 Function (only for CPU 948)
Register to Register Transfer Operations

These operations transfer the contents of one register into another register. MAS MAB MSA MSB MBA MBS N N N N N N N N N N N N N N N N N N N N N N N N N N N N N N N N N N N N N N N N N N 0.66 0.30 0.30 0.18 0.30 0.48 Transfer the contents of ACCU 1 (bits 20 to 2 19) into the step address counter (SAC) Transfer the contents of ACCU 1 (bits 20 to 2 19) into the base address register (BR) Transfer the contents of the step address counter (SAC) into ACCU 1 Transfer the contents of the step address counter (SAC) into the base address register (BR) 1) Transfer the contents of the base address register (BR) into ACCU 1 Transfer the contents of the base address register (BR) into the step address counter (SAC)
Load, Transfer and Arithmetic Operations with the

The base address register (20 bits) allows address arithmetic and indirect load and transfer operations without using the accumulators for addressing. The following applies: Absolute address = contents of base address register + constant MBR 0 to F FFFF - 32768 to + 32767 N N N N N N N
Base Address Register
0.48
Load a 20-bit constant into the base address register Add a 16-bit constant to the contents of the base address register
ABR
N N
0.39
1)
The bits 2 20 to 231 are set to "0".
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105
System Operations
Access to local, word-oriented memory: 1)

LRW - 32768 to + 32767 - 32768 to + 32767 - 32768 to + 32767 - 32768 to + 32767 N N N N N N N 22 3.6 0.59 Add the constant specified to the contents of the BR register and load the address of the word specified into ACCU 1-L 1). Add the constant specified to the contents of the BR register and load the address of the double word specified into ACCU 1 1). Add the constant specified to the contents of the BR register and transfer the contents of ACCU 1-L to the address of the word specified 1). Add the constant specified to the contents of the BR register and transfer the contents of ACCU 1 to the address of the double word specified 1).
LRD
N N
30
5.0
0.77
TRW
N N
21
3.4
0.59
TRD
N N
28
5.0
0.77
Test/set Busy location (global area): 1)

TSG - 32768 to + 32767 Y Y 0 N N N N 26
2)
4.7 2)
2.9 2)
Add the specified constant to the contents of the BR register, and test and set the Busy location 1) addressed.
1)
Possible absolute addresses: CPU 928/928B LRW/TRW 0000 to E3FF and E800 to EDFF 0000 to E3FE and E800 to EDFE 0000 to EFFF CPU 948 0 0000 to E FBFF
2)
Execution time for single processor operation and for bus access in multiprocessor operation. I/Os acknowledge within 0.1 s or proportionally longer execution times for longer acknowledgement time.
LRD/TRD TSG
0 0000 to E FBFE F 0000 to F FFFF
106
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System Operations
Access to global, byte-oriented memory:

LY GB LY GW LY GD TY GB TY GW TY GD - 32768 to + 32767 - 32768 to + 32767 - 32768 to + 32767 - 32768to + 32767 - 32768 to + 32767 - 32768 to + 32767 N N N N N N N 22
1)
3.0 1)
1.8 1)
Add the specified constant to the contents of the BR register and load the byte addressed into ACCU 1-LL 2). Add the specified constant to the contents of the BR register and load the word addressed into ACCU 1-L 2). Add the specified constant to the contents of the BR register and load the double word addressed into ACCU 1 2). Add the specified constant to the contents of the BR register and transfer the contents of ACCU 1-LL to the byte addressed 2). Add the specified constant to the contents of the BR register and transfer the contents of ACCU 1-L to the word addressed 2). Add the specified constant to the contents of the BR register and transfer the contents of ACCU 1 to the double word addressed 2).
N N
26
1)
3.9 1)
2.4 1)
N N
31
1)
5.5 1)
4.4 1)
N N
21
1)
2.9 1)
1.8 1)
N N
25
1)
3.7 1)
2.5 1)
N N
30
1)
5.3 1)
4.0 1)
1)
Execution time for single processor operation and for bus access in multiprocessor operation. I/Os acknowledge within 0.1s or proportionally longer execution times for longer acknowledgement time.
2)
Possible absolute addresses: CPU 928/928B LY GB/TY GW LY GW/TY GW LY GD/TY GD 0000 to EFFF 0000 to EFFE 0000 to EFFC CPU 948 F 0000 to F FFFF F 0000 to F FFFE F 0000 to F FFFC
108
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System Operations
Access to global, word-oriented memory:

LW GW LW GD TW GW TW GD - 32768 to + 32767 - 32768 to + 32767 - 32768 to + 32767 - 32768 to + 32767 N N N N N N N 27
1)
4.3 1)
1.8 1)
Add the specified constant to the contents of the BR register and load the word addressed into ACCU 1-L 2). Add the specified constant to the contents of the BR register and load the double word addressed into ACCU 1-L 2). Add the specified constant to the contents of the BR register and load the word addressed into ACCU 1-L 2). Add the specified constant to the contents of the BR register and transfer the contents of ACCU 1 to the double word addressed 2).
N N
33
1)
5.7 1)
2.4 1)
N N
26
1)
4.0 1)
1.8 1)
N N
32
1)
5.4 1)
2.5 1)
Open page:
ACR N N N N N N N 11
1)
0.571)
0.32 1)
Open the page whose number is in ACCU 1-L 3).
Test/set Busy location (page area):

TSC - 32768 to + 32767 Y Y 0 N N N N 29
1)
5.3 1)
3.6 1)
Add the specified constant to the contents of the BR register and test/set the Busy location 2) addressed on the page opened.
1)
2)
Possible absolute addresses: CPU 928/928B LW GB/TW GW LW GW/ TW GW 0000 to EFFF 0000 to EFFE F400 to FBFF CPU 948 F 0000 to F FFFF F 0000 to F FFFE F F400 to F FBFF
3)
Possible values: 0 to 255
TSC
110
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System Operations
Access to byte-oriented pages:

LY CB LY CW LY CD - 32768 to + 32767 - 32768 to + 32767 - 32768 to + 32767 - 32768 to + 32767 N N N N N N N 29
1)
3.6 1)
2.6 1)
Add the specified constant to the contents of the BR register and load the byte addressed from the page opened into ACCU 1-LL 2). Add the specified constant to the contents of the BR register and load the word addressed from the page opened into ACCU 1-L 2). Add the specified constant to the contents of the BR register and load the double word addressed from the page opened into ACCU 1 2). Add the specified constant to the contents of the BR register and transfer the contents of ACCU 1-LL to the byte addressed on the page opened 2). Add the specified constant to the contents of the BR register and transfer the contents of ACCU 1-L to the word addressed on the page opened 2). Add the specified constant to the contents of the BR register and transfer the contents of ACCU 1 to the double word addressed on the page opened 2).
N N
30
1)
4.5 1)
3.4 1)
N N
34
1)
6.1 1)
5.2 1)
TY CB
N N
28
1)
3.5 1)
2.5 1)
TY CW
- 32768 to + 32767
N N
29
1)
4.2
1)
3.3
1)
TY CD
- 32768 to + 32767
N N
34
1)
5.9 1)
4.8 1)
1)
2)
Possible absolute addresses: CPU 928/928B LY CB/TY CB LY CW/TY CW LY CD/TY CD F400 to FBFF F400 to FBFE F400 to FBFC CPU 948 F F400 to F FBFF F F400 to F FBFE F F400 to F FBFC
112
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113
System Operations
Access to word-oriented pages: 1)

LW CW - 32768 to + 32767 N N N N N N N 34
1)
4.9 1)
2.6 1)
Add the specified constant to the contents of the BR register and load the word addressed with the contents of the BR register from the page opened into ACCU 1-L 2). Add the specified constant to the contents of the BR register and load the double word addressed with the contents of the BR register from the page opened into ACCU 1 2). Add the specified constant to the contents of the BR register and transfer the contents of ACCU 1-L to the word addressed with the contents of the BR register on the page opened 2). Add the specified constant to the contents of the BR register and transfer the contents of ACCU 1 to the double word addressed with the contents of the BR register on the page opened 2).
LW CD
- 32768 to + 32767
N N
38
1)
6.3 1)
3.4 1)
TW CW
- 32768 to + 32767
N N
33
1)
4.7 1)
2.5 1)
TW CD
- 32768 to + 32767
N N
37
1)
6.0 1)
3.3 1)
1)
Execution time for single processor operation and for bus access in multiprocessor operation. l/Os acknowledge within 0.1s or proportionally longer execution times for longer acknowledgement time.
2)
Possible absolute addresses: CPU 928/928B LW CW/TW CW LW CD/TW CD F400 to FBFF F400 to FBFE CPU 948 F F400 to F FBFF F F400 to F FBFE
114
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115
Machine Code Listing

Explanation of subscripts a + byte address b + bit address c + formal operand address d + operand value e + constant f + block number g + word address h + number of shifts i + relative jump destination address k + register number l + block length in bytes m + jump displacement (16 bits) n + semaphore number o + block length in words B0 to B5: 1st to 6th machine code byte
Machine Code B0 L 0 0 0 0 0 0 0 0 0 0 0 R 0 1 2 3 4 5 6 7 8 8 9 L 0 0 0d 0l 0d 0 0c 0c 0 8 0 B1 R 0 0 0d 0l 0d 0 0c 0c 0 0 0 L B2 R L B3 R NOP 0 CFW L TNB FR BEC FR= A= IA RA CSW T T Operation Operand
116
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Machine Code B0 L 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 R A B C D E F 0 0 0 0 0 0 1 2 3 4 5 6 7 8 9 A B C D L 0d 0d 0d 0i 0c 0c 0e 8 8 8 8 F 0e 0d 0d 0d 0i 0c 0c 0d 0e 0d 0d 0d 0f B1 R 0d 0d 0d 0i 0c 0c 0e 2 3 4 5 F 0e 0d 0d 0d 0i 0c 0c 0d 0e 0d 0d 0d 0f L B2 R L B3 R L T LD JO= LD= O= BLD BLD BLD BLD BLD BLD I L T SF JP= SFD= S= DO D L T SE JC FD FD T FB RS FW FW T 0-255 130 131 132 133 255 FY FY T Operation Operand
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Machine Code B0 L 1 1 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 3 3 R E F 0 1 1 1 1 1 1 2 3 4 5 6 7 8 9 A B C D E F 0 0 L 0c 0c 0f 2 4 6 8 A C 0d 0d 0d 0i 0c 0c 0e 0h 0d 0d 0d 0i 0c 0c 0 0 B1 R 0c 0c 0f 0 0 0 0 0 0 0d 0d 0d 0i 0c 0c 0e 0h 0d 0d 0d 0i 0c 0c 1 2 0e 0e 0e 0e 0e 0e 0e 0e L B2 R L B3 R SEC= == C >F <F ><F !=F >=F <=F L T SD JM= SD= AN= L SLD L T SS JU= SSU= ON= L L KC KT DR DR T KB DL DL T DB Operation Operand
118
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Machine Code B0 L 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3
1)
B1 R 0 0 0 0 0 1 1 1 1 1 1 2 3 4 5 6 7 8 8 9 9 9 9 9 L 0 1 2 4 8 2 4 6 8 A C 0d 0d 0d 0i 0c 0c 0 4 2 4 6 8 A R 4 0 0 0 0 0 0 0 0 0 0 0d 0d 0d 0i 0c 0c 0 0 0 0 0 0 0 0e 0e L 0e 0e 0e 0e 0e
B2 R 0e 0e 0e 0e 0e L 0e 0e 0e 0e 0e
B3 R 0e 0e 0e 0e 0e
Operation
Operand
L L L L L >G <G ><G !=G >=G <=G L T SP JN= SP= RB=
KF KS KY KH KM
DW DW T
0e 0e
0e 0e
0e 0e
L L >D <D ><D !=D >=D
KG 1) DH 1)
3-word command with B4 and B5, filled with 0 e
C79000-K8576-C124-03
119
Machine Code B0 L 3 3 3 3 3 3 3 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 R 9 A B C D E F 0 1 2 3 4 5 6 7 8 9 A A B B C D E F L C 0d 0d 0d 0f 0c 0c 0 0 0d 0o 0d 0i 0c 0d 0 0 0d 8d 0d 8d 0d 0f 0d 0d B1 R 0 0d 0d 0d 0f 0c 0c 0k 0 0d 0o 0d 0i 0c 0d 0k 0 0d 0d 0d 0d 0d 0f 0d 0d L B2 R L B3 R <=D L T R JU RD= LW= LIR AW L TNW FR JZ= L= L TIR OW L L T T LD JC DO L IB QB IB QB C OB FW RT RJ C C DD DD T FB Operation Operand
120
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Machine Code B0 L 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 6 6 6 6 6
1)
B1 R 0 1 2 2 3 3 4 5 6 7 8 9 A A B B C D F 0 0 0 0 0 L 0e 0 0d 8d 0d 8d 0d 0f 0c 0d 0 0 0d 8d 0d 8d 0d 0f 0d 0 0 0 0 0 R 0e 0 0d 0d 0d 0d 0d 0f 0c 0d 0 0 0d 0d 0d 0d 0d 0f 0d 0 3 4 5 7 0e 0e L
B2 R L
B3 R
Operation
Operand
ADD XOW L L T T CD JC LDW= L 0e 0e 0e ADD -F L L T T S JC L :F :G xF 0e 0e 0e ADD xG
BN
IW QW IW QW C PB
OW KF
ID QD ID QD C SB OY
DH 1)
3-word command with B4 und B5, filled with 0 e
C79000-K8576-C124-03
121
Machine Code B0 L 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 R 0 0 0 0 0 0 1 2 3 4 5 5 6 7 8 8 8 8 8 8 8 8 8 8 8 L 0 0 0 0 0 0 0 0d 0d 0h 0 0 0c 0d 0 0h 0 0 0 0 0 0 0 0 0 B1 R 8 9 B C D F 0h 0d 0d 0h 0 1 0c 0d 0 1 2 3 4 5 6 7 8 A B 0e 0e 0e 0e 0e 0e 0e 0e 0e 0e 0e 0e 0e 0e 0e 0e 0 0 0i 0i L B2 R L B3 R ENT -D -G JOS= +D +G SLW L T RLD BE BEU T= T LRW SSW GFD TRW LRD TRD FDG CSD DUF DUD LDI A1 RJ RS RS Operation Operand
122
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Machine Code B0 L 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 7 R 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 9 A B C D E F 0 L 0 0 0 1 2 2 2 4 4 4 6 8 9 9 9 A A 0 0d 0d 0d 0f 0d 0d 0 B2 R C E F 9 9 B F 9 B F 9 9 9 B F B F 0h 0d 0d 0d 0f 0d 0d 0 L B3 R L B4 R DEF DED TDI MAS MAB LDI TDI MSA LDI TDI MSB MBA MBS LDI TDI LDI TDI SRW L T CU JU DO T STS RI RI C OB DW RT BA BA BR BR SA SA A2 A2 A1 Operation Operand
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123
Machine Code B0 L 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 L 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 2 2 2 2 3 B2 R 2 3 4 B C D E E E E F 5 5 5 5 E E E E F 5 5 5 5 8 0 4 8 C 0 0b 0b 0b 0b 0b 0g 0g 0g 0g 0a 0g 0g 0g 0g 0a 0 4 8 C 0 4 8 C 0b 0b 0b 0b 0b 0b 0b 0b 0g 0g 0g 0g 0g 0g 0g 0g 0g 0g 0g 0g 0g 0g 0g 0g 0 4 8 C 0b 0b 0b 0b 0g 0g 0g 0g 0g 0g 0g 0g 0m 0m 0m 0m L B3 R L B4 R TAK STP STW JUR LIM SIM RU SU TBN TB TXW RU SU TBN TB RU SU TBN TB TXB RU SU TBN TB RU T T T T I C C C C RJ RJ RJ RJ RT RT RT RT Operation Operand
124
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Machine Code B0 L 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 2 L 3 3 3 3 3 3 3 4 4 4 4 4 4 4 4 4 4 4 4 5 5 5 5 0h 0d B2 R 8 8 8 8 8 8 8 6 6 6 6 7 7 7 7 9 9 9 9 7 7 7 7 0h 0d L 0 4 4 8 8 C C 0 4 8 C 0 4 8 C 0 4 8 C 0 4 8 C B3 R 0b 0b 0b 0b 0b 0b 0b 0b 0b 0b 0b 0b 0b 0b 0b 0b 0b 0b 0b 0b 0b 0b 0b L 8a 0a 8a 0a 8a 0a 8a 0g 0g 0g 0g 0g 0g 0g 0g 0a 0a 0a 0a 0g 0g 0g 0g B4 R 0a 0a 0a 0a 0a 0a 0a 0g 0g 0g 0g 0g 0g 0g 0g 0a 0a 0a 0a 0g 0g 0g 0g RU SU SU TBN TBN TB TB RU SU TBN TB RU SU TBN TB RU SU TBN TB RU SU TBN TB SSD L PY Q I Q I Q I Q D D D D RI RI RI RI F F F F RS RS RS RS Operation Operand
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Machine Code B0 L 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 R 3 4 5 6 7 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 L 0d 0h 0f 0c 0d 0 0 0 0 0 0 0 0 0e 0 0 0 0 1 1 1 1 2 2 2 B2 R 0d 0h 0f 0c 0d 0 1 2 3 4 5 6 7 9 A B D E 0 B D E B D E 0b 0e 0e 0b 0e 0e 0a 0e 0e 0a 0e 0e 0a 0e 0e 0a 0e 0e 0a 0e 0e 0a 0e 0e 0 0 1 0 0 0 0 0e 0o 0b 0e 0e 1 9 1 0 0 0 0 0e 0o 0a 0e 0e 0f 0f 0f 0f 0f 0n 0n 0e 0o 0a 0e 0e 0c 0c 0f 0f 0f 0n 0n 0e 0o 0a 0e 0e L B3 R L B4 R T RRD JU DO= T IAE DOU DOC CX GX G SED SEE MBR ABR A LYCB LYGB RAE O LYCW LYGW S LYCD LYGD S S S FX FX DX DX DB OW PB PY Operation Operand
126
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Machine Code B0 L 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 R 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 L 3 3 3 3 3 3 3 3 3 4 5 5 5 6 6 6 8 8 9 9 A A A B C B2 R B D F F F F F F F B B D E B D E D E D E B D E B B 0 1 2 3 4 5 6 0b 0b 0e 0e 0b 0e 0e 0e 0e 0e 0e 0 0e 0e 0 0 0b 0b 0b 0b 0b 0b 0b 0a 0a 0e 0e 0a 0e 0e 0e 0e 0e 0e 0d 0e 0e 0d 0d 0g 0g 0g 0g 0g 0g 0g 0a 0a 0e 0e 0a 0e 0e 0e 0e 0e 0e 0d 0e 0e 0d 0d 0g 0g 0g 0g 0g 0g 0g 0a 0a 0e 0e 0a 0e 0e 0e 0e 0e 0e 0d 0e 0e 0d 0d L 0b B3 R 0a L 0a B4 R 0a = ACR A O AN ON S R = AN ON LWCW LWGW R LWCD LWGD TYCB TYGB TYCW TYGW L TYCD TYGD T L SY SW SY S D D D D D D D S S S Operation Operand
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Machine Code B0 L 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 8 8 9 9 A A B B B R 8 8 8 8 8 8 8 8 8 9 A B C D E F 0b 8b 0b 8b 0b 8b 0b 8 9 L C C D D D E E E F 0 0d 0d 0d 0f 0 0d 0a 0a 0a 0a 0a 0a 0a 0d 0d B1 R D E B D E B D E B 0 0d 0d 0d 0f 0 0d 0a 0a 0a 0a 0a 0a 0a 0d 0d L 0e 0e 0 0e 0e 0 0e 0e 0 B2 R 0e 0e 0d 0e 0e 0d 0e 0e 0d L 0e 0e 0d 0e 0e 0d 0e 0e 0d B3 R 0e 0e 0d 0e 0e 0d 0e 0e 0d TSC TSG T TWCW TWGW L TWCD TWGD T +F L T R JU DI T A O S = AN ON R A O OY F F F F F F F C C PW PW C SB SD SD SW Operation Operand
128
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Machine Code B0 L B B B B B B C C C C D D D D E E E E F F F F F F F R A B C D E F 0b 0b 8b 8b 0b 0b 8b 8b 0b 0b 8b 8b 0b 0b 8 9 A B C L 0 0 0d 0d 0 0 0a 8a 0a 8a 0a 8a 0a 8a 0a 8a 0a 8a 0a 8a 0d 0d 0i 0 0d B1 R 0 0 0d 0d 0 0 0a 0a 0a 0a 0a 0a 0a 0a 0a 0a 0a 0a 0a 0a 0d 0d 0i 0 0d L B2 R L B3 R A( O( AN ON BAS ) A A O O S S = = AN AN ON ON R R A O JC= O AN T I Q I Q I Q I Q I Q I Q I Q T T C C Operation Operand
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Machine Code B0 L F F F R D E F L 0d 0 F B1 R 0d 0 F L B2 R L B3 R ON BAF NOP 1 T Operation Operand
130
C79000-K8576-C124-03
Alphabetical Index of Operations

(with Machine Code)
For explanation of subscripts see page 116.
Operation A
Operand C D F I Q S T
Page 10 10 10 10 10 10 10
Machine Code B 8 0d 0d 7 8 3 F 8 0b 0a 0a C 0b0a 0a C 0b 8a 0a 7 8 0 B F 8 0d 0d B A 0 0 0 7 0c 0c 7 8 0 A 7 8 3 D 5 0 0e 0e 6 0 0 5 0e 0e 0e 0 e 0 e 0e 0e 0 e 0e 0e 0e 0 e 0o 0o 0o 0o 0b 0a 0a 0a 0 0b 0g 0g
A( A= ABR ACR ADD BN DH KF AN C D F
--Formal oper. Constant ---
16 56 102 110 94 94 94 12 12 12
5 8 0 0 B C 0d 0d 7 8 3 F A 0b 0a 0a
4 0 b 0g 0g
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Operation AN
Operand I Q S T
Page 10 10 12 12 56 56 80 80 52 52 52 54 54 54 54 54 54 50 36
Machine Code E 0b 0a 0a E 0b 8a 0a 7 8 4 B F C 0d 0d 2 7 0c 0c 4 1 0 0 F E 0 0 B E 0 0 6 5 0 0 0 5 0 0 6 5 0 1 1 0 0e 0e 1 0 8 2 1 0 8 3 1 0 8 4 1 0 8 5 1 0 F F 2 0 0 f 0f 5 4 0d 0d 0 1 0 0 6 8 0 7 0 9 0 0 6 C 0d 0d 7 8 0 3 1 9 0e 0e 6 8 0 E 6 8 0 C 1 1 0f 0f 0b 0a 0a 0a
AN= AW BAF BAS BE BEC BEU BLD
Formal oper. ------------0 - 255 130 131 132 133 255
C CD CFW CSD CSW CU CX D DED DEF
DB C ------C DX 0 - 255 -----
74 74 74 36 50 82 74 74
132
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Operation DI DO
Operand --DW FW RS
Page 96 84 84 96 84 50 48
Machine Code 7 E 0 0 6 E 0d 0d 4 E 0d 0d 1 8 0d 0d 7 6 0c 0c 7 8 0 2 7 8 0 1 6 8 0 A 6 8 0 8 6 0 0 8 6 8 0 6 4 4 0d 0d 0 4 0d 0d 0 6 0c 0c 7 8 0 5 6 8 0 2 7 8 0 4 1 1 0e 0e 0 8 0 0 7 8 0 0 1 D 0f 0f 4 D 0f 0f 5 5 0f 0f 5 D 0f 0f F A 0i 0i 2 5 0i 0i 3 5 0i 0i 0 D 0i 0i 133 0 0 0f 0f 0 0 0f 0f 0 9 0f 0f 0 1 0f 0f
DO = DOC DOU DUD DUF ENT FDG FR
Formal oper. FX FX --------C T
74 74 82 74 68 68 66 52
FR = G GFD GX I IA IAE JC
Formal oper. DB --DX 0 - 255 ----FB OB PB SB
74 52 82 80 80 48 50 48 50 78 78 78 78
JC = JM = JN = JO =
Symb. addr. Symb. addr. Symb. addr. Symb. addr.
C79000-K8576-C124-03
Operation JOS = JP = JU
Operand Symb. addr. Symb. addr. FB OB PB SB
Page 78 78 48 48 48 48 78 96 78 26 24 22 22 24 24 22 20 20 20 20 20 24 24 24 24
Machine Code 6 0 0 C 1 5 0i 0i 3 D 0f 0f 6 D 0f 0f 7 5 0f 0 f 7 D 0f 0 f 2 D 0i 0i 7 0 0 B 4 5 0i 0i 4 2 0d 0d 3 A 0d 0d 3 8 4 0 2 2 0d 0d 2 A 0d 0d 3 2 0d 0d 1 A 0d 0d 1 2 0d 0d 0 A 0d 0d 4 A 0d 0d 5 A 0d 0d 5 2 0d 0d 2 8 0e 0e 3 0 0 1 3 0 0 4 3 8 0 0 0e 0e 0e 0e 0e 0e 0e 0e 0e 0e 0e 0e 0e 0e 0e 0e 0e 0e 0e 0e 0e 0e 0e 0e 0m 0m 0m0m 0 0 0i 0i
JU = JUR JZ = L
Symb. addr. Constant Symb. addr. C DD DH DL DR DW FD FW FY IB ID IW KB KC KF KG
134
C79000-K8576-C124-03
Operation L
Operand KH KM KS KT KY OW OY PW PY QB QD QW RI RJ RS RT SD SW SY T
Page 24 24 24 24 24 26 26 26 26 20 20 20 70 70 70 70 22 22 22 26 70 26 26 88 88 88
Machine Code 3 0 4 0 3 0 8 0 3 0 1 0 3 0 0 2 3 0 2 0 5 7 0d 0d 5 F 0d 0d 7 A 0d 0d 7 2 0d 0d 4 A 8d 0d 5 A 8d 0d 5 2 8d 0d 6 A 0d 0d 4 7 0d 0 d 6 2 0 d 0d 4 F 0d 0d 7 8 E B 7 8 C B 7 8 A B 0 2 0d 0d 4 6 0c 0c 4 C 0d 0d 0 C 0d 0d 6 8 0 B 6 8 2 B 6 8 9 B 0 0d 0d 0d 0 0d 0d 0d 0 0d 0d 0d 0e 0e 0e 0e 0e 0e 0e 0e 0e 0e 0e 0e 0e 0e 0 e 0 e 0e 0e 0e 0e
L= LC
Formal oper. C T
LDI
A1 A2 BA
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Operation LDI
Operand BR SA
Page 88 88 70 70 98 86 106 106 70 114 114 110 110 112 112 112 108 108 108 104 104 104 104 104 104 104 54 54
Machine Code 6 8 A B 6 8 4 B 0 E 0c 0c 5 6 0c 0c 7 0 0 C 4 0 0 0k 6 8 0 4 6 8 0 0 3 F 0c 0c 7 8 6 D 7 8 5 D 7 8 6 E 7 8 5 E 7 8 0 D 7 8 2 D 7 8 1 D 7 8 0 E 7 8 2 E 7 8 1 E 6 8 2 9 6 8 1 9 6 8 8 9 7 8 0e 9 6 8 9 9 6 8 4 9 6 8 6 9 0 0 0 0 F F F F 0e 0e 0e 0e 0e 0e 0e 0e 0e 0e 0e 0e 0e 0e 0e 0e 0e 0e 0e 0e 0e 0e 0e 0e 0e 0e 0e 0e 0e 0e 0e 0e 0e 0e 0e 0e 0e 0e 0e 0e 0e 0e 0e 0e 0e 0e 0e 0e 0e 0e 0e 0e
LD = LDW = LIM LIR LRD LRW LW = LW CD LW CW LW GD LW GW LY CB LY CD LY CW LY GB LY GD LY GW MAB MAS MBA MBR MBS MSA MSB NOP 0 NOP 1
Formal oper. Formal oper. --Register no. Constant Constant Formal oper. Constant Constant Constant Constant Constant Constant Constant Constant Constant Constant ------Constant -----------
136
C79000-K8576-C124-03
Operation O
Operand C D F I Q S T ---
Page 14 12 12 12 12 12 14 14 16 56 14 14 14 14 14 14 14 56 56 36 18 18 16 16 18 34
Machine Code B 9 0d 0d 7 8 3 F 8 8b 0a 0a C 8b 0a 0a C 8b 8a 0a 7 8 1 B F 9 0d 0d F B 0 0 B B 0 0 0 F 0c 0c B D 0d 0d 7 8 3 F A 8b 0a 0a E 8b 0a 0a E 8b 8a 0a 7 8 5 B F D 0d 0d 2 F 0c 0c 4 9 0 0 7 C 0d 0d 7 8 3 F B 0b 0a 0a F 0b 0a 0a F 0b 8a 0a 7 8 6 B 3 C 0d 0d 0 8 8 0 0b 0a 0a 0a 5 0 b 0g 0g 0b 0a 0a 0a 3 0b 0g 0g 0b 0a 0a 0a 1 0b 0g 0g
O( O= ON
--Formal oper. C D F I Q S T
ON = OW R
Formal oper. --C D F I Q S T
RA
---
80
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Operation RAE RB = RD = RLD RRD RU
Operand --Formal oper. Formal oper. Constant Constant C D F I Q RI RJ RS RT T
Page 80 62 62 76 76 64 64 64 64 64 64 64 100 100 64 36 16 16 16 16 16 62 34 66 34 66 82
Machine Code 7 8 1 0 3 7 0c 0c 3 E 0c 0c 6 4 0h 0h 7 4 0h 0h 7 0 1 5 7 0 4 6 7 0 4 9 7 0 3 8 7 0 3 8 7 0 4 7 7 0 1 E 7 0 5 7 7 0 0 E 7 0 2 5 5 C 0d 0d 7 8 3 F 9 0b 0a 0a D 0b 0a 0a D 0b 8a 0a 7 8 2 B 1 7 0c 0c 2 4 0d 0d 2 6 0c 0c 1 C 0d 0d 1 E 0c 0c 7 8 0 6 0 0 0n 0n 0b 0a 0a 0a 4 0 b 0g 0g 0 0b 0g 0g 0 0b 0g 0g 0 0b 0g 0g 0 0b 0a 0a 0 0b 8a 0a 0 0b 0g 0g 0 0b 0g 0g 0 0b 0g 0g 0 0b 0g 0g 0 0b 0g 0g
C D F I Q S
S= SD SD = SE SEC = SED
Formal oper. T Formal oper. T Formal oper. Constant
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Operation SEE SF SFD = SIM SLD SLW SP SP = SRW SS SSD SSU = SSW STP STS STW SU
Operand Constant T Formal oper. --Constant Constant T Formal oper. Constant T Constant Formal oper. Constant ------C D F I Q RI RJ RS RT T
Page 82 34 66 98 76 76 34 66 76 34 76 66 76 54 98 98 62 64 62 62 62 64 64 100 100 62
Machine Code 7 8 0 7 1 4 0d 0d 1 6 0c 0c 7 0 0 D 2 9 0h 0h 6 1 0 0h 3 4 0d 0d 3 6 0c 0c 6 9 0 0h 2 C 0d 0d 7 1 0h 0h 2 E 0c 0c 6 8 0h 1 7 0 0 3 7 0 0 0 7 0 0 4 7 0 1 5 7 0 4 6 7 0 4 9 7 0 3 8 7 0 3 8 7 0 4 7 7 0 1 E 7 0 5 7 7 0 0 E 7 0 2 5 4 0b 0g 0g 4 0b 0g 0g 4 0b 0g 0g 4 0b 0a 0a 4 0b 8a 0a 4 0b 0g 0g 4 0b 0g 0g 4 0b 0g 0g 4 0b 0g 0g 4 0b 0g 0g 0 0 0n 0n
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Operation T
Operand DD DL DR DW FD FW FY IB ID IW OW OY PW PY QB QD QW RI RJ RS RT SD SW SY
Page 30 30 30 30 28 28 28 28 28 28 32 32 32 32 28 28 28 72 72 72 72 30 30 30 70 58 58
Machine Code 3 B 0d 0d 2 3 0d 0d 2 B 0d 0d 3 3 0d 0d 1 B 0d 0d 1 3 0d 0d 0 B 0d 0d 4 B 0d 0d 5 B 0d 0d 5 3 0d 0d 7 7 0d 0d 7 F 0d 0d 7 B 0d 0d 7 3 0d 0d 4 B 8d 0d 5 B 8d 0d 5 3 8d 0d 6 B 0d 0d 6 7 0d 0d 6 3 0d 0d 6 F 0d 0d 7 8 F B 7 8 D B 7 8 B B 6 6 0c 0 c 7 0 1 5 7 0 4 6 C 0b 0g 0g C 0b 0g 0g 0 0d 0d 0d 0 0 d 0 d 0d 0 0 d 0d 0d
T= TB
Formal oper. C D
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Operation TB
Operand F I Q RI RJ RS RT T
Page 58 58 58 58 58 58 58 58 60 60 60 60 60 60 60 60 60 60
Machine Code
0b 0a 0a 0b 0a 0a 0b 8a 0a 0b 0g 0g 0b 0g 0g 0b 0g 0g 0b 0g 0g 0b 0g 0g
7 0 7 0 7 0 7 0 7 0 7 0 7 0 7 0
4 3 3 4 1 5 0 2
9 8 8 7 E 7 E 5
C C C C C C C C
TBN
C D F I Q RI RJ RS RT T
7 0 1 5 7 0 4 6 7 0 4 9 7 0 3 8 7 0 3 8 7 0 4 7 7 0 1 E 7 0 5 7 7 0 0 E 7 0 2 5 7 0 0 2 6 8 0 F 6 8 2 F 6 8 9 F 6 8 A F 6 8 4 F 4 8 0 0k 0 3 0l 0l 4 3 0o 0o
8 0b 0g 0g 8 0b 0g 0g 8 0b 0a 0a 8 0b 0a 0a 8 0b 8a 0a 8 0b 0g 0g 8 0b 0g 0g 8 0b 0g 0g 8 0b 0g 0g 8 0b 0g 0g
TAK TDI A1 A2 BA BR SA TIR TNB TNW
---
96 88 88 88 88 88 86 90 90
Register no. Constant Constant
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Operation TRD TRW TSC TSG TW CD TW CW TW GD TW GW TXB TXW TY CB TY CD TY CW TY GB TY GD TY GW XOW ) =
Operand Constant Constant Constant Constant Constant Constant Constant Constant ----Constant Constant Constant Constant Constant Constant ---
Page 106 106 110 106 114 114 110 110 92 92 112 112 112 108 108 108 56 16
Machine Code 6 8 0 5 6 8 0 3 7 8 C D 7 8 C E 7 8 E D 7 8 D D 7 8 E E 7 8 D E 7 0 1 F 7 0 0 F 7 8 8 D 7 8 A D 7 8 9 D 7 8 8 E 7 8 A E 7 8 9 E 5 1 0 0 B F 0 0 7 8 3 F 9 8b 0a 0a D 8b 0a 0a D 8b 8a 0a 7 8 3 B 1 F 0c 0c 3 9 2 0 3 9 4 0 3 9 6 0 3 9 8 0 0b 0a 0a 0a 6 0b 0g 0g 0e 0e 0e0e 0e 0e 0e0e 0e 0e 0e0e 0e 0e 0e0e 0e 0e 0e0e 0e 0e 0e0e 0e 0e 0e0e 0e 0e 0e0e 0e 0e 0e0e 0e 0e 0e0e 0e 0e 0e0e 0e 0e 0e0e 0e 0e 0e0e 0e 0e 0e0e
D F I Q S
18 18 18 18 18 62 46 46 46 46
== >D <D ><D !=D
Formal oper. ---------
142
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Operation >=D <=D +D -D :F xF +F -F !=F >F <F ><F >=F <=F >G <G ><G != G >=G <=G :G xG +G -G
Operand -------------------------------------------------
Page 46 46 94 94 38 38 38 38 42 42 42 42 42 42 44 44 44 44 44 44 40 40 40 40
Machine Code 3 9 A 0 3 9 C 0 6 0 0 D 6 0 0 9 6 0 0 0 6 0 0 4 7 9 0 0 5 9 0 0 2 1 8 0 2 1 2 0 2 1 4 0 2 1 6 0 2 1 A 0 2 1 C 0 3 1 2 0 3 1 4 0 3 1 6 0 3 1 8 0 3 1 A 0 3 1 C 0 6 0 0 3 6 0 0 7 6 0 0 F 6 0 0 B
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Explanatory Notes on the Condition Codes

Structure of the Condition Code Byte
Word codes C C1 Bit 7 CC0 6 OV 5 OS 4 OR 3 Bit codes STA 2 RL O E RA B 1 0
Abbreviations CC 0 / CC 1 OV
Description Condition codes 0/1 (see Evaluation of CC 0 and CC 1) Overflow. This condition code is set if the maximum number range is exceeded during arithmetic operations. Stored overflow. The overflow bit is stored. This is an indication of whether and when an overflow error has occurred in the course of arithmetic operations. Internal condition code of the processor relating to AND and OR operations. STATUS; Signal status of the bit scanned. Result of Logic Operation. Contains the result of individual bit operations and comparison operations. First bit scanned. ERAB = 0 identifies the beginning and the end of a string of logic operations. The first operation of the string sets the ERAB bit to "1". Only at the end of the string is the ERAB bit reset (e.g. by a set/reset operation).
OS
OR STA RLO
ERAB
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Evaluation of CC0 and CC1
C C 1 0
C C 0 0
Arithmetic Operations Result =0
Digital Logic Operations Result =0
Comparison Operations
Shift Operations
For SED, SEE Semaphore has been set -
Jump Operations Executed JZ
ACCU 2 shifted = bit ACCU 1 = 0
Result <0 Result >0
ACCU 2 < ACCU 1
JM JN JP JN
Result 0
ACCU 2 shifted > bit ACCU 1 = 1 -
Semaphore is set now -
Divide by 0
JN
1)
1)
not executed with CPU 948
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List of Organization Blocks

= OB available on this CPU Organization Block CPU 922 CPU 928 CPU 928B CPU 948 = OB not available on this CPU Function
OBs for Program Processing

OB 1 OB 2 OB 3 to OB 8 OB 6 OB 9 OB 10 OB 11 OB 12 OB 13 OB 14 OB 15 OB 16 OB 17 OB 18
1) 2) 1) 1) 1)
OB for cyclic program processing

3)
Interrupt-driven program processing Interrupt-driven program processing Delay interrupt Time-driven program processing
3)
3)
3)
10 ms 20 ms 50 ms 100 ms 100 ms 200 ms 500 ms 1s 2s 5s
10 ms 20 ms 50 ms 100 ms 200 ms 500 ms 1s 2s 5s
0.1 s 2) 3) 0.2 s 2) 3) 0.5 s 2) 3) 1.0 s 2) 3) 2.0 s 2) 3) 5.0 s 2) 3) 10.0 s 2) 3) 20.0 s 2) 3) 50.0 s 2) 3)

3)
Time interrupts with set time grid
alternative FB 0 Default setting, can be changed via DX 0
Details about the functions of these OBs of the CPU 948 can be found in the "CPU 948 Programming Guide".
146
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= OB available on this CPU Organization Block CPU 922 CPU 928 CPU 928B CPU 948 = OB not available on this CPU Function
OBs for Program Processing (continued)

OB 31 OB 39
1)
Set cycle monitoring time Organization of the cyclic program for communication in SMOOTH STOP
OBs for Start-up Procedures

OB 20 OB 21 OB 22 OB 38
1)
Manual or automatic cold restart (can be set in DX 0) Manual warm restart Automatic warm restart after power failure Organization of the restart behavior for communication in SMOOTH STOP
The setting of the cycle monitoring time via OB 31 has a higher priority than the setting via DX 0 (CPU 948).
148
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149

= OB not available on this CPU Organization Block CPU 922 CPU 928 CPU 928B = OB not available on this CPU Cause of error Reaction without OB
OBs for Handling Controller Errors in the CPU 922/928/928B

OB 19 OB 23 Call of a block not programmed (LZF) Timeout in the case of direct access to the I/O module (QVZ) Timeout when updating the process image and transferring interprocessor communication flags Addressing error (ADF) Scan time exceeded (ZYK-FE) Substitution error (BCF) Stop by PG function/Stop switch/S5-BUS (ABBR) Operation error (BCF) Parameter assignment error (BCF) Other execution time errors (LZF) Stop none
OB 24 OB 25 OB 26 OB 27 OB 28 OB 29 OB 30 OB 31
1)
none Stop Stop Stop Stop1) Stop Stop Stop
Switchover to the STOP state always occurs independently of whether OB 28 is programmed and how it is programmed.
150
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151

= OB available on this CPU Organization Block CPU 922 CPU 928 CPU 928B = OB not available on this CPU Cause of error Reaction without OB
OBs for Handling Controller Errors in the CPU 922/928/928B (continued)

OB 32 OB 33 OB 34 OB 35
1) 1)
Transfer errors in the case of data blocks (LZF)1) Collision of two timed interrupts (WECK-FE) Error in PID controller processing Interface error
Stop Stop Stop none
On CPU 928B also loading error
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Organization Block
Cause of error
Reaction without OB
Organization Block
Cause of error
Reaction without OB
OBs for Handling Controller Errors in the CPU 948 Call a block that is not loaded (KB) OB 19 Open a data block that is not loaded (KDB) Timeout during direct access (user program) to CP, IP, COR or I/O modules via the S5 bus (QVZ) Timeout while updating the process image or transferring the IPC flags Stop none
OBs for Handling Controller Errors in the CPU 948 (continued) Timeout for distributed peripherals for the address areas: - F 0000H to F EFFFH, F F200H to F FFFFH
OB 29
none
OB 23
none
OB 30
Parity error and QVZ in the user memory (PARE)
Stop
OB 24
none
OB 32
Load/transfer error (TLAF)
Stop
Stop OB 25 Addressing error (ADF) 1) OB 33
Collision of time interrupts: - Queue overflow (WEFES) The time interrupt pulse has been masked for too long (WEFEH)
Stop none
OB 26 OB 27 OB 28
Stop Cycle time exceeded (ZYK) Substitution error (SUF) Timeout in input byte IB 0 (QVZ) Stop Stop
OB 34
Error while generating a data block with G DB or GX DX (FEDBX)
Stop
1)
if not inhibited by IAE
154
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Execution times in s Organization Block CPU 922 = OB not available on this CPU CPU 928 CPU 928B CPU 948 Function
Special Function OBs

OB 110 OB 111 OB 112 OB 113 OB 120 70 - 76 1) 31 - 34 1) 18 - 20 12 14 14 36 - 128 36 - 136 OB 121 58 - 78 47 - 52 1) OB 122 26 OB 123 OB 124 OB 125 OB 126
1)
1.7 1.2 2.0 2.0 68 68
Access to the condition-code byte Reset accumulators Roll up accumulator Roll down accumulator Activate/deactivate "Disable all interrupts" Activate/deactivate "Disable cyclic time interrupts individually" Set/read system time (compatible to CPU 946/947) Activate/deactivate "Delay all interrupts" Activate/deactivate "Disable all interrupts" Ativate/deactivate "Delay cyclic time interrupts individually" 1327 1477 93 Delete STEP 5 blocks Generate STEP 5 blocks Define and transfer process images
37 - 39
73
39 - 54
73
OB only available from version 09
156
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Special Functions OBs (continued)

OB 129 OB 131 OB 132 OB 133 OB 141 OB 142 OB 143 15 1.8 2.2 2.4 47 49 47 Determine battery status Delete Accu 1 to 4 Accu roll up Accu roll down Activate/deactivate "Disable cyclic time interrupts individually" Activate/deactivate "Delay all interrupts" Ativate/deactivate "Delay cyclic time interrupts individually" Set system time Read system time Clock-controlled time interrupt Job type 125 OB 151 max. 267 123 max. 152 max. 284 166 202 1 to 7 0 read 1 to 7 262 0 set Function
265 OB 150 132
266 153
158
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159

Special Function OBs (continued)

OB 152 90 Cycle scan statistic Delay interrupt Function no. OB 153 66 60 70 OB 160 - 163 21 - 23 1) 55 + n * 27.5 1) 11 - 14 34 + n * 15.8 16 40 - 53 1) 24 - 29 1.1 60 + n * 13.3 1.0 3.6 171 + n * 0.65 76 38 170+n 1 2) 170+n 10.5 3) 110 72 80 1 2 3 Repeat loops Read block stack (BSTACK); n = number of BSTACK elements Random data block access Test data blocks (DB/DX) Copy data area; 4) n = number of data words Function Define and start delay time Stop delay time Read current remaining time
OB 170 OB 180 OB 181 OB 182
1) 2) 3)
OB only available from version 09. For copy direction decrementing For copy direction incrementing
4) CPU 948: The copy direction "decrementing" is standard. The direction "incrementing" is only selected if the data areas overlap each other. This includes that the start address of the source area is smaller than the end address of the source area.
160
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1)
47 + n * 0.75
2) 3)
OB 190
48.5 + n * 0.5
25 + n * 0.5 25 + n * 0.3
2) 3)
54 + n * 0.5 55 + n * 0.3
2) 3)
Transfer flag byte by byte into data block; n = number of flag bytes
1)
47 + n * 0.75
2) 3)
OB 191
48 + n * 0.5
1)
25 + n * 0.5 25 + n * 0.3
2) 3)
54 + n * 0.5 55 + n * 0.3
2) 3)
Transfer data field byte by byte into flag area; n = number of flag bytes
OB 192
46 + n * 2.8 2) 46 + n * 2.55
3)
25 + n * 1.8 2) 40 + n * 0.57 3)
51 + n * 1.8 2) 53 + n * 0.57 3)
Transfer flag word by word into a data block; n = number of flag bytes
1)
OB 193
46 + n * 2.8 2) 46 + n * 2.55
3)
25 + n * 1.8 2) 40 + n * 0.57 3)
51 + n * 1.8 2) 53 + n * 0.57 3)
Transfer data field word by word into flag area; n = number of flag bytes
OB 200, 202 - 205 OB 216 OB 217 OB 218

1) 2) 3) 4)
4)
4)
4)
4)
Interprocessor communication in multiprocessor mode Access to page frames Access to page frames Access to page frames
31.8 - 42.5 32.6 - 43.1 26.3
28 - 35 30 - 35 21
58 - 65 60 - 66 54
OB only available from version 09. If number of first flag byte is uneven. If number of first flag byte is even. See manual of relevant CPU.
162
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OB 220 OB 221 OB 222 OB 223 25 44.5 21.5 39 14 36 18 18 0.57 62 48 48 35 13 Convert the contents of ACCU 1 from a 16-bit fixedpoint number to a 32-bit fixed-point number Set and trigger a new scan time monitor Retrigger the scan time monitor Change to stop status in case of non-uniform restart modes in multiprocessor mode Block transfer of the interprocessor communication flags in multiprocessor mode Read the contents of a system program memory location Read the check sum of the system program memory Read status information of a program processing level
2)
OB 224
23
11
41
OB 226
29
19
53
OB 227
31
14
48
OB 228 OB 230 - 237

1)
34.5 1)
2)
21
2)
56
2)
Functions for handling blocks
OB only available from version 09
2)
See Manual "SIMATIC S5 - Standard Function Blocks Handling Blocks CPU 922, CPU 928, CPU 928B S5-135U, S5-155U Programmable Controllers"
164
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OB 240 OB 241 OB 242 OB 250 OB 251 OB 254 120 - 805 42 - 110 12 158 < 730 85 + n * 1 73 + n * 12 28 + n * 12 17 114 425 80 + n * 0.2 105 + n * 12 60 + n * 9 46 144 455 112 + n * 0.7 1472 - 2869 Initialize a shift register; n = number of pointers Call a shift register; n = number of pointers Delete a shift register Initialize a PID controller Call a PID controller Copy a DX data block (extension); n = number of data words to be transferred Copy a DB data block; n = number of data words to be transferred
OB 255
85 + n * 1
80 + n * 0.2
112 + n * 0.7
1472 - 2869
166
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Intentionally blank!
168
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s5-948 Overview

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SIMATIC S5

S5-135U/155U CPU 922/CPU928/CPU 928B/CPU 948

Copyright Siemens AG 1993 All Rights Reserved

Machine Code Listing Alphabetical Index of Operations

116 131 144 146

Explanatory Notes on the Condition Codes List of Organization Blocks

Explanatory Notes on the List of Operations

The high word of the four 32-bit accumulators

The low word of the four 32-bit accumulators

PII/PIQ RLO RLO-dependent command flow?

Explanatory Notes on the Operands

1) CPU 922 from version 09

all all all all all all all all all

all all all all all all

922/ 928/ 110 to 255 928B 948 121 to 255 0 to 254

Permissible Value Range for Operands CPU Range 0 to 255

Flag, additional (S flag)

922 928 928B 948

Sequence block Flag double word, additional (S flag double word)

all 922 928 928B 948

Flag word, additional (S flag word)

922 928 928B 948

Flag byte, additional (S flag byte)

922 928 928B 948

Explanatory Notes on the Formal Operands (Block Parameters)

Data Type Type specification not permitted

Type specification not permitted Type specification not permitted

Boolean Logic Operations

Q 0.0 to 127.7 F 0.0 to 255.7 S 0.0 to 1023.7

A S 0.0 to 4095.7 A A A AN AN D 0.0 to 255.15 T 0 to 255 C 0 to 255 I 0.0 to 127.7

Boolean Logic Operations (continued)

Q 0.0 to 127.7 F 0.0 to 257.7 S 0.0 to 1023.7

O S 0.0 to 4095.7 O D 0.0 to 255.15

Boolean Logic Operations (continued)

Q 0.0 to 127.7 F 0.0 to 255.7 S 0.0 to 1023.7

ON S 0.0 to 4095.7 ON ON ON O D 0.0 to 255.15 T 0 to 255 C 0 to 255 -

Boolean Logic Operations (continued)

Set/Reset Operations, Binary

Q 0.0 to 127.7 F 0.0 to 255.7 S 0.0 to 1023.7

Set/Reset Operations, Binary (continued)

Q 0.0 to 127.7 F 0.0 to 255.7 S 0.0 to 1023.7

Load Operations (continued)

SY 0 to 1023 L SY 0 to 4095 SW 0 to 1022 L SW 0 to 4094 SD 0 to 1020 L SD 0 to 4092 DH 0 to FFFF FFFF DL 0 to 255

Operation possible from version 09 onwards.

Load Operations (continued)

KC 0 to 999 KF -32768 to +32767

KG (see page 4) N KH 0 to FFFF KM bit pattern, 16 bit KS (2 ASCII characters) N

0.0 to 999.3 N 2 bytes N 0 to 255 each

Load a constant (2-byte number) into ACCU 1-L

Load Operations (continued)

0 to 255 0 to 255 0 to 255 0 to 255

0.81 0.81 3.7 3.7

0.30 0.30 0.39 0.39

Transfer Operations (continued)

SW 0 to 1022 T SW 0 to 4094 SD 0 to 1020 T SD 0 to 4092 T T T DL 0 to 255

Transfer Operations (continued)

PW 0 to 126 T PW 128 to 254

Start timer (stored in ACCU 1-L) as ON delay

Start timer (stored in ACCU 1-L) as stored ON delay