S5-135u/155u Cpu 928/cpu 928b/cpu 948
S5-135u/155u Cpu 928/cpu 928b/cpu 948
S5-135u/155u Cpu 928/cpu 928b/cpu 948
S5-135U/155U
CPU 928/CPU 928B/CPU 948
List of Operations
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SIMATIC S5
S5-135U/155U
CPU 928/CPU 928B/CPU 948
List of Operations
Order No.
6ES5 997-3UA23, Release 01
This publication is protected by copyright. Transmission and reproduction of this docu-
ment as well as use and notification of its contents are not permitted without express
authority. This also applies to translation into other languages.
Offenders will be liable for damages. All rights, including rights created by patent grant
or registration of a utility model or design, are reserved.
Technical data subject to alteration.
Copyright © Siemens AG 1996 All Rights Reserved
Supplementary Operations 56
Logic Operations 56
Digital Operations 56
Bit Test Operations 58
Set/Reset Operations 62
Timer and Counter Operations 66
Load and Transfer Operations 70
Conversion Operations 74
Shift and Rotate Operations 76
Jump Operations 78
Other Operations 80
C79000-N8576-C871-01 I
Page
System Operations 86
Load and Transfer Operations 86
Arithmetic Operations 94
Jump Operations 96
Other Operations 96
Set Operations 100
Register to Register Transfer Operations 102
Load, Transfer and Arithmetic Operations
with the Base Address Register 102
Access to local, word-oriented memory 106
Test/set Busy location (global area) 106
Access to global, byte-oriented memory 108
Access to global, word-oriented memory 110
Open page 110
Test/set Busy location (page area) 110
Access to byte-oriented pages 112
Access to word-oriented pages 114
II C79000-N8576-C871-01
Explanatory Notes on
the List of Operations
Abbreviations Explanations
C79000-N8576-C871-01 1
Abbreviations Explanations
RLO reloaded? Y The RLO does not change. The RLO cannot
be combined any further. If a command
which reloads the RLO is followed by a
binary logic operation, the scan result is
reloaded and a new RLO is started.
2 C79000-N8576-C871-01
Explanatory Notes on the
Operands
Permissible Value
Range for Size
Abbr Description Operands in
Bits
CPU Range
948 2 to 255
948 3 to 255
C79000-N8576-C871-01 3
Permissible Value
Range for Size
Abbr Description Operands in
Bits
CPU Range
4 C79000-N8576-C871-01
Permissible Value
Range for Size
Abbr Description Operands in
Bits
CPU Range
C79000-N8576-C871-01 5
Permissible Value
Range for Size
Abbr Description Operands in
Bits
CPU Range
948 0 to 4092
948 0 to 4094
948 0 to 4095
6 C79000-N8576-C871-01
Explanatory Notes on the
Formal Operands
(Block Parameters)
A maximum of 126 different formal operands (nos. 1 to 126) can be
programmed per FB/FX.
KH for a 4 digit
hexadecimal number
KS for a character
(max. 2 alphanum.
characters)
KF for a fixed-point
number from
-32768 to +32767
KG for a floating-point
number from
±0,1701412 . 1039 to
±0,1469368 . 10-38
C79000-N8576-C871-01 7
Parameter Data Type Actual Operands
Type Permitted
FB Function blocks
(permitted without
parameters only)
are called uncon-
ditionally:
JU FB
OB Organization blocks
are called uncon-
ditionally:
JU OB
PB Program blocks
are called uncon-
ditionally :
JU PB
SB Sequence blocks
are called
unconditionally:
JU SB
8 C79000-N8576-C871-01
Intentionally blank!
C79000-N8576-C871-01 9
Basic Operations
Permissible for all blocks
A I 0.0 to 127.7 N N N N N Y N 0.9 0.57 0.18 Scan input for "1" and combine with RLO through
logic AND
A Q 0.0 to 127.7 N N N N N Y N 0.9 0.57 0.18 Scan output for "1" and combine with RLO through
logic AND
A F 0.0 to 255.7 N N N N N Y N 0.9 0.57 0.18 Scan flag for "1" and combine with RLO through
logic AND
A D 0.0 to 255.15 N N N N N Y N 23 3.4 0.77 Scan a bit in the data block (DB/DX) for "1" and
combine with RLO through logic AND
A T 0 to 255 N N N N N Y N 0.9 0.57 0.18 Scan a time for "1" and combine with RLO through
logic AND
A C 0 to 255 N N N N N Y N 0.9 0.57 0.18 Scan a counter for "1" and combine with RLO with
RLO through logic AND
AN I 0.0 to 127.7 N N N N N Y N 0.9 0.57 0.18 Scan input for "0" and combine with RLO through
logic AND
AN Q 0.0 to 127.7 N N N N N Y N 0.9 0.57 0.18 Scan output for "0" and combine with RLO through
logic AND
10 C79000-N8576-C871-01 C79000-N8576-C871-01 11
Basic Operations
Permissible for all blocks
AN F 0.0 to 255.7 N N N N N Y N 0.9 0.57 0.18 Scan flag for "0" and combine with RLO through
logic AND
AN D 0.0 to 255.15 N N N N N Y N 23 3.4 0.77 Scan a bit in the data block (DB/DX) for "0" and
combine with RLO through logic AND
AN T 0 to 255 N N N N N Y N 0.9 0.57 0.18 Scan a time for "0" and combine with RLO through
logic AND
AN C 0 to 255 N N N N N Y N 0.9 0.57 0.18 Scan a counter for "0" and combine with RLO
through logic AND
O I 0.0 to 127.7 N N N N N Y N 0.9 0.57 0.18 Scan input for "1" and combine with RLO through
logic OR
O Q 0.0 to 127.7 N N N N N Y N 0.9 0.57 0.18 Scan output for "1" and combine with RLO through
logic OR
O F 0.0 to 257.7 N N N N N Y N 0.9 0.57 0.18 Scan flag for "1" and combine with RLO through
logic OR
O D 0.0 to 255.15 N N N N N Y N 23 3.4 0.77 Scan a bit in the data block (DB/DX) for "1" and
combine with RLO through logic OR
12 C79000-N8576-C871-01 C79000-N8576-C871-01 13
Basic Operations
Permissible for all blocks
O T 0 to 255 N N N N N Y N 0.9 0.57 0.18 Scan a time for "1" and combine with RLO through
logic OR
O C 0 to 255 N N N N N Y N 0.9 0.57 0.18 Scan a counter for "1" and combine with RLO
through logic OR
ON I 0.0 to 127.7 N N N N N Y N 0.9 0.57 0.18 Scan input for "0" and combine with RLO through
logic OR
ON Q 0.0 to 127.7 N N N N N Y N 0.9 0.57 0.18 Scan output for "0" and combine with RLO through
logic OR
ON F 0.0 to 255.7 N N N N N Y N 0.9 0.57 0.18 Scan flag for "0" and combine with RLO through
logic OR
ON D 0.0 to 255.15 N N N N N Y N 23 3.4 0.77 Scan a bit in the data block (DB/DX) for "0" and
combine with RLO through logic OR
ON T 0 to 255 N N N N N Y N 0.9 0.57 0.18 Scan a time for "0" and combine with RLO through
logic OR
ON C 0 to 255 N N N N N Y N 0.9 0.57 0.18 Scan a counter for "0" and combine with RLO
through logic OR
14 C79000-N8576-C871-01 C79000-N8576-C871-01 15
Basic Operations
Permissible for all blocks
S I 0.0 to 127.7 N N N N Y N Y 1.0 0.63 0.32 The input of the process image is set to "1" if the
RLO is "1"
S Q 0.0 to 127.7 N N N N Y N Y 1.0 0.63 0.32 The output of the process image is set to "1" if the
RLO is "1"
S F 0.0 to 255.7 N N N N Y N Y 1.0 0.63 0.32 The flag is set to "1" if the RLO is "1"
S D 0.0 to 255.15 N N N N Y N Y 23 3.4 0.77 The bit in the data block (DB/DX) is set to "1" if the
RLO is "1"
R I 0.0 to 127.7 N N N N Y N Y 1.0 0.63 0.32 The input of the process image is reset to "0" if the
RLO is "1"
R Q 0.0 to 127.7 N N N N Y N Y 1.0 0.63 0.32 The output of the process image is reset to "0" if
the RLO is "1"
16 C79000-N8576-C871-01 C79000-N8576-C871-01 17
Basic Operations
Permissible for all blocks
R F 0.0 to 127.7 N N N N Y N Y 1.0 0.63 0.32 The flag is reset to "0" if the RLO is "1"
R D 0.0 to 255.15 N N N N Y N Y 23 3.4 0.77 The bit in the data block (DB/DX) is reset to "0" if
the RLO is "1"
= I 0.0 to 127.7 N N N N N N Y 1.0 0.63 0.32 The value of the RLO is assigned to the input in the
process image
= Q 0.0 to 127.7 N N N N N N Y 1.0 0.63 0.32 The value of the RLO is assigned to the output in
the process image
= F 0.0 to 255.7 N N N N N N Y 1.0 0.63 0.32 The value of the RLO is assigned to the flag
= D 0.0 to 255.15 N N N N N N Y 23 3.4 0.77 The value of the RLO is assigned to the bit in the
data block (DB/DX)
18 C79000-N8576-C871-01 C79000-N8576-C871-01 19
Basic Operations
Permissible for all blocks
Load Operations
The original contents of ACCU 1 are passed on to ACCU 2 before
the byte, word or double word addressed is loaded into ACCU 1.
During byte and word operations, the high bits (not loaded) of
ACCU 1 are deleted (bits 8 to 31 for byte operations, bits 16 to 31
for word operations). If you use ACCU 3 and ACCU 4, you must
insert the "ENT" operation from the supplementary operation set
to restore the accumulator contents.
L IB 0 to 127 N N N N N N N 11 0.81 0.18 Load an input byte from the PII into ACCU 1-L
L QB 0 to 127 N N N N N N N 11 0.81 0.18 Load an output byte from the PIQ into ACCU 1-L
20 C79000-N8576-C871-01 C79000-N8576-C871-01 21
Basic Operations
Permissible for all blocks
SY 0 to 1023 N N N N N N N 2.4
L Load an S flag byte into ACCU 1-L
SY 0 to 4095 N N N N N N N 0.39
SW 0 to 1022 N N N N N N N 2.5
Load an S flag word into ACCU 1-L:
L
Byte n → bits 8-15,byte n+1 → bits 0-7
SW 0 to 4094 N N N N N N N 0.59
L DL 0 to 255 N N N N N N N 11 1.7 0.50 Load the left byte of a data word of the current data
block into ACCU 1-L
22 C79000-N8576-C871-01 C79000-N8576-C871-01 23
Basic Operations
Permissible for all blocks
L DR 0 to 255 N N N N N N N 11 1.7 0.50 Load the right byte of a data word of the current
data block into ACCU 1-L
L DW 0 to 255 N N N N N N N 11 1.5 0.50 Load a data word of the current data block into
ACCU 1-L
Load a flag double word into ACCU 1:
L DD 0 to 254 N N N N N N N 12 2.0 0.68
word n → bits 16-31, word n+1 → bits 0-7
L KB 0 to 255 N N N N N N N 5 0.63 0.18 Load a constant (1-byte number) into ACCU 1-L
L KC 0 to 999 N N N N N N N 11 1.2 0.39 Load a constant (count in BCD) into ACCU 1-L
L KG (see page 4) N N N N N N N 11 1.7 0.57 Load a constant (floating point number) into ACCU
1-L
KM bit pattern,
L N N N N N N N 11 1.2 0.39 Load a constant (bit pattern) into ACCU 1-L
16 bit
L KT 0.0 to 999.3 N N N N N N N 11 1.2 0.39 Load a constant time (time in BCD) into ACCU 1-L
KY 2 bytes
L N N N N N N N 11 1.2 0.39 Load a constant (2-byte number) into ACCU 1-L
0 to 255 each
24 C79000-N8576-C871-01 C79000-N8576-C871-01 25
Basic Operations
Permissible for all blocks
L PY 0 to 255 N N N N N N N 131) 1.4 1) 1.7 1) Load a peripheral byte from the digital/analog
inputs into ACCU 1-L
Load a peripheral word from the digital/analog
L PW 0 to 254 N N N N N N N 151) 2.1 1) 2.69 1) inputs into ACCU 1-L:
byte n → bits 8-15, byte n+1 → bits 0-7
L OY 0 to 255 N N N N N N N 131) 1.4 1) 1.7 1) Load a byte of the extended I/O area into
ACCU 1-L
Load a word of the extended I/O area into
L OW 0 to 254 N N N N N N N 151) 2.1 1) 2.7 1) ACCU 1-L:
byte n → bits 8-15, byte n+1 → bits 0-7
L T 0 to 255 N N N N N N N 12 0.81 0.30 Load a time in binary code into ACCU 1-L
L C 0 to 255 N N N N N N N 12 0.81 0.30 Load a count in binary code into ACCU 1-L
1)
Execution time for single processing operation and for
immediate bus access in multiprocessing operations. I/Os
acknowledge within 0.1 µs or proportionally longer
execution time for longer acknowledgement time.
26 C79000-N8576-C871-01 C79000-N8576-C871-01 27
Basic Operations
Permissible for all blocks
Transfer Operations
The contents of ACCU 1 are transferred to the operand specified.
T IB 0 to 127 N N N 0 N N N 11 0.75 0.18 Transfer the contents of ACCU 1-L (bits 0-7) to an
input byte (into the PII)
Transfer the contents of ACCU 1-L (bits 0-7) to an
T IW 0 to 126 N N N 0 N N N 15 0.8 0.41 input word (into PII):
bits 8-15 → byte n, bits 0-7 → byte n+1
Transfer the contents of ACCU 1 to an input double
word (into the PII):
T ID 0 to 124 N N N 0 N N N 16 1.9 0.59
bits 24-31 → byte n, bits 16-23 → byte n+1,
bits 8-15 → byte n+2, bits 0-7 → byte n+3
T QB 0 to 127 N N N 0 N N N 11 0.75 0.18 Transfer the contents of ACCU 1-L (bits 0-7) to an
output byte (into the PIQ)
Transfer the contents of ACCU 1-L (bits 0-7) to an
T QW 0 to 126 N N N 0 N N N 15 0.8 0.41 output word (into the PIQ):
bits 8-15 → byte n, bits 0-7 → byte n+1
Transfer the contents of ACCU 1 to an output
double word (into the PIQ):
T QD 0 to124 N N N 0 N N N 16 1.9 0.59
bits 24-31 → byte n, bits 16-23 → byte n+1,
bits 8-15 → byte n+2, bits 0-7 → byte n+3
T FY 0 to255 N N N 0 N N N 11 0.75 0.18 Transfer the contents of ACCU 1-L to a flag byte
(bits 0-7)
Transfer the contents of ACCU 1-L to a flag word:
T FW 0 to 254 N N N 0 N N N 15 0.8 0.41
bits 8-15 → byte n, bits 0-7 → byte n+1
Transfer the contents of ACCU 1 to a flag double
word:
T FD 0 to 252 N N N 0 N N N 16 1.9 0.59
bits 24-31 → byte n, bits 16-23 → byte n+1,
bits 8-15 → byte n+2, bits 0-7 → byte n+3
28 C79000-N8576-C871-01 C79000-N8576-C871-01 29
Basic Operations
Permissible for all blocks
SY 0 to 1023 N N N 0 N N N 2.3
T Transfer the contents of ACCU 1-L to an S flag
byte (bits 0-7)
SY 0 to 4095 N N N 0 N N N 0.39
T DL 0 to 255 N N N 0 N N N 17 1.5 0.68 Transfer the contents of ACCU 1-L (bits 0-7) to a
data word (left byte) in a DB/DX
T DR 0 to 255 N N N 0 N N N 17 1.4 0.68 Transfer the contents of ACCU 1-L (bits 0-7) to a
data word (right byte) in a DB/DX
T DW 0 to 255 N N N 0 N N N 17 1.4 0.41 Transfer the contents of ACCU 1-L (bits 0-15) to a
data word in a DB/DX
Transfer the contents of ACCU 1 to a data double
T DD 0 to 254 N N N 0 N N N 18 1.9 0.59 word in a DB/DX:
bits 16-31 → word n, bits 0-15 → word n+1
30 C79000-N8576-C871-01 C79000-N8576-C871-01 31
Basic Operations
Permissible for all blocks
PY 128 to 255 N N N 0 N N N 14 1) 1.21) 1.5 1) Transfer the contents of ACCU 1-L (bits 0-7) to a
peripheral byte of the digital or analog outputs.
Transfer the contents of ACCU 1-L (bits 0-15) to a
peripheral word of the digital or analog outputs:
1) 1)
PW 0 to 126 N N N 0 N N N 18 3.2 2.6 1) bits 8-15 → byte n; bits 0-7 → byte n+1
T The PIQ is also corrected.
Transfer the contents of ACCU 1-L (bits 0-15) to a
PW 128 to 254 N N N 0 N N N 18 1) 2.0 1) 2.4 1) peripheral word of the digital or analog outputs:
bits 8-15 → byte n; bits 0-7 → byte n+1
Transfer the contents of ACCU 1-L (bits 0-7) to a
T OY 0 to 255 N N N 0 N N N 14 1) 1.2 1) 1.5 1) byte of the extended periphery of the digital or
analog outputs (no process image).
Transfer the contents of ACCU 1-L to a word of the
1) 1) 1) extended periphery of the digital or analog outputs
T OW 0 to 254 N N N 0 N N N 18 2.0 2.4
(no process image):
bits 8-15 → byte n; bits 0-7 → byte n+1
1)
Execution time for single processing operation and for
immediate bus access in multiprocessing operation. I/Os
acknowledge within 0.1 µs or proportionally longer
execution time for longer acknowledgement time.
32 C79000-N8576-C871-01 C79000-N8576-C871-01 33
Basic Operations
Permissible for all blocks
Timer Operations
SE T 0 to 255 N N N N 5 3.6 0.18 Start timer (stored in ACCU 1-L) as extended pulse
Y↑ N Y
(start timer with one-shot enable)
SS T 0 to 255 N N N N Y↑ N Y 5 3.6 0.18 Start timer (stored in ACCU 1-L) as stored ON delay
SF T 0 to 255 N N N N Y↓ N Y 5 3.6 0.18 Start timer (stored in ACCU 1-L) as OFF delay
34 C79000-N8576-C871-01 C79000-N8576-C871-01 35
Basic Operations
Permissible for all blocks
Counter Operations
S C 0 to 255 N N N N Y↑ N Y 12 3.8 0.18 Set counter with the value stored in ACCU 1-L
(BCD number from 0 to 999)
36 C79000-N8576-C871-01 C79000-N8576-C871-01 37
Basic Operations
Permissible for all blocks
Arithmetic Operations
The result (numerical value) of an arithmetic operation is stored in
ACCU 1. All other accumulator contents change as follows:
For +F, -F, xF, :F: For +G, -G, xG, :G, +D, -D:
ACCU-2-L: = ACCU-3-L ACCU 2: = ACCU 3
ACCU-3-L: = ACCU-4-L ACCU 3: = ACCU 4
ACCU-4-L: = ACCU-4-L ACCU 4: = ACCU 4
38 C79000-N8576-C871-01 C79000-N8576-C871-01 39
Basic Operations
Permissible for all blocks
40 C79000-N8576-C871-01 C79000-N8576-C871-01 41
Basic Operations
Permissible for all blocks
Comparison Operations
The contents of ACCU 2 (operand) are compared with the
contents of ACCU 1 (operand 2). The RLO is set to "1"
if the comparison condition is fulfilled or to "0" if it is not fulfilled.
Whether the contents of ACCU 2 are <, > or = those in ACCU 1,
can be evaluated via CC0 and CC1
(see Explanatory Notes on the Condition Codes).
!=F - Y Y 0 0 N Y N 18 0.8 0.30 Compare two fixed-point numbers for equal to: if
ACCU 2-L = ACCU 1-L, the RLO is "1"
Compare two fixed-point numbers for not equal to:
><F - Y Y 0 0 N Y N 18 0.8 0.30
if ACCU 2-L ≠ ACCU 1-L, the RLO is "1"
>F - Y Y 0 0 N Y N 18 0.8 0.30 Compare two fixed-point numbers for greater than:
if ACCU 2-L > ACCU 1-L, the RLO is "1"
Compare two fixed-point numbers for greater than
>=F - Y Y 0 0 N Y N 18 0.8 0.30
or equal to: if ACCU 2-L ≥ ACCU 1-L, the RLO is "1"
<F - Y Y 0 0 N Y N 18 0.8 0.30 Compare two fixed-point numbers for less than: if
ACCU 2-L < ACCU 1-L, the RLO is "1"
Compare two fixed-point numbers for less than or
<=F - Y Y 0 0 N Y N 18 0.8 0.30
equal to: if ACCU 2-L ≤ ACCU 1-L, the RLO is "1"
42 C79000-N8576-C871-01 C79000-N8576-C871-01 43
Basic Operations
Permissible for all blocks
!=G - Y Y 0 0 N Y N 20 1.9 1.4 Compare two floating-point numbers for equal to: if
ACCU 2 = ACCU 1, the RLO is "1"
Compare two floating-point numbers for not equal
><G - Y Y 0 0 N Y N 20 1.9 1.4
to: if ACCU 2 ≠ ACCU 1, the RLO is "1"
<G - Y Y 0 0 N Y N 20 1.9 1.4 Compare two floating-point numbers for less than:
if ACCU 2 < ACCU 1, the RLO is "1"
<=G - Y Y 0 0 N Y N 20 1.9 1.4 Compare two floating-point numbers for less than
or equal to: if ACCU 2 ≤ ACCU 1, the RLO is "1"
44 C79000-N8576-C871-01 C79000-N8576-C871-01 45
Basic Operations
Permissible for all blocks
!=D - Y Y 0 0 N Y N 15 1.6 0.52 Compare two fixed-point double words for equal to:
if ACCU 2 = ACCU 1, the RLO is "1"
Compare two fixed-point double words for not
><D - Y Y 0 0 N Y N 15 1.6 0.52
equal to: if ACCU 2 ≠ ACCU 1, the RLO is "1"
>D - Y Y 0 0 N Y N 15 1.6 0.52 Compare two fixed-point double words for greater
than: if ACCU 2 > ACCU 1, the RLO is "1"
Compare two fixed-point double words for greater
>=D - Y Y 0 0 N Y N 15 1.6 0.52 than or equal to: if ACCU 2 ≥ ACCU 1, the RLO is
"1"
<D - Y Y 0 0 N Y N 15 1.6 0.52 Compare two fixed-point double words for less
than: if ACCU 2 < ACCU 1, the RLO is "1"
<=D - Y Y 0 0 N Y N 15 1.6 0.52 Compare two fixed-point double words for less than
or equal to: if ACCU 2 ≤ ACCU 1, the RLO is "1"
46 C79000-N8576-C871-01 C79000-N8576-C871-01 47
Basic Operations
Permissible for all blocks
1.5/6.0
JU PB 0 to 255 N N N 0 N N Y 12 3.7 5) Unconditional program block call
1.5/6.0
JU FB 0 to 255 N N N 0 N N Y 12 3.7 5) Unconditional function block call
1.5/6.0
DOU FX 0 to 255 N N N 0 N N Y 13 5.8 5) Unconditional extended function call
1.5/6.0
JU SB 0 to 255 N N N 0 N N Y 12 3.7 5) Unconditional sequence block call
1.5/6.0
JU OB 1 to 39 N N N 0 N N Y 12 3.7 5) Unconditional organization block call
JU OB 40 to 255 1) 1) 1) 1)
N 1)
Y 2) 2) 2) Unconditional call of a special function organization
block of the operating system
2.7/3.7 1.6/6.1
JC PB 0 to 255 N N N 03) Y 1 Y 11/12 4) 4) 5) Conditional program block call (if RLO is "1")
2.7/3.7 1.6/6.1
JC FB 0 to 255 N N N 03) Y 1 Y 12/12 4) 4) 5) Conditional function block call (if RLO is "1")
1) 3)
The condition codes are set or not set according to the The Os bit remains unchanged if RLO = 0 (not for CPU 948).
special function executed (see Programming Guide -
4)
Special Function OBs) Time applies when RLO =0 / RLO = 1.
2) 5)
For execution times see List of Special Functions, page 130ff. Time applies when "interruption at block limits".
48 C79000-N8576-C871-01 C79000-N8576-C871-01 49
Basic Operations
Permissible for all blocks
JC OB 110 to 255 3) 3) 3) 3)
Y 14) Y 5) 5) 5) Conditional call of special function organization
block of the operating system
DB 2 to 255 N N N N N N N 0.91
C Call a data block
DB 3 to 255 N N N N N N N 12 1.9
DX 1 to 255 N N N N N N N
1) 4)
The OS bit remains unchanged if RLO = 0 (not for CPU 948). Only if the RLO = 0 before the OB is called, otherwise the
RLO can be influenced according to the special function
2)
Time applies when RLO = 0 / RLO = 1. executed (see Programming Guide - Special Function OBs).
3) 5)
The condition codes are set or not set according to the For execution times see List of Special Functions, page 156ff.
special function executed (see Programming Guide -
6)
Special Function OBs). Time applies when "interruption at block limits".
50 C79000-N8576-C871-01 C79000-N8576-C871-01 51
Basic Operations
Permissible for all blocks
DB 2 to 255 N N N N N N N 498
G Generate a data block. The number of its data
words must be stored in ACCU 1 (max. 4091 DW)
DB 3 to 255 N N N N N N N 29 28
DX 1 to 255 N N N N N N N
2.9/3.8
BEC - N N N 01) Y 1 Y 5/6 2) 2) 2.1 Block end, conditional (if RLO is "1")
1)
The OS bit remains unchanged if RLO = 0 (not for CPU 948).
2)
Time applies when RLO = 0 / RLO = 1.
52 C79000-N8576-C871-01 C79000-N8576-C871-01 53
Basic Operations
Permissible for all blocks
Null Operations
NOP
- N N N N N N N 0.9 0.57 0.18 No operation (all bits set to 0)
0
NOP
- N N N N N N N 0.9 0.57 0.18 No operation (all bits set to 1)
1
Stop Operation
Direct transition to "STOP" mode
BLD 0 - 255 N N N N N N N 0.9 0.57 0.18 Display construction statement/NOP for the
programmable controller
BLD 130 N N N N N N N 0.9 0.57 0.18 Display construction operation for the programmer:
generate blank line by carriage return
BLD 131 N N N N N N N 0.9 0.57 0.18 Display construction operation for the programmer:
switch over to statement list (STL)
BLD 132 N N N N N N N 0.9 0.57 0.18 Display construction operation for the programmer:
switch over to control system flowchart CSF)
BLD 133 N N N N N N N 0.9 0.57 0.18 Display construction operation for the programmer:
switch over to ladder diagram (LAD)
BLD 255 N N N N N N N 0.9 0.57 0.18 Display construction operation for the programmer:
terminate segment
54 C79000-N8576-C871-01 C79000-N8576-C871-01 55
Supplementary Operations
Permissible only in function blocks
A= Formal operand N N N N N Y N 22 1) 2.4 1) 0.91 1) AND operation: scan a formal operand for "1"
(parameter type: I, Q, T, C; data type: BI)
AN= Formal operand N N N N N Y N 22 1) 2.4 1) 0.91 1) AND operation: scan a formal operand for "0"
(parameter type: I, Q, T, C; data type: BI)
O= Formal operand N N N N N Y N 22 1) 2.4 1) 0.91 1) OR operation: scan a formal operand for "1"
(parameter type: I, Q, T, C; data type: BI)
ON= Formal operand N N N N N Y N 22 1) 2.4 1) 0.91 1) OR operation: scan a formal operand for "0"
(parameter type: I, Q, T, C; data type: BI)
Digital Operations
The result (= "0" or ≠ "0") can be evaluated via CC0 and CC1
(see Explanatory Notes on the Condition Codes)
1)
The execution time of the substituted operation must be added.
56 C79000-N8576-C871-01 C79000-N8576-C871-01 57
Supplementary Operations
Permissible only in function blocks
These operations scan the status of a bit and update it in the RLO.
TB I 0.0 to 127.7 N N N N N Y N 0.48 Scan an input bit for signal status "1"
TB Q 0.0 to 127.7 N N N N N Y N 0.48 Scan an output bit for signal status "1"
TB F 0.0 to 255.7 N N N N N Y N 0.48 Scan a flag bit for signal status "1"
TB T 0.0 to 255.15 N N N N N Y N 0.48 Scan a bit of a timer word for signal status "1"
TB C 0.0 to 255.15 N N N N N Y N 0.48 Scan a bit of a counter word for signal status "1"
TB D 0.0 to 255.15 N N N N N Y N 0.77 Scan a bit of a data word (DB/DX) for signal status
"1"
RI 0.0
TB N N N N N Y N 0.48 Scan a bit in the RI area for signal status "1"
to 255.15
RJ 0.0
TB N N N N N Y N 0.48 Scan a bit in the RJ area for signal status "1"
to 255.15
RS 0.0
TB N N N N N Y N 0.48 Scan a bit in the RS area for signal status "1"
to 255.15
RT 0.0
TB N N N N N Y N 0.48 Scan a bit in the RT area for signal status "1"
to 255.15
58 C79000-N8576-C871-01 C79000-N8576-C871-01 59
Supplementary Operations
Permissible only in function blocks
These operations scan the status of a bit and update it in the RLO.
TBN I 0.0 to 127.7 N N N N N Y N 0.48 Scan an input bit for signal status "0"
TBN Q 0.0 to 127.7 N N N N N Y N 0.48 Scan an output bit for signal status "0"
TBN F 0.0 to 255.7 N N N N N Y N 0.48 Scan a flag bit for signal status "0"
TBN T 0.0 to 255.15 N N N N N Y N 0.48 Scan a bit of a timer word for signal status "0"
TBN C 0.0 to 255.15 N N N N N Y N 0.48 Scan a bit of a counter word for signal status "0"
TBN D 0.0 to 255.15 N N N N N Y N 0.77 Scan a bit of a data word (DB/DX) for signal status
"0"
RI 0.0
TBN N N N N N Y N 0.48 Scan a bit in the RI area for signal status "0"
to 255.15
RJ 0.0
TBN N N N N N Y N 0.48 Scan a bit in the RJ area for signal status "0"
to 255.15
RS 0.0
TBN N N N N N Y N 0.48 Scan a bit in the RS area for signal status "0"
to 255.15
RT 0.0
TBN N N N N N Y N 0.48 Scan a bit in the RT area for signal status "0"
to 255.15
60 C79000-N8576-C871-01 C79000-N8576-C871-01 61
Supplementary Operations
Permissible only in function blocks
Set/Reset Operations
RD= Formal operand N N N N Y N Y 13 1) 1.9 1) 0.64 1) Digital resetting of a formal operand for timers and
counters (parameter type: T, C)
SU I 0.0 to 127.7 N N N N N N Y 0.48 Set an input bit (in the PII) unconditionally
SU Q 0.0 to 127.7 N N N N N N Y 0.48 Set an output bit (in the PIO) unconditionally
1)
The execution time of the substituted operation must be added.
62 C79000-N8576-C871-01 C79000-N8576-C871-01 63
Supplementary Operations
Permissible only in function blocks
RI 0.0
SU N N N N N N Y 0.48 Set a bit in the RI area unconditionally
to 255.15
RJ 0.0
SU N N N N N N Y 0.48 Set a bit in the RJ area unconditionally
to 255.15
RU I 0.0 to 127.7 N N N N N N Y 0.48 Reset an input bit (in the PII) unconditionally
RU Q 0.0 to 127.7 N N N N N N Y 0.48 Reset an output bit (in the PIO) unconditionally
RI 0.0
RU N N N N N N Y 0.48 Reset a bit in the RI area unconditionally
to 255.15
RJ 0.0
RU N N N N N N Y 0.48 Reset a bit in the RJ area unconditionally
to 255.15
64 C79000-N8576-C871-01 C79000-N8576-C871-01 65
Supplementary Operations
Permissible only in function blocks
1)
The RLO is evaluated according to the executed operation.
2)
The execution time of the substituted operation must be added.
66 C79000-N8576-C871-01 C79000-N8576-C871-01 67
Supplementary Operations
Permissible only in function blocks
1)
Time applies when RLO = "0"/RLO = "1".
68 C79000-N8576-C871-01 C79000-N8576-C871-01 69
Supplementary Operations
Permissible only in function blocks
LD= Formal operand N N N N N N N 12 1) 1.9 1) 0.64 1) Load formal operand in BCD into ACCU 1
(parameter type: T, C)
Load the bit pattern of a formal operand into
LW= Formal operand N N N N N N N 11 1.7 0.50 1) ACCU 1
parameter type: D; data type: KF, KH, KM, KY, KS,
KT, KC)
LDW= Formal operand N N N N N N N 12 2.2 0.68 1) The value of the formal operand is loaded into
ACCU 1 (parameter type: D; data type: KG)
The contents of ACCU 1 are transferred to the
T= Formal operand N N N 0 N N N 12 1) 2.1 1) 0.64 1) formal operand
(parameter type: I, Q; data type: BY, D, W)
L RI 0 to 255 N N N N N N N 11 0.62 0.18 Load a word from the interface data range (RI) into
ACCU 1-L
L RJ 0 to 255 N N N N N N N 11 0.62 0.18 Load a word from the extended interface data area
range into ACCU 1-L
L RS 0 to 255 N N N N N N N 11 0.62 0.18 Load a word from the system data area into
ACCU 1-L
L RT 0 to 255 N N N N N N N 11 0.62 0.18 Load a word from the extended system data area
into ACCU 1-L
1)
The execution time of the substituted operation must be added.
70 C79000-N8576-C871-01 C79000-N8576-C871-01 71
Supplementary Operations
Permissible only in function blocks
T RI 0 to 255 N N N 0 N N N 11 0.57 0.18 Transfer the contents of ACCU 1-L to a word in the
interface data area
T RJ 0 to 255 N N N 0 N N N 11 0.57 0.18 Transfer the contents of ACCU 1-L to a word of the
extended interface data area
T RT 0 to 255 N N N 0 N N N 11 0.57 0.18 Transfer the contents of ACCU 1-L to a word of the
extended system data area
72 C79000-N8576-C871-01 C79000-N8576-C871-01 73
Supplementary Operations
Permissible only in function blocks
Conversion Operations
The data in ACCU 1 is converted.
CFW - N N N N N N N 15 0.57 0.18 Form one’s complement of ACCU 1-L (bits 0-15)
CSW - Y Y Y Y N N N 15 0.57 0.18 Form two’s complement of ACCU 1-L (bits 0 - 15).
Result can be evaluated via CC0/CC1 and OV
CSD - Y Y Y Y N N N 18-251) 0.94 0.43 Form two’s complement of ACCU 1-L (bits 0 - 31).
Result can be evaluated via CC0/CC1 and OV
DEF - N N N N N N N 22 1.9 0.30 Convert a 16-bit fixed point from BCD into binary
DUF - N N N Y N N N 24 3.2 0.43 Convert a 16-bit fixed point from binary into BCD
DED - N N N N N N N 31-39 7.7 0.48 Convert a 32-bit fixed point from BCD into binary
DUD - N N N Y N N N 19-391) 9.8 0.62 Convert a 32-bit fixed point from binary into BCD
FDG - N N N N N N N 18-391) 5.2 2.6 Convert a fixed-point number (32 bits) into a
floating-point number
1)
The time is dependent on the date in ACCU 1(non-linear).
74 C79000-N8576-C871-01 C79000-N8576-C871-01 75
Supplementary Operations
Permissible only in function blocks
RLD 0-321) Y 0 0 0 N N N 6-26 2) 2.6 0.48 Rotate ACCU 1 to the left (32 bits wide) from
position 0 to 32
RRD 0-321) Y 0 0 0 N N N 7-26 2) 2.7 0.48 Rotate ACCU 1 to the right (32 bits wide) from
position 0 to 32
1)
With the operand = "0" an NOP operation is executed;
the condition codes are not affected.
2)
The time is dependent on the size of the (non-linear) operand.
76 C79000-N8576-C871-01 C79000-N8576-C871-01 77
Supplementary Operations
Permissible only in function blocks
Jump Operations
The jump operations are executed depending on the RLO
(only operation JC) or CC0/CC1 and the OV and OS bits
(see Evaluation of CC0 and CC1, page 120)
Symbolic address
JU= N N N N N N N 1.3 1.0 0.59 Unconditional jump to a symbolic address
max. 4 characters
Symbolic address 0.9/1.3 0.7/1.0 0.4/0.8 Conditional jump to a symbolic address, executed
JC= N N N N Y 1 Y
max. 4 characters 1) 1) 1) only if RLO = 1; if RLO = "0", it is set to "1"
Symbolic address 11/12 1.1/1.4 0.4/0.8 Jump if result is "0": the jump is only made if
JZ= N N N N N N N
max. 4 characters 1) 1) 1) CC1 = 0 and CC0 = 0
2)
Jump if result ≠ "0": the jump is only made if
Symbolic address 11/12 1.1/1.4 0.4/0.8 CC1 = 0 and CC0 = 1 or
JN= N N N N N N N CC1 = 1 and CC0 = 0 or
max. 4 characters 1) 1) 1)
CC1 = 1 and CC0 = 0
Symbolic address 11/12 1.1/1.4 0.4/0.8 Jump if result > "0": the jump is only made if
JP= N N N N N N N
max. 4 characters 1) 1) 1) CC1 = 1 and CC0 = 0
Symbolic address 11/12 1.1/1.4 0.4/0.8 Jump if result < "0": the jump is only made if
JM= N N N N N N N
max. 4 characters 1) 1) 1) CC1 = 0 and CC0 = 1
Symbolic address 11/12 1.1/1.4 0.4/0.8 Jump on "overflow": the jump is only made if the OV
JO= N N N N N N N
max. 4 characters 1) 1) 1) bit is set.
Symbolic address 11/12 0.9/1.3 0.7/0.9 Jump on "stored overflow": the jump is only made if
JOS= N N N 0 N N N
max. 4 characters 1) 1) 1) the OS bit is set
1) 2)
Jump condition: fulfilled/not fulfilled If CC 1 = "1" and CC 0 ="1", not executed for CPU 948
78 C79000-N8576-C871-01 C79000-N8576-C871-01 79
Supplementary Operations
Permissible only in function blocks
Other Operations
80 C79000-N8576-C871-01 C79000-N8576-C871-01 81
Supplementary Operations
Permissible only in function blocks
1)
New value of := Old value of
ACCU 1 := ACCU 1
ACCU 2 := ACCU 2
ACCU 3 := ACCU 2
ACCU 4 := ACCU 3
The original contents of ACCU 4 are lost.
2)
Semaphore locations on the coordinator module
3)
Add the waiting time for the bus allocation
82 C79000-N8576-C871-01 C79000-N8576-C871-01 83
Supplementary Operations
Permissible only in function blocks
1)
The condition codes are evaluated and changed according to
the operation executed.
2)
The execution time of the substituted operation must
be added.
3)
The following operations are possible:
- A.., AN.., O.., ON.., S.., R..,=..
with the areas I, Q, F and S,
- FR T, R T, SF T, SR T, SP T, SS T, SE T,
FR C, R C, S C, CD C, CU C,
- L.., T..
with the areas P, O, I, Q, F, S, D, RI, RJ, RS and RT,
- L T, L C,
- LC T, LC C,
- JU=, JC=, JZ=, JN=, JP=, JM=, JO=,
- SLW, SRW,
- D, I, SED, SEE,
- C DB, JU.., JC.., G DB, GX DX, CX DX, DOC FX, DOU FX
84 C79000-N8576-C871-01 C79000-N8576-C871-01 85
System Operations
Permissible only in function blocks
Register no. 10-12 0.9-2.1 Load register with the contents of a memory word
LIR N N N N N N N 7-23 2) 2)
0 to 15 addressed by ACCU 1 1)
Register no. 10-12 0.7-1.9 Transfer register contents into the memory word
TIR N N N N N N N 7-23 2) 2)
0 to 15 addressed by ACCU 1 1)
1) 2)
Registers for LIR and TIR (register width = 16 bits) Execution time for single processing operation and for
immediate bus access in multiprocessing operation. l/Os
acknowledge within 0.1µs or proportionally longer
Reg.-No. Register designation execution time for longer acknowledgement time.
3)
Differences in the CPU 948:
0 ACCU 1-H high word ACCU 1
1 ACCU 1-L low word ACCU 1 The operations LIR/TIR operate with 20 bit absolute addresses.
2 ACCU 2-H high word ACCU 2
3 ACCU 2-L low word ACCU 2 Specifying the address in ACCU 1:
5 BSP (only on Block Stack Pointer
CPU 948) ACCU-1-H: Bit no. 15 to 4 = 0
6 DBA Start address of the current data Bit no. 3 to 0 = address bits nos. 19 to 16
block (address of the first DW)
ACCU-1-L: Bit no. 15 to 0 = address bits nos. 15 to 0
86 C79000-N8576-C871-01 C79000-N8576-C871-01 87
System Operations
Permissible only in function blocks
1) 2)
Registers for LDI and TDI (register width = 32 bits) Execution time for single processing operation and for
immediate bus access in multiprocessing operation. l/Os
acknowledge within 0.1µs or proportionally longer
Reg.-No. Register designation execution time for longer acknowledgement time.
3)
Specifying the address in ACCU 1:
A1 ACCU 1
A2 ACCU 2
SA SAC = STEP address counter ACCU-1-H: Bit no. 15 to 4 = 0
BA BA register (block start address, Bit no. 3 to 0 = address bits nos. 19 to 16
bit no. 0 to 19)
BR BR register (block address register, ACCU-1-L: Bit no. 15 to 0 = address bits nos. 15 to 0
bit no. 0 to 19)
88 C79000-N8576-C871-01 C79000-N8576-C871-01 89
System Operations
Permissible only in function blocks
Length of area 66 -
25- Block transfer 0 to 255 bytes3):
TNB N N N 01) N N N 1258 End address of target area in ACCU 1-L
0 to 255 1226
2) End address of source area in ACCU 2-L
Length of area 65 -
25- Block transfer 0 to 255 words3):
TNW N N N 01) N N N 2400 End address of target area in ACCU 1-L
0 to 255 2340
2) End address of source area in ACCU 2-L
1) 3)
With CPU 928/928B the OS bit is not influenced by TNB 0/TNW 0. Block transfer operations function decrementally, i.e., the
number of words/bytes specified is transferred starting with
2)
Execution time for single processing operation and for bus the end address. Source area and target area must be located
access in multiprocessing operation. I/Os acknowledge completely within one of the following memory areas:
within 0.1 µs or proportionally longer execution time for
longer acknowledgement time. Address area Size Memory area
90 C79000-N8576-C871-01 C79000-N8576-C871-01 91
System Operations
Permissible only in function blocks
The block transfer operations of the CPU 948 listed below function
with 20 bit absolute addresses. Only these operations can be
interrupted by timeout (QVZ) and power failure (NAU).
2-250
Length of area
TNW
0 to 255
N N N 0 N N N 1) Block transfer in words in the 16 bit memory area 2)
3-560
1) 2)
Execution time for single processing operation and for Block transfer operations function decrementally, i.e., the
immediate bus access in multiprocessing operation. number of words specified is transferred starting with the end
I/Os acknowledge within 0.1 µs or proportionally longer address. The end address of the target area (20 bit) must be
execution time for longer acknowledgement time. located in ACCU 1, the end address of the source area (20 bit)
must be located in ACCU 2. Both the source and the target
Address area of the CPU 948 area must be completely within a memory area listed in the
table.
0 0000 to E FBFF (16 bit)
For TXB and TXW ACCU 3 must contain the block length
E A000 to E AFFF (8 bit - S flag) (number of words, 0 to 127).
E FC00 to E FFFF (8 bit) A conversion takes place in case of block transfers between
8 and 16 bit memory areas. Two bytes are converted into a
F 0000 to F FFFF (8/16 bit) word and vice versa.
92 C79000-N8576-C871-01 C79000-N8576-C871-01 93
System Operations
Permissible only in function blocks
Arithmetic Operations
1)
For changes to ACCU 2 and ACCU 3 see
Arithmetic Operations, page 38
94 C79000-N8576-C871-01 C79000-N8576-C871-01 95
System Operations
Permissible only in function blocks
Jump Operation
- 32768 to
JUR N N N N N N N 11 1.2 0.68 Any jump within a function block
+ 32767
Other Operations
Execute an operation3) whose operation code is
1) 1) 1) 1) 1) 1) 1)
DI - 12 2) 1.7 2) 1.1 2) stored in a formal operand. The number of the
formal operand must be stored in ACCU 1.
3)
DO RS 60 to 63 1) 1) 1) 1) 1) 1) 1)
12 2)
0.8 2) 0.71 2) Execute an operation whose operation code is
stored in the system data
1) 3)
The codes are evaluated and changed according to the The following operations are possible:
operation executed. - A.., AN.., O.., ON.., S.., R.., =..
with the areas I, Q, F, and S,
2)
The execution time of the operation must be added.
- FR T, R T, SF T, SR T, SP T, SS T, SE T,
FR C, R C, S C, CD C, CU C,
- L.., T..
with the areas P, O, I, Q, F, S, D, RI, RJ, RS and RT,
- L T, L C,
- LC T, LC C,
- SLW, SRW,
- D, I, SED, SEE,
96 C79000-N8576-C871-01 C79000-N8576-C871-01 97
System Operations
Permissible only in function blocks
1)
Add the time for the ISTACK operation (approx. 6.5 µs)
98 C79000-N8576-C871-01 C79000-N8576-C871-01 99
System Operations
Permissible only in function blocks
Set Operations
RS 60.0 to
SU N N N N N N Y 0.48 Set a bit in the RS area unconditionally
63.15
RT 0.0 to
SU N N N N N N Y 0.48 Set a bit in the RT area unconditionally
RT 255.15
RS 60.0 to
RU N N N N N N Y 0.48 Reset a bit in the RS area unconditionally
63.15
RT 0.0 to
RU N N N N N N Y 0.48 Reset a bit in the RT area unconditionally
RT 255.15
Load, Transfer and Arithmetic Operations with the Base Address Register
The base address register (32 bits) allows address arithmetic and
indirect load and transfer operations without using the
accumulators for addressing. The following applies:
Absolute address = contents of base address register + constant
1)
The bits 215 to 231 are set to "0". 2)
The bits 220 to 231of the BR register are set to "0".
.
Load, Transfer and Arithmetic Operations with the Base Address Register
The base address register (20 bits) allows address arithmetic and
indirect load and transfer operations without using the
accumulators for addressing. The following applies:
Absolute address = contents of base address register + constant
1)
The bits 220 to 231 are set to "0".
1) 2)
Possible absolute addresses: Execution time for single processor operation and for
bus access in multiprocessor operation. I/Os acknowledge
CPU 928/928B CPU 948 within 0.1 µs or proportionally longer execution times
for longer acknowledgement time.
0000 to E3FF and
LRW/TRW 0 0000 to E FBFF
E800 to EDFF
1) 2)
Execution time for single processor operation and Possible absolute addresses:
for bus access in multiprocessor operation. I/Os
acknowledge within 0.1µs or proportionally longer CPU 928/928B CPU 948
execution times for longer acknowledgement time.
LY GB/TY GW 0000 to EFFF F 0000 to F FFFF
Open page:
ACR - N N N N N N N 11 1) 0.571) 0.32 1) Open the page whose number is in ACCU 1-L 3).
1) 2)
Execution time for single processor operation and Possible absolute addresses:
for bus access in multiprocessor operation. I/Os
acknowledge within 0.1 µs or proportionally longer CPU 928/928B CPU 948
execution times for longer acknowledgement time.
LW GB/TW GW 0000 to EFFF F 0000 to F FFFF
1) 2)
Execution time for single processor operation and Possible absolute addresses:
for bus access in multiprocessor operation. I/Os
acknowledge within 0.1 µs or proportionally longer CPU 928/928B CPU 948
execution times for longer acknowledgement time.
LY CB/TY CB F400 to FBFF F F400 to F FBFF
1) 2)
Execution time for single processor operation and Possible absolute addresses:
for bus access in multiprocessor operation. l/Os
acknowledge within 0.1µs or proportionally longer CPU 928/928B CPU 948
execution times for longer acknowledgement time.
LW CW/TW CW F400 to FBFF F F400 to F FBFF
Machine Code
Opera- Ope-
B0 B1 B2 B3 tion rand
L R L R L R L R
0 0 0 0 NOP 0
0 1 0 0 CFW
0 2 0d 0d L T
0 3 0l 0l TNB
0 4 0d 0d FR T
0 5 0 0 BEC
0 6 0c 0c FR=
0 7 0c 0c A=
0 8 0 0 IA
0 8 8 0 RA
0 9 0 0 CSW
116 C79000-N8576-C871-01
Machine Code
Opera- Ope-
B0 B1 B2 B3 tion rand
L R L R L R L R
0 A 0d 0d L FY
0 B 0d 0d T FY
0 C 0d 0d LD T
0 D 0i 0i JO=
0 E 0c 0c LD=
0 F 0c 0c O=
1 0 0e 0e BLD
1 0 8 2 BLD 130
1 0 8 3 BLD 131
1 0 8 4 BLD 132
1 0 8 5 BLD 133
1 0 F F BLD 255
1 1 0e 0e I
1 2 0d 0d L FW
1 3 0d 0d T FW
1 4 0d 0d SF T
1 5 0i 0i JP=
1 6 0c 0c SFD=
1 7 0c 0c S=
1 8 0d 0d DO RS
1 9 0e 0e D
1 A 0d 0d L FD
1 B 0d 0d T FD
1 C 0d 0d SE T
1 D 0f 0f JC FB
C79000-N8576-C871-01 117
Machine Code
Opera- Ope-
B0 B1 B2 B3 tion rand
L R L R L R L R
1 E 0c 0c SEC=
1 F 0c 0c ==
2 0 0f 0f C DB
2 1 2 0 >F
2 1 4 0 <F
2 1 6 0 ><F
2 1 8 0 !=F
2 1 A 0 >=F
2 1 C 0 <=F
2 2 0d 0d L DL
2 3 0d 0d T DL
2 4 0d 0d SD T
2 5 0i 0i JM=
2 6 0c 0c SD=
2 7 0c 0c AN=
2 8 0e 0e L KB
2 9 0h 0h SLD
2 A 0d 0d L DR
2 B 0d 0d T DR
2 C 0d 0d SS T
2 D 0i 0i JU=
2 E 0c 0c SSU=
2 F 0c 0c ON=
3 0 0 1 0e 0e 0e 0e L KC
3 0 0 2 0e 0e 0e 0e L KT
118 C79000-N8576-C871-01
Machine Code
Opera- Ope-
B0 B1 B2 B3 tion rand
L R L R L R L R
3 0 0 4 0e 0e 0e 0e L KF
3 0 1 0 0e 0e 0e 0e L KS
3 0 2 0 0e 0e 0e 0e L KY
3 0 4 0 0e 0e 0e 0e L KH
3 0 8 0 0e 0e 0e 0e L KM
3 1 2 0 >G
3 1 4 0 <G
3 1 6 0 ><G
3 1 8 0 !=G
3 1 A 0 >=G
3 1 C 0 <=G
3 2 0d 0d L DW
3 3 0d 0d T DW
3 4 0d 0d SP T
3 5 0i 0i JN=
3 6 0c 0c SP=
3 7 0c 0c RB=
3 8 0 0 0e 0e 0e 0e L KG 1)
3 8 4 0 0e 0e 0e 0e L DH 1)
3 9 2 0 >D
3 9 4 0 <D
3 9 6 0 ><D
3 9 8 0 !=D
3 9 A 0 >=D
1)
3-word command with B4 and B5, filled with 0 e
C79000-N8576-C871-01 119
Machine Code
Opera- Ope-
B0 B1 B2 B3 tion rand
L R L R L R L R
3 9 C 0 <=D
3 A 0d 0d L DD
3 B 0d 0d T DD
3 C 0d 0d R T
3 D 0f 0f JU FB
3 E 0c 0c RD=
3 F 0c 0c LW=
4 0 0 0k LIR
4 1 0 0 AW
4 2 0d 0d L C
4 3 0o 0o TNW
4 4 0d 0d FR C
4 5 0i 0i JZ=
4 6 0c 0c L=
4 7 0d 0d L RJ
4 8 0 0k TIR
4 9 0 0 OW
4 A 0d 0d L IB
4 A 8d 0d L QB
4 B 0d 0d T IB
4 B 8d 0d T QB
4 C 0d 0d LD C
4 D 0f 0f JC OB
4 E 0d 0d DO FW
4 F 0d 0d L RT
120 C79000-N8576-C871-01
Machine Code
Opera- Ope-
B0 B1 B2 B3 tion rand
L R L R L R L R
5 0 0e 0e ADD BN
5 1 0 0 XOW
5 2 0d 0d L IW
5 2 8d 0d L QW
5 3 0d 0d T IW
5 3 8d 0d T QW
5 4 0d 0d CD C
5 5 0f 0f JC PB
5 6 0c 0c LDW=
5 7 0d 0d L OW
5 8 0 0 0e 0e 0e 0e ADD KF
5 9 0 0 -F
5 A 0d 0d L ID
5 A 8d 0d L QD
5 B 0d 0d T ID
5 B 8d 0d T QD
5 C 0d 0d S C
5 D 0f 0f JC SB
5 F 0d 0d L OY
6 0 0 0 :F
6 0 0 3 :G
6 0 0 4 xF
6 0 0 5 0e 0e 0e 0e ADD DH 1)
6 0 0 7 xG
1)
3-word command with B4 und B5, filled with 0 e
C79000-N8576-C871-01 121
Machine Code
Opera- Ope-
B0 B1 B2 B3 tion rand
L R L R L R L R
6 0 0 8 ENT
6 0 0 9 -D
6 0 0 B -G
6 0 0 C 0 0 0i 0i JOS=
6 0 0 D +D
6 0 0 F +G
6 1 0 0h SLW
6 2 0d 0d L RS
6 3 0d 0d T RS
6 4 0h 0h RLD
6 5 0 0 BE
6 5 0 1 BEU
6 6 0c 0c T=
6 7 0d 0d T RJ
6 8 0 0 0e 0e 0e 0e LRW
6 8 0h 1 SSW
6 8 0 2 GFD
6 8 0 3 0e 0e 0e 0e TRW
6 8 0 4 0e 0e 0e 0e LRD
6 8 0 5 0e 0e 0e 0e TRD
6 8 0 6 FDG
6 8 0 7 CSD
6 8 0 8 DUF
6 8 0 A DUD
6 8 0 B LDI A1
122 C79000-N8576-C871-01
Machine Code
Opera- Ope-
B0 B2 B3 B4 tion rand
L R L R L R L R
6 8 0 C DEF
6 8 0 E DED
6 8 0 F TDI A1
6 8 1 9 MAS
6 8 2 9 MAB
6 8 2 B LDI A2
6 8 2 F TDI A2
6 8 4 9 MSA
6 8 4 B LDI SA
6 8 4 F TDI SA
6 8 6 9 MSB
6 8 8 9 MBA
6 8 9 9 MBS
6 8 9 B LDI BA
6 8 9 F TDI BA
6 8 A B LDI BR
6 8 A F TDI BR
6 9 0 0h SRW
6 A 0d 0d L RI
6 B 0d 0d T RI
6 C 0d 0d CU C
6 D 0f 0f JU OB
6 E 0d 0d DO DW
6 F 0d 0d T RT
7 0 0 0 STS
C79000-N8576-C871-01 123
Machine Code
Opera- Ope-
B0 B2 B3 B4 tion rand
L R L R L R L R
7 0 0 2 TAK
7 0 0 3 STP
7 0 0 4 STW
7 0 0 B 0m 0m 0m 0m JUR
7 0 0 C LIM
7 0 0 D SIM
7 0 0 E 0 0b 0g 0g RU RT
7 0 0 E 4 0b 0g 0g SU RT
7 0 0 E 8 0b 0g 0g TBN RT
7 0 0 E C 0b 0g 0g TB RT
7 0 0 F TXW
7 0 1 5 0 0b 0g 0g RU C
7 0 1 5 4 0b 0g 0g SU C
7 0 1 5 8 0b 0g 0g TBN C
7 0 1 5 C 0b 0g 0g TB C
7 0 1 E 0 0b 0g 0g RU RJ
7 0 1 E 4 0b 0g 0g SU RJ
7 0 1 E 8 0b 0g 0g TBN RJ
7 0 1 E C 0b 0g 0g TB RJ
7 0 1 F TXB
7 0 2 5 0 0b 0g 0g RU T
7 0 2 5 4 0b 0g 0g SU T
7 0 2 5 8 0b 0g 0g TBN T
7 0 2 5 C 0b 0g 0g TB T
7 0 3 8 0 0b 0a 0a RU I
124 C79000-N8576-C871-01
Machine Code
Opera- Ope-
B0 B2 B3 B4 tion rand
L R L R L R L R
7 0 3 8 0 0b 8a 0a RU Q
7 0 3 8 4 0b 0a 0a SU I
7 0 3 8 4 0b 8a 0a SU Q
7 0 3 8 8 0b 0a 0a TBN I
7 0 3 8 8 0b 8a 0a TBN Q
7 0 3 8 C 0b 0a 0a TB I
7 0 3 8 C 0b 8a 0a TB Q
7 0 4 6 0 0b 0g 0g RU D
7 0 4 6 4 0b 0g 0g SU D
7 0 4 6 8 0b 0g 0g TBN D
7 0 4 6 C 0b 0g 0g TB D
7 0 4 7 0 0b 0g 0g RU RI
7 0 4 7 4 0b 0g 0g SU RI
7 0 4 7 8 0b 0g 0g TBN RI
7 0 4 7 C 0b 0g 0g TB RI
7 0 4 9 0 0b 0a 0a RU F
7 0 4 9 4 0b 0a 0a SU F
7 0 4 9 8 0b 0a 0a TBN F
7 0 4 9 C 0b 0a 0a TB F
7 0 5 7 0 0b 0g 0g RU RS
7 0 5 7 4 0b 0g 0g SU RS
7 0 5 7 8 0b 0g 0g TBN RS
7 0 5 7 C 0b 0g 0g TB RS
7 1 0h 0h SSD
7 2 0d 0d L PY
C79000-N8576-C871-01 125
Machine Code
Opera- Ope-
B0 B2 B3 B4 tion rand
L R L R L R L R
7 3 0d 0d T PY
7 4 0h 0h RRD
7 5 0f 0f JU PB
7 6 0c 0c DO=
7 7 0d 0d T OW
7 8 0 0 IAE
7 8 0 1 0 1 0f 0c DOU FX
7 8 0 2 0 9 0f 0c DOC FX
7 8 0 3 1 1 0f 0f CX DX
7 8 0 4 0 0 0f 0f GX DX
7 8 0 5 0 0 0f 0f G DB
7 8 0 6 0 0 0n 0n SED
7 8 0 7 0 0 0n 0n SEE
7 8 0e 9 0e 0e 0e 0e MBR
7 8 0 A 0o 0o 0o 0o ABR
7 8 0 B 0b 0a 0a 0a A S
7 8 0 D 0e 0e 0e 0e LYCB
7 8 0 E 0e 0e 0e 0e LYGB
7 8 1 0 RAE
7 8 1 B 0b 0a 0a 0a O S
7 8 1 D 0e 0e 0e 0e LYCW
7 8 1 E 0e 0e 0e 0e LYGW
7 8 2 B 0b 0a 0a 0a S S
7 8 2 D 0e 0e 0e 0e LYCD
7 8 2 E 0e 0e 0e 0e LYGD
126 C79000-N8576-C871-01
Machine Code
Opera- Ope-
B0 B2 B3 B4 tion rand
L R L R L R L R
7 8 3 B 0b 0a 0a 0a = S
7 8 3 D ACR
7 8 3 F 0 0b 0g 0g A D
7 8 3 F 1 0b 0g 0g O D
7 8 3 F 2 0b 0g 0g AN D
7 8 3 F 3 0b 0g 0g ON D
7 8 3 F 4 0b 0g 0g S D
7 8 3 F 5 0b 0g 0g R D
7 8 3 F 6 0b 0g 0g = D
7 8 4 B 0b 0a 0a 0a AN S
7 8 5 B 0b 0a 0a 0a ON S
7 8 5 D 0e 0e 0e 0e LWCW
7 8 5 E 0e 0e 0e 0e LWGW
7 8 6 B 0b 0a 0a 0a R S
7 8 6 D 0e 0e 0e 0e LWCD
7 8 6 E 0e 0e 0e 0e LWGD
7 8 8 D 0e 0e 0e 0e TYCB
7 8 8 E 0e 0e 0e 0e TYGB
7 8 9 D 0e 0e 0e 0e TYCW
7 8 9 E 0e 0e 0e 0e TYGW
7 8 A B 0 0d 0d 0d L SY
7 8 A D 0e 0e 0e 0e TYCD
7 8 A E 0e 0e 0e 0e TYGD
7 8 B B 0 0d 0d 0d T SY
7 8 C B 0 0d 0d 0d L SW
C79000-N8576-C871-01 127
Machine Code
Opera- Ope-
B0 B1 B2 B3 tion rand
L R L R L R L R
7 8 C D 0e 0e 0e 0e TSC
7 8 C E 0e 0e 0e 0e TSG
7 8 D B 0 0d 0d 0d T SW
7 8 D D 0e 0e 0e 0e TWCW
7 8 D E 0e 0e 0e 0e TWGW
7 8 E B 0 0d 0d 0d L SD
7 8 E D 0e 0e 0e 0e TWCD
7 8 E E 0e 0e 0e 0e TWGD
7 8 F B 0 0d 0d 0d T SD
7 9 0 0 +F
7 A 0d 0d L PW
7 B 0d 0d T PW
7 C 0d 0d R C
7 D 0f 0f JU SB
7 E 0 0 DI
7 F 0d 0d T OY
8 0b 0a 0a A F
8 8b 0a 0a O F
9 0b 0a 0a S F
9 8b 0a 0a = F
A 0b 0a 0a AN F
A 8b 0a 0a ON F
B 0b 0a 0a R F
B 8 0d 0d A C
B 9 0d 0d O C
128 C79000-N8576-C871-01
Machine Code
Opera- Ope-
B0 B1 B2 B3 tion rand
L R L R L R L R
B A 0 0 A(
B B 0 0 O(
B C 0d 0d AN C
B D 0d 0d ON C
B E 0 0 BAS
B F 0 0 )
C 0b 0a 0a A I
C 0b 8a 0a A Q
C 8b 0a 0a O I
C 8b 8a 0a O Q
D 0b 0a 0a S I
D 0b 8a 0a S Q
D 8b 0a 0a = I
D 8b 8a 0a = Q
E 0b 0a 0a AN I
E 0b 8a 0a AN Q
E 8b 0a 0a ON I
E 8b 8a 0a ON Q
F 0b 0a 0a R I
F 0b 8a 0a R Q
F 8 0d 0d A T
F 9 0d 0d O T
F A 0i 0i JC=
F B 0 0 O
F C 0d 0d AN T
C79000-N8576-C871-01 129
Machine Code
Opera- Ope-
B0 B1 B2 B3 tion rand
L R L R L R L R
F D 0d 0d ON T
F E 0 0 BAF
F F F F NOP 1
130 C79000-N8576-C871-01
Alphabetical Index
of Operations
(with Machine Code)
A C 10 B 8 0d 0d
D 10 7 8 3 F 0 0b 0g 0g
F 10 8 0b 0a 0a
I 10 C 0b0a 0a
Q 10 C 0b 8a 0a
S 10 7 8 0 B 0b 0a 0a 0a
T 10 F 8 0d 0d
A( --- 16 B A 0 0
A= Formal oper. 56 0 7 0c 0c
ADD BN 94 5 0 0e 0e
DH 94 6 0 0 5 0e 0e 0e 0 e
0 e 0e 0e 0 e
KF 94 5 8 0 0 0e 0e 0e 0 e
AN C 12 B C 0d 0d
D 12 7 8 3 F 4 0 b 0g 0g
F 12 A 0b 0a 0a
C79000-N8576-C871-01 131
Operation Operand Page Machine Code
AN I 10 E 0b 0a 0a
Q 10 E 0b 8a 0a
S 12 7 8 4 B 0b 0a 0a 0a
T 12 F C 0d 0d
AW --- 56 4 1 0 0
BAF --- 80 F E 0 0
BAS --- 80 B E 0 0
BE --- 52 6 5 0 0
BEC --- 52 0 5 0 0
BEU --- 52 6 5 0 1
BLD 0 - 255 54 1 0 0e 0e
130 54 1 0 8 2
131 54 1 0 8 3
132 54 1 0 8 4
133 54 1 0 8 5
255 54 1 0 F F
C DB 50 2 0 0 f 0f
CD C 36 5 4 0d 0d
CFW --- 74 0 1 0 0
CSD --- 74 6 8 0 7
CSW --- 74 0 9 0 0
CU C 36 6 C 0d 0d
CX DX 50 7 8 0 3 1 1 0f 0f
D 0 - 255 82 1 9 0e 0e
DED --- 74 6 8 0 E
DEF --- 74 6 8 0 C
DI --- 96 7 E 0 0
132 C79000-N8576-C871-01
Operation Operand Page Machine Code
DO DW 84 6 E 0d 0d
FW 84 4 E 0d 0d
RS 96 1 8 0d 0d
DO = Formal oper. 84 7 6 0c 0c
DOC FX 50 7 8 0 2 0 9 0f 0f
DOU FX 48 7 8 0 1 0 1 0f 0f
DUD --- 74 6 8 0 A
DUF --- 74 6 8 0 8
ENT --- 82 6 0 0 8
FDG --- 74 6 8 0 6
FR C 68 4 4 0d 0d
T 68 0 4 0d 0d
FR = Formal oper. 66 0 6 0c 0c
G DB 52 7 8 0 5 0 0 0f 0f
GFD --- 74 6 8 0 2
GX DX 52 7 8 0 4 0 0 0f 0f
I 0 - 255 82 1 1 0e 0e
IA --- 80 0 8 0 0
IAE --- 80 7 8 0 0
JC FB 48 1 D 0f 0f
OB 50 4 D 0f 0f
PB 48 5 5 0f 0f
SB 50 5 D 0f 0f
JC = Symb. addr. 78 F A 0i 0i
JM = Symb. addr. 78 2 5 0i 0i
JN = Symb. addr. 78 3 5 0i 0i
JO = Symb. addr. 78 0 D 0i 0i
C79000-N8576-C871-01 133
Operation Operand Page Machine Code
JP = Symb. addr. 78 1 5 0i 0i
JU FB 48 3 D 0f 0f
OB 48 6 D 0f 0f
PB 48 7 5 0f 0 f
SB 48 7 D 0f 0 f
JU = Symb. addr. 78 2 D 0i 0i
JZ = Symb. addr. 78 4 5 0i 0i
L C 26 4 2 0d 0d
DD 24 3 A 0d 0d
DH 22 3 8 4 0 0e 0e 0e 0e
0e 0e 0e 0e
DL 22 2 2 0d 0d
DR 24 2 A 0d 0d
DW 24 3 2 0d 0d
FD 22 1 A 0d 0d
FW 20 1 2 0d 0d
FY 20 0 A 0d 0d
IB 20 4 A 0d 0d
ID 20 5 A 0d 0d
IW 20 5 2 0d 0d
KB 24 2 8 0e 0e
KC 24 3 0 0 1 0e 0e 0e 0e
KF 24 3 0 0 4 0e 0e 0e 0e
KG 24 3 8 0 0 0e 0e 0e 0e
0e 0e 0e 0e
134 C79000-N8576-C871-01
Operation Operand Page Machine Code
L KH 24 3 0 4 0 0e 0e 0e 0e
KM 24 3 0 8 0 0e 0e 0e 0e
KS 24 3 0 1 0 0e 0e 0e 0e
KT 24 3 0 0 2 0e 0e 0 e 0 e
KY 24 3 0 2 0 0e 0e 0e 0e
OW 26 5 7 0d 0d
OY 26 5 F 0d 0d
PW 26 7 A 0d 0d
PY 26 7 2 0d 0d
QB 20 4 A 8d 0d
QD 20 5 A 8d 0d
QW 20 5 2 8d 0d
RI 70 6 A 0d 0d
RJ 70 4 7 0d 0 d
RS 70 6 2 0 d 0d
RT 70 4 F 0d 0d
SD 22 7 8 E B 0 0d 0d 0d
SW 22 7 8 C B 0 0d 0d 0d
SY 22 7 8 A B 0 0d 0d 0d
T 26 0 2 0d 0d
L= Formal oper. 70 4 6 0c 0c
LC C 26 4 C 0d 0d
T 26 0 C 0d 0d
LDI A1 88 6 8 0 B
A2 88 6 8 2 B
BA 88 6 8 9 B
C79000-N8576-C871-01 135
Operation Operand Page Machine Code
LDI BR 88 6 8 A B
SA 88 6 8 4 B
LD = Formal oper. 70 0 E 0c 0c
LIM --- 98 7 0 0 C
LW = Formal oper. 70 3 F 0c 0c
LW CD Constant 114 7 8 6 D 0e 0e 0e 0e
LW CW Constant 114 7 8 5 D 0e 0e 0e 0e
LW GD Constant 110 7 8 6 E 0e 0e 0e 0e
LW GW Constant 110 7 8 5 E 0e 0e 0e 0e
LY CB Constant 112 7 8 0 D 0e 0e 0e 0e
LY CD Constant 112 7 8 2 D 0e 0e 0e 0e
LY CW Constant 112 7 8 1 D 0e 0e 0e 0e
LY GB Constant 108 7 8 0 E 0e 0e 0e 0e
LY GD Constant 108 7 8 2 E 0e 0e 0e 0e
LY GW Constant 108 7 8 1 E 0e 0e 0e 0e
NOP 0 --- 54 0 0 0 0
NOP 1 --- 54 F F F F
136 C79000-N8576-C871-01
Operation Operand Page Machine Code
O C 14 B 9 0d 0d
D 12 7 8 3 F 1 0b 0g 0g
F 12 8 8b 0a 0a
I 12 C 8b 0a 0a
Q 12 C 8b 8a 0a
S 12 7 8 1 B 0b 0a 0a 0a
T 14 F 9 0d 0d
--- 14 F B 0 0
O( --- 16 B B 0 0
O= Formal oper. 56 0 F 0c 0c
ON C 14 B D 0d 0d
D 14 7 8 3 F 3 0b 0g 0g
F 14 A 8b 0a 0a
I 14 E 8b 0a 0a
Q 14 E 8b 8a 0a
S 14 7 8 5 B 0b 0a 0a 0a
T 14 F D 0d 0d
ON = Formal oper. 56 2 F 0c 0c
OW --- 56 4 9 0 0
R C 36 7 C 0d 0d
D 18 7 8 3 F 5 0 b 0g 0g
F 18 B 0b 0a 0a
I 16 F 0b 0a 0a
Q 16 F 0b 8a 0a
S 18 7 8 6 B 0b 0a 0a 0a
T 34 3 C 0d 0d
RA --- 80 0 8 8 0
C79000-N8576-C871-01 137
Operation Operand Page Machine Code
RAE --- 80 7 8 1 0
RB = Formal oper. 62 3 7 0c 0c
RD = Formal oper. 62 3 E 0c 0c
RLD Constant 76 6 4 0h 0h
RRD Constant 76 7 4 0h 0h
RU C 64 7 0 1 5 0 0b 0g 0g
D 64 7 0 4 6 0 0b 0g 0g
F 64 7 0 4 9 0 0b 0g 0g
I 64 7 0 3 8 0 0b 0a 0a
Q 64 7 0 3 8 0 0b 8a 0a
RI 64 7 0 4 7 0 0b 0g 0g
RJ 64 7 0 1 E 0 0b 0g 0g
RS 100 7 0 5 7 0 0b 0g 0g
RT 100 7 0 0 E 0 0b 0g 0g
T 64 7 0 2 5 0 0b 0g 0g
S C 36 5 C 0d 0d
D 16 7 8 3 F 4 0 b 0g 0g
F 16 9 0b 0a 0a
I 16 D 0b 0a 0a
Q 16 D 0b 8a 0a
S 16 7 8 2 B 0b 0a 0a 0a
S= Formal oper. 62 1 7 0c 0c
SD T 34 2 4 0d 0d
SD = Formal oper. 66 2 6 0c 0c
SE T 34 1 C 0d 0d
SED Constant 82 7 8 0 6 0 0 0n 0n
SEE Constant 82 7 8 0 7 0 0 0n 0n
138 C79000-N8576-C871-01
Operation Operand Page Machine Code
SF T 34 1 4 0d 0d
SIM --- 98 7 0 0 D
SLD Constant 76 2 9 0h 0h
SLW Constant 76 6 1 0 0h
SP T 34 3 4 0d 0d
SP = Formal oper. 66 3 6 0c 0c
SRW Constant 76 6 9 0 0h
SS T 34 2 C 0d 0d
SSD Constant 76 7 1 0h 0h
SSW Constant 76 6 8 0h 1
STP --- 54 7 0 0 3
STS --- 98 7 0 0 0
STW --- 98 7 0 0 4
SU C 62 7 0 1 5 4 0b 0g 0g
D 64 7 0 4 6 4 0b 0g 0g
F 62 7 0 4 9 4 0b 0g 0g
I 62 7 0 3 8 4 0b 0a 0a
Q 62 7 0 3 8 4 0b 8a 0a
RI 64 7 0 4 7 4 0b 0g 0g
RJ 64 7 0 1 E 4 0b 0g 0g
RS 100 7 0 5 7 4 0b 0g 0g
RT 100 7 0 0 E 4 0b 0g 0g
T 62 7 0 2 5 4 0b 0g 0g
C79000-N8576-C871-01 139
Operation Operand Page Machine Code
T DD 30 3 B 0d 0d
DL 30 2 3 0d 0d
DR 30 2 B 0d 0d
DW 30 3 3 0d 0d
FD 28 1 B 0d 0d
FW 28 1 3 0d 0d
FY 28 0 B 0d 0d
IB 28 4 B 0d 0d
ID 28 5 B 0d 0d
IW 28 5 3 0d 0d
OW 32 7 7 0d 0d
OY 32 7 F 0d 0d
PW 32 7 B 0d 0d
PY 32 7 3 0d 0d
QB 28 4 B 8d 0d
QD 28 5 B 8d 0d
QW 28 5 3 8d 0d
RI 72 6 B 0d 0d
RJ 72 6 7 0d 0d
RS 72 6 3 0d 0d
RT 72 6 F 0d 0d
SD 30 7 8 F B 0 0d 0d 0d
SW 30 7 8 D B 0 0 d 0 d 0d
SY 30 7 8 B B 0 0 d 0d 0d
T= Formal oper. 70 6 6 0c 0 c
TB C 58 7 0 1 5 C 0b 0g 0g
D 58 7 0 4 6 C 0b 0g 0g
140 C79000-N8576-C871-01
Operation Operand Page Machine Code
TB F 58 7 0 4 9 C 0b 0a 0a
I 58 7 0 3 8 C 0b 0a 0a
Q 58 7 0 3 8 C 0b 8a 0a
RI 58 7 0 4 7 C 0b 0g 0g
RJ 58 7 0 1 E C 0b 0g 0g
RS 58 7 0 5 7 C 0b 0g 0g
RT 58 7 0 0 E C 0b 0g 0g
T 58 7 0 2 5 C 0b 0g 0g
TBN C 60 7 0 1 5 8 0b 0g 0g
D 60 7 0 4 6 8 0b 0g 0g
F 60 7 0 4 9 8 0b 0a 0a
I 60 7 0 3 8 8 0b 0a 0a
Q 60 7 0 3 8 8 0b 8a 0a
RI 60 7 0 4 7 8 0b 0g 0g
RJ 60 7 0 1 E 8 0b 0g 0g
RS 60 7 0 5 7 8 0b 0g 0g
RT 60 7 0 0 E 8 0b 0g 0g
T 60 7 0 2 5 8 0b 0g 0g
TAK --- 96 7 0 0 2
TDI A1 88 6 8 0 F
A2 88 6 8 2 F
BA 88 6 8 9 F
BR 88 6 8 A F
SA 88 6 8 4 F
TNB Constant 90 0 3 0l 0l
TNW Constant 90 4 3 0o 0o
C79000-N8576-C871-01 141
Operation Operand Page Machine Code
TXB --- 92 7 0 1 F
TXW --- 92 7 0 0 F
XOW --- 56 5 1 0 0
) 16 B F 0 0
= D 18 7 8 3 F 6 0b 0g 0g
F 18 9 8b 0a 0a
I 18 D 8b 0a 0a
Q 18 D 8b 8a 0a
S 18 7 8 3 B 0b 0a 0a 0a
== Formal oper. 62 1 F 0c 0c
>D --- 46 3 9 2 0
<D --- 46 3 9 4 0
><D --- 46 3 9 6 0
!=D --- 46 3 9 8 0
142 C79000-N8576-C871-01
Operation Operand Page Machine Code
>=D --- 46 3 9 A 0
<=D --- 46 3 9 C 0
+D --- 94 6 0 0 D
-D --- 94 6 0 0 9
:F --- 38 6 0 0 0
xF --- 38 6 0 0 4
+F --- 38 7 9 0 0
-F --- 38 5 9 0 0
!=F --- 42 2 1 8 0
>F --- 42 2 1 2 0
<F --- 42 2 1 4 0
><F --- 42 2 1 6 0
>=F --- 42 2 1 A 0
<=F --- 42 2 1 C 0
>G --- 44 3 1 2 0
<G --- 44 3 1 4 0
><G --- 44 3 1 6 0
!= G --- 44 3 1 8 0
>=G --- 44 3 1 A 0
<=G --- 44 3 1 C 0
:G --- 40 6 0 0 3
xG --- 40 6 0 0 7
+G --- 40 6 0 0 F
-G --- 40 6 0 0 B
C79000-N8576-C871-01 143
Explanatory Notes on
the Condition Codes
C C1 CC0 OV OS OR STA RL O E RA B
Bit 7 6 5 4 3 2 1 0
Abbreviations Description
144 C79000-N8576-C871-01
Evaluation of CC0 and CC1
Jump
C C Arith- Digital Com- Shift For Opera-
C C metic Logic parison Opera- SED, tions
1 0 Opera- Opera- Opera- tions SEE Exe-
tions tions tions cuted
1)
not executed with CPU 948
C79000-N8576-C871-01 145
List of Organization
Blocks
3)
OB 2 Interrupt-driven program processing
3)
OB 3 to OB 8 Interrupt-driven program processing
3)
OB 6 Delay interrupt
3)
OB 9 Time-driven program processing
OB 10 10 ms 10 ms 0.1 s 2) 3)
OB 11 20 ms 20 ms 0.2 s 2) 3)
OB 12 50 ms 50 ms 0.5 s 2) 3)
OB 16 1s 1s 10.0 s 2) 3)
OB 17 2s 2s 20.0 s 2) 3)
OB 18 5s 5s 50.0 s 2) 3)
1) 3)
alternative FB 0 Details about the functions of these OBs of the CPU 948 can
be found in the "CPU 948 Programming Guide".
2)
Default setting, can be changed via DX 0
1)
The setting of the cycle monitoring time via OB 31 has
a higher priority than the setting via DX 0 (CPU 948).
1)
Switchover to the STOP state always occurs independently of
whether OB 28 is programmed and how it is programmed.
1)
On CPU 928B also loading error
OBs for Handling Controller Errors OBs for Handling Controller Errors
in the CPU 948 in the CPU 948 (continued)
Call a block that is not loaded Timeout for distributed peripherals for
(KB) none the address areas:
OB 19 OB 29 - F 0000H to F EFFFH, none
Open a data block that is not F F200H to F FFFFH
loaded (KDB) Stop
1)
if not inhibited by IAE
Execution times in µs
Organization
Function
Block = OB not available on this CPU
Execution times in µs
Organization
Function
Block = OB not available on this CPU
8.5 *D
OB 134
OB 135 11 /D
11 MOD
OB 136
2.5 PUSH
OB 139
Execution times in µs
Organization
Function
Block = OB not available on this CPU
Delay interrupt
Execution times in µs
Organization
Function
Block = OB not available on this CPU
24 + n * 0.4 1) 20 + n * 0.4 1) Transfer data field byte by byte into flag area;
OB 191
24 + n * 0.2 2) 20 + n * 0.2 2) n = number of flag bytes
25 + n * 1.8 1) 51 + n * 1.8 1) Transfer data field word by word into flag area;
OB 193
40 + n * 0.8 2) 53 + n * 0.8 2) n = number of flag bytes
533 (200 basic load + 10.5/word); 542 (220 + Interprocessor communication in multiprocessor,
OB 202 send
(92 for warning) 19/W); 110
528 (195 basic load + 10.5/word); 506 (218 + Interprocessor communication, receive
OB 204
(79 for warning) 18/W); 132
Execution times in µs
Organization
Function
Block = OB not available on this CPU
1)
See Manual "SIMATIC S5 - Standard Function Blocks
Handling Blocks CPU 928, CPU 928B
S5-135U, S5-155U Programmable Controllers"
Execution times in µs
Organization
Function
Block = OB not available on this CPU
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