80 Microprocessing & Interfacing

MICROPROCESSING & INTERFACING

Dec - 2016
Paper Code:-EE-309-F

Note : Attempt five questions in all, selecting one question from each Section.
Question No. 1 is compulsory. All questions carry equal marks.

Q.1.(a) Write a program of find 1’s complement of the number. (5)

Ans. Statement : Find the 1’s complement of the number stored at memory location
2200H and store the complemented number at memory location 2300H.
Sample Problem :
(2200H) = 55H
Result = (2300H) = A AH
Program
LDA 2200H  Get the number
CMA  Complement number
STA 2300H  Store the result
HLT  Terminate program execution.

Flowchart
Start

Get the number

Complement the number

Store the result

End

Q.1.(b) What are NOP and HLT instructions ? (5)

Ans. NOP instruction :
Mnemonic NOP Flags : It does not affect any flag.
NOP : No operation
Algorithm Do nothing
Addr. Mode Implied addressing mode
Operation The execution of this instruction causes the CPU to do nothing.
(i) This instruction causes the CPU to do nothing.This instruction
uses three clock cycles and increments the instruction pointer to
point to the next instruction.
(ii) It can be used to increase the delay of a delay loop.
B.Tech., 5th Semester, Solved papers, Dec -2016 81

Example :
MOV AL, 00011011b
NOT AL ; AL = 11100100b
RET
Flags : all unchanged.
HLT (Halt until interrupt or reset) Instruction :
Mnemonic Halt processing Flags : No flags are affected..
Operation (i) The HLT instruction will cause the 8086 to stop fetching and
executing instructions. The 8086 enters into a half state. To
come out of the halt state, there are 3 ways given below.
(a) Interrupt signal on INTR pin, (b) Interrupt signal on NMI pin
(c) Reset signal on reset pin.
(ii) It may be used as an alternative to an endless software loop in
situations where a program must wait for an interrupt.
Q.1.(c) What is programmable interval timer ? (5)
Ans. There are two types of programmable interval timer are generally used. Intel 8253
is a programmable Interval Timer/Counter which can generate accurate time delays and
waveforms ranging from 0 Hz to 2 MHz using software control. 8254 is its upgraded version
which can operate with higher clock frequency range (DC – 8 MHz) and it is pin to pin compatible
with 8253.
Q.1.(d) Explain direct memory access. (5)
Ans. Direct memory access (DMA) is a feature of modern computers that allows
certain hardware subsystems within the computer to access system memory independently of
the central processing unit (CPU).
Without DMA, when the CPU is using programmed input/output, it is typically fully
occupied for the entire duration of the read or write operation, and is thus unavailable to perform
other work. With DMA, the CPU initiates the transfer, does other operations while the transfer
is in progress, and receives an interrupt from the DMA controller when the operation is done.
This feature is useful any time the CPU cannot keep up with the rate of data transfer, or where
the CPU needs to perform useful work while waiting for a relatively slow I/O data transfer.
Many hardware systems use DMA, including disk drive controllers, graphics cards, network
cards and sound cards. DMA is also used for intra-chip data transfer in multi-core processors.
Computers that have DMA channels can transfer data to and from devices with much less CPU
overhead than computers without a DMA channel. Similarly, a processing element inside a multi-
core processor can transfer data to and from its local memory without occupying its processor
time, allowing computation and data transfer to proceed in parallel.

SECTION – A
Q.2.(a) Define interrupts ? Explain 8085 interrupts. (10)
Ans. Interrupts : The interrupt driven I/O is one of the data transfer techniques used
in the microprocessor systems. By using this techniques, the external device or a peripheral can
inform the processor that it is ready for communication.
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8085 microprocessor provides hardware and software interrupts.

Hardware Interrupts : 8085 microprocessor provides five hardware interrupt viz.
TRAP, RST 7.5, RST 6.5, RST5.5 and INTR. The interrupt structure is a five level structure.
(i) TRAP : It is non-maskable edge and level triggered interrupt, request input line. It is
used for emergency purpose like power failure, parity error checker, smoke detector etc. The
microprocessor does not execute any interrupt acknowledge cycle to read interrupt information
from the interrupting device. The interrupt information is provided by control section of
microprocessor internally. But microprocessor executes ideal machine cycle to acknowledge
this interrupt. To generate starting address of TRAP interrupt service routine. The TRAP signal
must make low to high transition and remain high until acknowledged that means this interrupt is
triggered only at the rising edge of the signal. The avoids false trigerring due to noise or glitches.
It is not affected by any instruction. It has the highest priority among all interrupt. It is always
enabled. This interrupt transfers microprocessors control to location 0024 H. User cannot rest
TRAP flip-flops that means we cannot cancel this interrupt.
(ii) RST 7.5 : It is maskable edge triggered interrupt request input line. The microprocessor
does not execute any interrupt acknowledge cycle to read interrupt information from the interrupting
device. The interrupt information is provided by control selection of microprocessor internally.
Instead of interrupt acknowledge cycle, the microprocessor executes ideal machine cycle (6T)
to acknowledge this interrupt. During this cycle it executes RST 7.5. Instruction to generate
starting address of interrupt service routine. This interrupt is triggered at the rising edge of the
signal. It priority among all maskable interrupt. This interrupt to location 003CH. User can reset
R 7.5 flip-flop that means we can cancel this interrupt by SIM instruction.
(iii) RST 6.5 and RST 5.5 : These are level triggered maskable interrupt request input
lines. The microprocessor does not execute any interrupt acknowledge cycle to read interrupt
information from the interrupting device. The microprocessor executes idle machine cycle (6T)
to acknowledge these interrupts. Durring this cycle it executes RST 6.5 and RST 5.5 instructions
to generate address of ISR 6.5 and ISR 5.5 respectively. They can be disabled by executing SIM
or EI instruction. RST 6.5 transfers microprocessor’s control to location 0034 H while RST 5.5
transfers microprocessor’s control to location 002 CH.
(iv) INTR : It is level triggered, maskable interrupt request input line. The microprocessor
executes interrupt acknowledge cycle to read interrupt information from interrupting device.
The microprocessor executes one interrupt acknowledge cycle (6T) and three interrupt
acknowledge cycles (6T + 3T + 3T) for RST N and CALL instructions respectively.
The starting address of ISR depends upon interrupt information. This interrupt is not
affected by SIM instruction. It is enabled by executing EI instruction while disabled by DI
instruction.
Software interrupts : (i) In case of software interrupts the cause of the interrupt is the
execution of the instruction.
(ii) The microprocessor 8085 has eight instructions. These eight instructions are RST 0
to RST 7. Such interrupts are called as software interrupts.
(iii) They allow the microprocessor to transfer program control from the main program
to the subroutine program (i.e. predefined service routine addresses).
(iv) After completing the subroutine program, the program control returns back to the
main program.
B.Tech., 5th Semester, Solved papers, Dec -2016 83

Q.2.(b) Describe various arithmetic instructions with examples in 8085. (10)

Ans. The arithmetic group of instructions include following instructions :
(i) ADD R (ii) ADD M (iii) ADC R (iv) ADC M
(v) ADI data (vi) ACI data (vii) DAD RP (viii) SUB R
(ix) SUB M (x) SBB R (xi) SBB M (xii) SUI data
(xiii) SBI data (xiv) INR R (xv) INR M (xvi) DCR R
(xvii) DCR M (xviii) INX RP (xix) DCX RP (xx) DAA
Some of the describe as follows :
ADD R :
Description : Add register R contents to accumulator.
This instruction adds the contents of register R and accumulator and
stores the result in accumulator. The example of R are all general purpose
registers such as A, B, C, D, E, H and L. In addition to the result in
accumulator all the flags are modified to reflect the result of operation.
Operation : A+ R A
Example : ADD : A + B  A.
Suppose A = 40 H and B = 65 H.
A 0100 0000
+B 0110 0101
A 1010 0101 = A5
ADC R :
Description : Add register R cut carry flag contents to accumulator.
This instruction adds the contents of Register R, Carry flag Cy and
accumulator and stores the result in accumulator. The example of R are
all general purpose registers such as A, B, C, D, E, H and L. In addition
to the result in accumulator all the flags are modified to reflect the result
of operation.
Operation : A + R  Cy  A
Example : ADC : A + B + Cy  A.
Suppose B = 20, A = 3 F and Cy = Set and ADC B instruction is executed.
A = 0011 1111
B = 0011 0000
Cy = 1
A = 0110 0000
ADI data :
Description : Add immediate data to accumulator.
This instruction adds the 8 bits of data specified along with the instruction
to accumulator and result is stored in accumulator. All flags are also
modified to reflect the result of operation. The storing format of this
instruction will be 1st byte opcode and 2nd byte operand (data).
Operation : A + data  A
Example : ADI B7 H : Add B7 H data to accumulator and store result in accum-
-ulator.
84 Microprocessing & Interfacing

Suppose A = 59 H and instruction ADI B7 is executed.

A = 0101 1001
M = 1011 0111
1 0110 0000
DAD RP :
Description : Add the specified register pair to HL pair.
This instruction adds the contents of specified register pair to HL pair
and stores the result in HL pair. The example of Rp are SP, BC, DE
and HL. Only carry flag is modified to reflect the result of operation.
Operation : RP + HL  HL
Example : (i)DAD B : BC + HL  HL
(ii)DAD SP : SP + HL  HL
DAD B
Suppose B = 20, C = 35, H = 80, L = 45, is executed.
The result of instruction will be
2035 BC
+ 8045 HL
A0 7A HL
SUB M :
Description : Subtract memory location contents from accumulator.
This instruction subtracts memory location contents (whose address is
given by HL) from accumulator and result is placed in accumulator.
The subtraction is performed in the sameways SUB R instruction. All
flags are modified to reflect the result of operation.
Operation : A – (HL)  A
Example : SUB M : A – (HL)  A.
Suppose A = 50H, H = C2, L = 00, at memory location C200 : 20 H is
stored and instruction SUB M is excuted.
(C200) = 0 0 1 0 0000
2’s com = 1 1 1 0 0000
A = 0101 0000
2’s comp. = 1 1 1 0 0000
[1] 0 0 1 1 0000
SUI data :
Description : Subtract immediate data from accumulator.
This instruction subtracts the data specified along with instruction from
accumulator. The subtraction is performed by using 2’s complement
method and operation is same as SUB R instruction.
Operation : A – data  A
Example : SUI 50 : A – 50  A.
Suppose A = 20 and instruction SUI 50 is executed.
INR M :
Description : Increment memory contents by one.
B.Tech., 5th Semester, Solved papers, Dec -2016 85

This instruction increments the contents of memory location address by

HL register pair by 1 and result is stored back at same memory location.
Only carry flag is not modified, all other flags are modified.
Operation : (HL) + 1  (HL) or M + 1  M
Example : INR M : (HL) + 1  (HL).
Suppose H = C2, L = 02, at memory location C202 : 04 is stored, flag
reg = 10 × 1 × 0 × 1 and and instruction INR M is executed.

Q.3.(a) Explain pin diagram of 8085 microprocessor. (10)

Ans. Fig. shows functional pin diagram of 8085 microprocessor. The signals of 8085
can be classified into seven groups according to their functions :
(i) Power supply and frequency signals. (v) Serial I/O signals
(ii) Data bus and address bus (vi) DMA signals
(iii) Control bus (vii) Reset signals
(iv) Interrupt signals

RESET

RST
RST
RST

Fig. : Pin diagram of 8085 microprocessor

86 Microprocessing & Interfacing

(i) Power Supply and Frequency Signals :

(a) VCC : It requires a single +5V power supply.
(b) VSS : Ground reference
(c) X1 and X2 : A tuned circuit like LC, RC or crystal is connected at these two pins. The
internal clock generator divides oscillator frequency by 2, therefore, to operate a system at
3 MHz, the crystal of tuned circuit must have a frequency of 6 MHz.
(d) CLK OUT : This signal is used as a system clock for other devices. Its frequency is
half of the oscillator frequency.
(ii) Data bus and address bus :
(a) AD0 to AD7 : The 8 bit data bus (D0 - D7) is multiplexed with the lower half (A0 - A7)
of the 16 bit address bus. During first part of the machine cycle (T1), lower 8 bits of memory
address or I/O address appear on the bus. During remaining part of the machine cycle (T2 and
T3) these lines are used as a bi-directional data bus.
(b) A8 to A15 : The upper half of the 16 bit address appears on the address lines A8 to A15.
These lines are exclusively used for the most significant 8 bits of the 16 bit address.
(iii) Control and status signals :
(a) ALE (Address Latch Enable) : We know that AD0 to AD7 lines are multiplexed and
the lower half of the address is also necessary during T2 and T3 of machine cycle to access
specific location in memory or I/O port. This means that the lower half of an address must be
latched in T1 of the machine cycle, so that it is available throughout the machine cycle. The
latching of lower half of an address is done by external latch and ALE signal from 8085.
(b) RD and WR : These signals are basically used to control the direction of the direction
of the data flow between processor and memory or I/O device/port. A low on RD indicates that
the data must be read from the selected memory location or I/O port via data bus. A low on WR
indicates that the data must be written into the selected memory location or I/O port via data bus.
(c) IO/ M , S0 and S1 : IO/ M indicates whether I/O operation or memory operation is
being carried out. S1 and S0 indicate the type of machine cycle in progress.
(d) Ready : It is used by the microprocessor to sense whether a peripheral is ready or
not for data transfer. If not, the processor waits. It is thus used to synchronize slower peripherals
to the microprocessor. If peripherals are fast enough it is tied to VCC. If it is left open, 8085 enters
in the wait state.
(iv) Interrupt signals : The 8085 has five hardware interrupt signals : RST 5.5, RST
6.5, RST 7.5, TRAP and INTR. The microprocessor recognizes interrupt requests on these lines
at the end of the current instruction execution.
The INTA (Interrupt Acknowledge) signal is used to indicate that the processor has
acknowledged an INTR interrupt.
(v) Serial I/O signals :
(a) SID (Serial I/P data) : This input serial is used to accept serial data bit by bit from the
external device.
(b) SOD (Serial O/P Data) : This is an output signal which enables the transmission of
serial data bit by bit to the external device.
(vi) DMA Signals :
(a) HOLD : This signal indicates that another master is requesting for the use of address
bus, data bus and control bus.
B.Tech., 5th Semester, Solved papers, Dec -2016 87

(b) HLDA : This active high signal is used to acknowledge HOLD request.
(vii) Reset signal :
(a) RESET IN : A low on this pin
– Sets the program counter to zero (0000H).
– Resets the interrupt enable and HLDA flip-flops. Before entering any interrupts
service routine we may have to initialize certain passing parameters. Thus it is not desired to
activate interrupts at the RESET time.
– Tri-states the data bus, addres bus and control bus.
– Affects the contents of processor’s internal registers randomly.
On reset, the PC sets to 0000H which causes the 8085 to execute the first instruction
from address 0000H. For proper reset operation reset signal must be held low for at least 3 clock
cycles. The power-on reset circuit can be used to ensure execution of first instruction from
address 0000H.
(b) RESET OUT : This active high signal indicates that processor is being reset. This
signal is synchronized to the processor clock and it can be used to reset other devices connected
in the system.

Q.3.(b) What is the functioning of timing and control unit in 8085

microprocessor? Discuss all its signals in details. (10)
Ans. Timing and Control : This is a control section of 8085 made up of synchronous
sequential logic circuit. It controls all internal and external circuits in the microprocessor system.
It operates with reference to clock signal. It accepts information from instruction decoder and
generates microsteps to perform it. In addition to this, the block accepts clock inputs, performs
sequencing and synchronising operations. The synchronization is required for communication
between microprocessor and peripheral devices. Fig. shows the control section of microprocessor.
The contents of the instruction register are in the form of 0’s and 1’s. They are converted
to meaningful form by the decoding network called matrices. The control matrix provides internal
signals for controlling operation and data between registers. The control unit also generates
timing signals essential for microprocessor to operate. The microprocessor uses a quartz crystal
(LC or RC circuit) to determine the clock frequency, so that other timing and control signals are
developed. The speed of microprocessor is directly proportional to the speed of the crystal. The
clock speed and access time must be compatible for maximum performance. To implement this
it uses different status and control signals.
Control and status signals :
(a) ALE (Address Latch Enable) : We know that AD0 to AD7 lines are multiplexed and
the lower half of the address is also necessary during T2 and T3 of machine cycle to access
specific location in memory or I/O port. This means that the lower half of an address must be
latched in T1 of the machine cycle, so that it is available throughout the machine cycle. The
latching of lower half of an address is done by external latch and ALE signal from 8085.
(b) RD and WR : These signals are basically used to control the direction of the data
flow between processor and memory or I/O device/port. A low on RD indicates that the data
must be read from the selected memory location or I/O port via data bus. A low on WR indicates
that the data must be written into the selected memory location or I/O port via data bus.
88 Microprocessing & Interfacing

Fig. : Control section of microprocessor

(c) IO/ M , S0 and S1 : IO/ M indicates whether I/O operation or memory operation is
being carried out. S1 and S0 indicate the type of machine cycle in progress.
(d) Ready : It is used by the microprocessor to sense whether a peripheral is ready or
not for data transfer. If not, the processor waits. It is thus used to synchronize slower peripherals
to the microprocessor. If peripherals are fast enough it is tied to VCC. If it is left open, 8085 enters
in the wait state.
SECTION – B

Q.4.(a) Explain BIU and EU of 8086 microprocessor. (15)

Ans. BUS Interface Unit (BIU) : The BIU interface 8086 to the outside word. It
provides a full 16 bit bidirectional data bus and 20bit address bus. The BIU is responsible for
performing all external bus operations as given below :
(i) It sends address of the memory or I/O.
(ii) It fetches instruction from memory.
(iii) It reads data from port/memory.
(iv) It writes data into port/memory.
(v) It supports instruction queuing.
(vi) It provides the address location facility.
The BIU has a dedicated order. The main function of this order is to produce 20 bit
physical address. The bus control logic of the BIU generates all bus control signals such as
READ and WRITE for memory and I/O.
Instruction Queue : To speed up program execution, the BIU fetches six instruction
bytes ahead of time from memory. These prefetched instruction bytes are held for the execution
unit in a group of registers called queue. With the help of queue it is possible to fetch next
instruction while current instruction is in execution. There are number of instructions in 8086
which need a quite large number of clock cycles for execution. During this execution time the
BIU fetches the next instruction or instructions from memory into the instruction queue instead
of remaining idle. The BIU continues this process as long as the queue is not full. Due to this,
B.Tech., 5th Semester, Solved papers, Dec -2016 89

execution unit gets, the ready instruction in the queue and instruction fetch time is eliminated
(while decoding or executing an instruction EU does not require use of the
buses).
This system has the advantage over the 8085 because, while the EU is executing an
instruction, the BIU is fetching and storing in the queue the next instructions.
The BIU’s instruction queue is based on first in first out (FIFO). So that the EU gets the
instructions for execution in the order they are fetched. If the queue is full and EU does not
request BIU for accessing memory, the BIU does not perform any bus cycle. On the other hand,
if the queue is not full and even through the EU does not request BIU for accessing the memory
the BIU can fill the queue on its own. If the EU interrupts the BIU, the BIU Ist completes the
prefetching and then attains to the service of the EU.
In case of JUMP and CALL instruction, instruction already fetched in queue are of no
use. Hence, in these cases queue is dumped and newly formed by loading instructions from new
address specified by JUMP or CALL instruction.

Execution Unit (EU) : The EU of 8086 tells the BIU from where to fetch instructions
or data, decodes instruction and executes instructions. It contains :
(i) Control Circuitry
(ii) Instruction Decoder
(iii) Arithmetic Logic Unit (ALU)
(iv) Flag register
(v) General purpose registers
(vi) Pointers and Index registers
The central circuitry in the EU directs the internal operation. A decoder in the EU
translates the instructions fetched from memory into a series of actions which the EU performs.
ALU is 6 bit. If can add, subtract, AND, OR, XOR, increment, decrements complement and
shift binary numbers.
More about Queue : In the beginning, the CS : IP is loaded with the required address
from which the execution is to be started. In the initial condition the queue will be empty and the
microprocessor starts a fetch operation to bring one byte (the first byte) of instruction code, if
the CS : IP address is odd, and two bytes at a time, if the CS : IP address is even. The first byte
is a complete opcode in case of some instructions(one byte opcode instructions), the remaining
part of opcode may lie in the second byte. But invariably the first byte of an instruction is an
opcode. These opcodes along with data are fetched and arranged in the queue. When the first
byte from the queue goes for decoding and interpretation, one byte in the queue becomes empty
and subsequently the queue is updated.
(i) The microprocessor does not perform the next fetched operation till at least two
bytes of the instruction queue are emptied. The instruction execution cycle is never broken for
fetch operation. After decoding the first byte the decoding circuit decides whether the instruction
is of single opcode byte or double opcode byte. If the single opcode bytes, the next bytes are
treated as data bytes depending upon the decoded instruction length. Otherwise, the next byte in
the queue is treated as the second byte of the instruction opcode.
90 Microprocessing & Interfacing

(ii) The queue is updated after every byte is read from the queue but the fetch cycle is
entreated by BIU only if at least two bytes of the queue are empty and the EU may be concurrently
executing the fetched instructions. Fig. shows the queue operation.

Fig : Queue operation

Q.4.(b) Discuss Pipelining. (5)
Ans. Pipelining : The process of fetching the next instruction, when the present
instruction is being executed is called as pipelining. Pipelining has become possible due to the use
of queue. BIU fills in the queue, until the entire queue is full. BIU restarts filling in the queue
when atleast two locations of queue are vacant.
Advantage of Pipelining :
(i) The EU always reads the next instruction byte from the queue in BIU. This is much
faster than sending out an address to the memory and waiting for the next instruction byte to
come.
(ii) In short pipelining eliminates the waiting time of EU and speeds up the processing.
(iii) The 8086 BIU will not initiate a fetch unless and until there are two empty bytes in
its queue. 8086 BIU normally obtains two instruction bytes per fetch.

Q.5.(a) Explain the block diagram of 8086 microprocessor. (10)

Ans. Block Diagram of 8086 : The block diagram of 8086 microprocessor is shown in
figure. As shown in block diagram, the 8086 is divided into two independent functional units. The
Bus interface Unit (BIU) and the Execution.
(i) The Bus Interface Unit : The Bus Interface unit fetches instructions from memory,
reads data from ports and memory and writes data to ports and memory. It handles all transfers
of data and addresses on the buses for the execution unit. The Bus interface Unit consists of the
following :
(a) Instruction Queue (b) Segment Registers (c) Instruction Pointer
B.Tech., 5th Semester, Solved papers, Dec -2016 91

(a) Instruction Queue : The instruction queue is a first-in-first-out group of registers.

To speed up program execution, the Bus Interface Unit fetches as many as six instruction bytes
are held for the Execution Unit in a Instruction Queue. The BIU can be fetching instruction
bytes while the Execution Unit (EU) is decoding the instruction or executing an instruction which
does not require use of the buses. When the Execution Unit is ready for its next instruction, it
simply reads the instruction from the Instruction Queue in the BIU. This scheme is much faster
than sending out an address to memory and then waiting for memory to send sack the next
instruction byte. The prefetch instruction and queue scheme greatly speeds up processing. The
arrangement of fetching the next instruction while the current instruction executes is called pipe
lining.

Fig. : Block diagram of 8086 microprocessor

(b) Segment Registers : The Big Interface Unit (BIU) contains four 16 bit segment
registers. They are :
– Code Segment Register (CS)
– Stock Segment Register (SS)
– Extra Segment Register (ES)
– Data Segment Register (DS)
92 Microprocessing & Interfacing

(c) Instruction Pointer : The instruction pointer register is a 16 bit register which holds
the address of the next code byte that is to be fetched within the code segment. This register
contains the address value which is an offset, because this value must be added to the segment
base address contained in CS register to produce the required 20 bit physical address.
(ii) The Execution Unit : The execution unit of 8086 performs the following major
operations :
– It tells the BIU, from where to fetch instructions or data.
– It decodes and executes instructions.
To perform the above operations, the execution unit consists of the following sections :
(a) Instruction Decoder, ALU and control circuitry.
(b) Flag Register
(c) General Purpose Registers
(d) Stack Pointer Register
(e) Other Pointer and Index Registers
(a) Instruction decoder, ALU and control circuitry : The instruction decoder in the
EU translate instructions fetched from memory into a series of actions which are further carried
out. The Arithmetic and Logic Unit (ALU) of 8086 is of 16 bits which can add, subtract, AND,
OR, XOR, increment, decrement, complement or shift the binary numbers. All internal operations
of EU are controlled by control circuitry.
(b) Flag register : 8086 microprocessor contains one 16 bit flag register (status register).
A flag register is a flip flop which indicates the status of some conditions produced by the
execution of an instruction or controls certain operations of the Execution Unit. In a 16 bit flag
register, there are nine active flags. Six of the nine flag bits are used to indicate some conditions
produced by an instructions. These six flags are called status flag (conditional flags). The remaining
three flag bits in the flag register are used to control certain operations of the processor and are
called control flags.
(c) General purpose registers : The execution unit 8086 contains eight general purpose
registers labelled as AH, AL, BH, BL, CH, CL, DH and DL in the fig. below.

Fig. : 8086 general purpose register

(d) Stack pointer register : The stack pointer register SP is a 16 bit register which
contains the 16 bit offset address from the start of the stack segment to the memory location
where a word was most recently stored on the stack. The stack memory location where a word
was most recently stored is called top of the stack.
(e) Other pointer and index registers : In addition to the stack pointer register SP, the
EU of the 8086 also contains a 16 bit base pointer register BR The base pointer register BP
contains the 16 bit offset address relative to the stack segment register SS but it is employed in
the based addressing mode of 8086.
B.Tech., 5th Semester, Solved papers, Dec -2016 93

Q.5.(b) How physical address is computated in 8086 microprocessor ? (10)

Ans. The generation of 20 bit physical address of the location in the code segment
which contains the next code byte.
(i) The sequence of operation is as follows.
Physical Address Generation :
Step 1: The CS register contains the upper 16 bits of the starting address of the code
segment.
 CS Register : 3 4 8 A Segment base

Step 2 : The BIU will automatically insert zeros for the lowest four bits of the segment
base address to get the 20 bit physical address for the starting of code segment.
 Starting address of code segment : 3 4 8 A 0
 BIU adds this zero
Step 3 : The I.P. register contains the offset or distance from this address. The offset
here is 4214H.
 I.P. Register : 4 2 1 4

Step 4 : Add the starting address of code segment (20 bit) to the offset to get the
physical address of the location containing the next code byte as follows :
Starting address of code segment  3 4 8 A 0  Hard wired 0
Offset in the I.P. Register + 4 2 1 4
Physical address of the location  3 8 A B 4
containing the next code byte
(ii) This 20 bit physical address is then sent out by the BIU to fetch the next code byte
stored at this location.
Alternative way to represent the physical address :
(i) An alternative way of representing a 20 bit physical address is as follows :
Segment base : Offset
(ii) For example the 20 bit physical address in the above example is 348 A : 4214.

SECTION – C
Q.6.(a) Explain directives and identifiers used in 8086 microprocessor. (10)
Ans. Directives used in assembly language program are as follows :
Directive Action
ALIGN aligns next variable or instruction to byte which is multiple of operand.
ASSUME selects segment register(s) to be the default for all symbol in segment(s)
COMMENT indicates a comment
DB allocates and optionally initializes bytes of storage
DW allocates and optionally initializes doublewords of storage
DD allocates and optionally initializes doublewords of storage
DQ allocates and optionally initializes quadwords of storage
DT allocates and optionally initializes 10-byte long storage units
94 Microprocessing & Interfacing

END terminates assembly; optionally indicates program entry point

ENDM terminates a macro definition
ENDP marks end of procedure definition
ENDS marks end of segment or structure
EQU assigns expression to name
EVEN aligns next variable or instruction to even byte
ESITM terminates macro expansion
EXTRN indicates externally defined symbols
LABEL creates a new label with specified type and current location counter
LOCAL declares local variables in macro definition
MACRO starts macro definition
MODEL specifies mode for asssembling the program
ORG sets location counter to argument
PAGE sets length and width of program listing; generates page break
PROG starts procedure definition
PTR assigns a specific type to a variable or to a label
PUBLIC identifies symbols to be visible outside module
TITLE defines the program listing title
Identifiers : An identifier is basically a name that is applied to an item in the program
for reference purpose.
An identifier is basically a symbol cased for reference is a program.
Basically these are two types of identifiers in 8086 p.
(i) NAME identifier : This type of identifiers identifies the item by name or can say
refers to the address of data item.
e.g. COUNTER (Name identifier) in Counter DBO.
(ii) Label Identifier : Refer to the address of an instruction, procedure or segment
e.g. MAIN PROC FAR MAIN  MAIN is label identifier.
B 30 : ADD BL, 30 B30 is label identifier
Maximum length of an identifier is 31 characters upto MASM 6.0 & 247.
Following characters can be used as Indentifies
(i) Alphabetic characters : - A to Z and a -z
(ii) Digit : 0 – 9 (but not as 1st character)
(iii) Special characters : ? _ $ @. (but not as 1st character)

Q.6.(a) Write a simple assembly program to subtract two memory location, where
each memory location is one byte wide. (10)
Ans. Assembly program :
Instruction Comments
LDA 4201 H ; Content of 4201 H loaded into Accumulator
MOV B, A ; Content of A copied to B register
LDA 4200 H ; Get the minuend in A register
MVI C, 00 H ; Clear C register to account for sign
SUB B ; Get the difference in A register
B.Tech., 5th Semester, Solved papers, Dec -2016 95

JNC AHEAD ; if CF = 0 then go the AHEAD

CMA ; Complement Accumulator
ADI 01 H ; 2’s complement of difference in A
AHEAD : STA 4202 H ; Store the result in memory
MOV A, C ;
STA 4203 H ; Store the sign bit in memory
HLT ; Halt program
End
Sample data :
Input data : Minuend = 5 EH
Subtrahend = 34H
Output data : Difference = 2AH
Sign Bit = 00H
Memory Address Content
4200 5EH
4201 34H
4202 2AH
4203 00H

Q.7.(a) Write short notes on directives and operators. (10)

Ans. Assembler directives : These are the statements that direct the assembler to do
something. As the name says, it direct the assembler to do a task. The speciality of these
statements is that they are effective only during the assembly of a program but they do not
generate any code that is machine executable. We can divide the assembler directives into two
categories namely the general purpose directives and the special directives. They are classified
into the following categories based on the functions performed by them.
(i) Simplified segment directives (ii) Data allocation directives
(iii) Segment directives (iv) Macros related directives
(v) Code label directives (vi) Scope directives
(vii) Listing control directives (viii) Miscellaneous directives

Fig : Assembly directives

96 Microprocessing & Interfacing

Operators : Various operators are as follows :

(i) Length : It is an operator which tells the assembler to determine the number of
elements in some named data item such as a string or array.
Example : MOV BX, LENGTH STRING 1; Loads the Length of string in BX.
(ii) OFFSET : It is an operator which tells the assembler to determine the offset or
displacement of a named data item (variable) from the start of the segment which contains.
Example : MOV AX, OFFSET MES1, : Loads the offset of variable, MESI in
AX register.
(iii) Short : A short is an operator. It tells the assembler that only 1-byte displacement is
needed to code a jump instruction. If the jump destination is after the jump instruction in the
program, the assembler will automatically reserve 2-bytes for the displacement. Using the short
operator saves 1-byte of memory by telling the assembler that it only needs to reserve 1-byte for
this particular jump. The short operator should be used only when the destination is fit the range
of -128 bytes of +127 bytes from the address of the instruction after the jump.
Example : IMP SHORT NEAR–LABEL
(iv) Type : It is an operator which tells assembler to determine the type of specified
variable. Assembler determines the type of specified variable in number of bytes. For byte types
variable the assembler gives a value of 1. For word type variable the assembler gives a value of
2 and for doubles word type variable the assembler gives a value of 4.

Q.7.(b) Write a 8086 assembly language program to find largest number in data
array. (10)
Ans. Program :
0201 BE, 00, 03 MOV SI, 0300H MEMORY ADDRESS IN SI
0204 8B, 0C MOV CX, [SI] COUNT IN CX
0206 B8, 00, 00 MOV AX, 0000 INITIAL VALUE 0000 FOR COMPARISON
0209 46 BCK INC SI INCREMENT SI
020A 46 INC SI INCREMENT SI
020B 3B, 04 CMP, AX, [SI] COMPARE PREVIOUS MAX. WITH
NEXT NUMBER
020D 73, 02 JAE GO JUMP IF NUMBER IN AX IS
GREATER
020F 8B, 04 MOV AX, [SI] SAVE NEW LARGER NUMBER IN AX
0211 E2, F6 GO LOOP BCK JUMP UNTIL CX = 0
0213 A3, 51, 03 MOV [0351], AX STORE LARGEST NUMBER IN
MEMORY
0216 CC INT 3 BREAKPOINT

SECTION – D
Q.8. Explain 8259 interrupt controller with the help of block diagram. (20)
Ans. The block diagram of 8259 is shown in fig.(a). It contains following blocks :
(i) Data bus buffer (ii) Read/write logic
(iii) Cascade buffer and comparator (iv) Control logic
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(v) IRR (Interrupt Request Register) (vi) InSR (In-Service Register)

(vii) Priority resolver (viii) IMR (Interrupt Mask Register)
(i) Data bus buffer : It is used to transfer data between microprocessor and internal
bus.
(ii) Read/Write control logic : It sets the direction of data bus buffer. It controls all
internal read/write operations. It contains initialization and operation command registers.
(iii) Cascaded buffer and comparator : In master mode, it functions as a cascaded
buffer. The cascaded buffers outputs slave identification number on cascade lines. In slave
mode, it functions as a comparator. The comparator reads slave identification number from
cascade lines and compares this number with its internal identification number. In buffered mode
it generates an EN signal.

Fig. (a) : Functional block diagram of 8259

(iv) Control logic : It generates an INT signal. In response to an INTA signal, it
releases three byte CALL address or one byte Vector number. It controls read/write control
logic, cascade buffer/comparator, in service register, priority resolver and IRR.
(v) Interrupt request register (IRR) : It is used to store all pending interrupt requests
. Each bit of this register is set at the rising edge or at the high level of the corresponding interrupt
request line. The microprocessor can read contents of this register by issuing appropriate, command
word.
(vi) In service register (InSR) : It is used to store all interrupt levels currently being
serviced. Each bit of this register is set by priority resolver and reset by End of interrupt command
word. The microprocessor can read contents of this register by issuing appropriate command
word.
(vii) Priority resolver : It determines the priorities of the bit set in the IRR. To make
decision, the priority resolver looks at the ISR. If the higher priority bit in the InSR is set then it
98 Microprocessing & Interfacing

ignores the new request. If the priority resolvers finds that the new interrupt has a higher priority
than the highest priority interrupt currently being serviced and the new interrupt is not in service,
then it will set appropriate bit in the InSR and send the INT signal to the microprocessor for new
interrupt request.
(viii) Interrupt mask register (IMR) : It is a programmable register. It is used to
Mask unwanted interrupt request, by writing appropriate command word. The microprocessor
can read contents of this register without issuing any command word.

Q.9. Explain the following : (20)

(a) 8253/8254 programmable interval timer.
(b) Instruction register and priority resolver.
Ans.(a) 8253/8254 programmable Interval timer : The 8253/8354 is an intelligent
Programmable Interval Timer/Counter (PIT). It is available in 24-pin DIP package using nMOS
technology and operates with +5V power supply. It has three 16-bit presettable down counters.
Each of the 3-counters can operate either in binary or BCD mode. Each counter has 2-inputs :
Clock (CLK) and Gate (GATE) and one Output (OUT). Various functions of the 8253/8254 are
as follows :
(i) As event counter,
(ii) As programmable rate generator,
(iii) As binary rate multiplier,
(iv) As digital mono shot,
(v) As complex motor controller.
Pinout and Block Diagram : The pin outs and its internal details in the form of block
diagram is shown in fig.(a) and fig.(b) respectively. Each one of the 3-counters of the 8253 is
capable of counting from DC to 2 MHz. The input clock is fed to its CLK terminal with the
frequency < 2 MHz. The functions of the GATE and OUT terminals depends on the mode and
setting of the particular counter.

Fig.(a) : Pinouts of 8253

B.Tech., 5th Semester, Solved papers, Dec -2016 99

The 8254 has exactly the same pinout as that of the 8253. But the 8254 differs from that
of the 8253 in 2 ways, namely,
(i) no read back  Once the particular counter of the 8253 is programmed, its status
can not be read back.
(ii) The maximum clock frequency it can count is limited to 2 MHz. The upper limit of
clock frequency of 8254 is 8 MHz and that of the 8254-2 is 10 MHz.

Fig.(b) : Block diagram of 8253/8254 programmable interval timer

– Electrical characteristics : The access time of the 8254 is 200ns where as the
access time of the 8254-2 is 175ns. The GATE and CLK inputs present 10 A load and OUT
output can source 400 A in the high state and sink 2 mA in the low state.
– Data bus buffer : The 8-bit tri-state data buffer has 3-basic functions :
(a) Programming different modes of the 8253/8254,
(b) Loading the count register, and
(c) Reading the count value.
– Read/write control logic : The 8253/8254 has 5-signals, namely, CS , A0, A1, RD ,
WR . The functions of these control signals are :
(a) RD (Read Bar) : A low on this pin informs the 8253/8254 that the P is ready to
accept data in the form count value.
(b) WR (Write Bar) : A low on this pin informs the 8253/8254 that the P is ready to
output data in the form of mode informations or data.
Hence, in the isolated I/O mode, RD and WR are directly connected to IOR and
IOW . On the other hand, in the memory mapped I/O, RD and WR are connected to MEMR
and MEMW respectively..
100 Microprocessing & Interfacing

(c) CS (Chip select Bar) : The 8253/8254 is selected only when a low (0) is applied at
this terminal. No reading or writing operations will be performed by or on the 8253/8254 unless
this chip is selected. The CS = 1 does effect the operation of the counters.
(d) A1 A0 (Address Pin) : These lines (A1 A0) are connected to the address bus. The
function of A1 and A0 are to select any one of the three counters and the control word register of
8253/8254 is indicated in below table :
Table : Selection of counter and CWR
A1 A0 Selection of counter
0 0 Counter-0 Selected
0 1 Counter-1 Selected
1 0 Counter-2 Selected
1 1 Control word register selected (CWR)

– Control word Register : As indicated in above table, the control word register is
selected only when A1A0 = 11. It is loaded with the formation of the control word to indicate
which particular counter is to be used in which mode and whether READ and WRITE operation
is to be performed.

Ans.(b) Instruction Register : This register is not accessible to the user. The instruction
register holds the opcode of the instruction that is decoded and executed.
The opcode is further sent to the instruction decoder to select one of the 256 alternatives
(operations). The contents of the instruction decoder are in the form of 0’s and 1’s.
Priority resolver : It determines the priorities of the bit set in the IRR. To make
decision, the priority resolver looks at the ISR. If the higher priority bit in the InSR is set then it
ignores the new request. If the priority resolvers finds that the new interrupt has a higher priority
than the highest priority interrupt currently being serviced and the new interrupt is not in service,
then it will set appropriate bit in the InSR and send the INT signal to the microprocessor for new
interrupt request.